TWI415256B - 電力半導體裝置 - Google Patents

電力半導體裝置 Download PDF

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TWI415256B
TWI415256B TW099142542A TW99142542A TWI415256B TW I415256 B TWI415256 B TW I415256B TW 099142542 A TW099142542 A TW 099142542A TW 99142542 A TW99142542 A TW 99142542A TW I415256 B TWI415256 B TW I415256B
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insulating film
semiconductor substrate
gate
semiconductor device
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TW201133838A (en
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Sigeto Honda
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Mitsubishi Electric Corp
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Description

電力半導體裝置
本發明是有關於電力半導體裝置，特別是有關於具有終端構造的高耐壓型的電力半導體裝置。
高耐壓的二極體、雙極電晶體、電源MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)、IGBT(Insulated Gate Bipolar Transistor)等高耐壓型的電力半導體裝置的終端部之中，為了緩和主接合表面附近的空乏層端部的電場，已經有藉著具有中介著絕緣膜在半導體基板上設置導電膜(場效平板)的場效平板構造、在半導體基板的表面附近選擇性地設置與基板不同導電型的低濃度擴散層的RESURF(Reduced Surface Field)層，以提升元件耐壓的技術。場效平板構造為中介著氧化膜在例如RESURF層上設置Al-Si膜的構造，且特別是藉由設置於電場容易集中的主接合區域周邊的p型層與RESSURF層的接合區域上，所以使該接合區域附近的電場緩和，而可提升元件耐壓。
在場效平板構造之中，場效平板下的絕緣膜的膜厚薄的情況，在場效平板端部會產生累積崩潰(Avalanche)，而元件耐壓會降低，所以有必要使絕緣膜的膜厚變厚。然而，形成絕緣膜的話，會成為晶圓製程時的高度落差(比起未形成絕緣膜的區域，整體的膜厚會變厚)，所以絕緣膜的膜厚變厚的話，會產生光阻塗佈時的光阻塗佈不均一，再者，會產生照相製版時的聚焦裕度的確保變得困難等的問題。
為了解決上述問題，本申請案申請人已提案使場效平板下的絕緣膜形成於半導體基板內的終端構造。該終端構造是在半導體基板形成凹陷區域後，在半導體基板全面性地形成絕緣膜，再以CMP(Chemical Mechanical Polishing)處理沈積後的表面以平坦化而形成。再者，有在形成於半導體基板表面的RESURF層形成凹陷區域，再將絕緣膜填充於該凹陷區域的終端構造(例如，參照特許文獻1)。
特許文獻1：特開2009-88385號公報
具有凹陷區域，且在該凹陷區域形成絕緣膜的終端構造，在半導體基板全面性地沈積絕緣膜，進行CMP處理時，為了防止對半導體基板造成的損傷，有必要在包含電晶體晶胞區域(cell)的凹陷區域以外的區域(非凹陷區域)上，留下沈積的絕緣膜。然而，CMP處理後的絕緣膜的膜厚分佈，對於被凹陷區域包圍的非凹陷區域的面積具有依存性，非凹陷區域的面積愈廣，膜厚分佈會變得愈大(膜厚的變動變大)。膜厚的變動變大時，結果會產生特性變動的問題。
有鑑於上述這些問題，本發明的目的在於提供一種電力半導體裝置，能夠減低CMP處理後的絕緣膜的膜厚的變動，而減低特性的變動。
為了解決上述課題，本發明的電力半導體裝置，其為在填充於形成在半導體基板的第1凹陷區域的絕緣膜上具有設置場效平板的終端構造，且並聯複數個單位晶胞的電力半導體裝置，包括：配置與上述複數個單位晶胞的各個閘極電極電性連接的閘極導線區域；以及與上述閘極導線區域電性連接的閘極墊區域；其特徵在於：上述閘極導線區域是配置在填充於形成在半導體基板的第2凹陷區域的上述絕緣膜上。
根據本發明，在填充於形成在半導體基板第1凹陷區域的絕緣膜上具有設置場效平板的終端構造，且並聯複數個單位晶胞的電力半導體裝置，包括：配置與上述複數個單位晶胞的各個閘極電極電性連接的閘極導線區域；以及與上述閘極導線區域電性連接的閘極墊區域，由於閘極導線區域是配置在填充於形成在半導體基板的第2凹陷區域的上述絕緣膜上，所以能夠減低CMP處理後的絕緣膜的膜厚的變動，而減低特性的變動。
以下根據圖式，以說明本發明之實施形態。
<前提技術>
首先，說明作為本發明的前提的技術。
第8圖為一般IGBT的晶片佈局的一個例子的上視圖。第8圖雖然顯示IGBT的一個例子，然而如第8圖所示，具有電源MOSFET、IGBT等的閘極機能的高耐壓型的電力半導體裝置設有導線區域12，使得包圍電晶體單元區域10。電力半導體裝置的控制電流高、且電晶體單元區域的面積大的情況，在電晶體單元區域的中央部的有效閘極電阻會變高，而成為開關速度降低、破壞耐量降低的問題。因此，如第1圖所示，將電晶體單元區域10分割成複數個單位，藉由這些單位晶胞並聯而形成一元件，以縮小被閘極導線區域12包圍著的電晶體晶胞區域10的面積。並且，11以及13分別為終端區域以及閘極墊。
第9圖為前提技術之電力半導體裝置的閘極導線區域的剖面圖。如第9圖所示，D-Poly等形成的閘極電極4與Al-Si電極6等形成的閘極導線，為了與n型矽半導體基板1電性絕緣，配置於形成於n型矽半導體基板1上的絕緣膜3上。再者，藉由在閘極電極4下，於n型矽半導體基板1的表面附近形成P型井區域2，可提升相對於閘極電極4與n型矽半導體基板1之間的漏電的耐壓。
第10圖為顯示根據本申請案申請人之前提技術，使場效平板(field plate)下的絕緣膜形成於矽半導體基板所形成的凹陷區域內形成的終端構造之例子的圖式。如第10圖所示，絕緣膜23填充於形成在n型矽半導體基板1的凹陷區域內。再者，在凹陷區域下形成有p型RESURF區域21，p型RESURF區域21上中介著絕緣膜23而設有Al-Si電極26(場效平板)。再者，n型矽半導體基板1的表面附近形成有p型陽極區域20，在p型陽極區域20上設有陽極電極22。並且，n型矽半導體基板1的表面附近、Al-Si電極26 下方形成有n型通道停止區域24，而n型矽半導體基板1的背面設有陰極電極25。
第11圖以及第12圖為顯示上述前提技術，將絕緣膜沈積2μm後的CMP處理後的絕緣膜的膜厚分佈的圖，第11圖顯示電晶體晶胞區域為5mm□(5mm×5mm)、第12圖顯示電晶體晶胞區域為10mm□(10mm×10mm)的情況絕緣膜的分佈。如第11圖以及第12圖所示，可得知非凹陷區域的電晶體晶胞區域較廣的話，CMP處理後的膜厚分佈會變大(膜厚的變動會變大)。因此，如前述，膜厚的變動若變大，會因而產生特性的變動的問題。
本發明是為了解決上述問題，以下詳細地說明。
<實施形態1>
第1圖為顯示本發明實施形態1之電力半導體裝置的閘極導線區域構造的剖面圖。並且，以下，本實施形態之電力半導體裝置是以例如第8圖所示的一般晶片佈局配置，如第10圖所示，具有在填充於形成在半導體基板的凹陷區域(第1凹陷區域)的絕緣膜上設有場效平板的終端區域11(終端構造)，且複數個電晶體晶胞區域10(單位晶胞)並聯著。其次，在閘極導線區域12，配置著分別與複數個電晶體晶胞區域10各別的閘極電極電性連接的閘極導線，且閘極墊13(閘極墊區域)與閘極導線區域12電性連接著。
如第1圖所示，本實施形態之電力半導體裝置的閘極導線區域，在形成於n型矽半導體基板1(半導體基板)的表面附近的p型井區域2設有凹陷區域，在凹陷區域內填充著絕緣膜3，使得與n型矽半導體基板1的表面成為同一平面。絕緣膜3上設有閘極電極4、層間膜5、Al-Si電極6，n型矽半導體基板1的背面依序設有p型集極層7、集極電極8。亦即，相較於習知技術(例如，第9圖)，本實施形態1的電力半導體裝置的閘極導線區域的特徵在於，Al-Si電極6(閘極導線區域)是配置在填充於形成在n型矽半導體基板1的凹陷區域(第2凹陷區域)的絕緣膜3上。
在形成於n型矽半導體基板1的凹陷區域(第2凹陷區域)填充絕緣膜3的構造與在終端構造中於凹陷區域(第1凹陷區域)填充絕緣膜的構造相同，所以兩構造可同時形成。亦即，兩構造填充的絕緣膜3是相同的。
終端構造形成時，首先一開始，藉由照相製版處理以在n型矽半導體基板1上形成光阻圖案之後，藉由乾蝕刻等以在n型矽半導體基板1形成凹陷區域(第1以及第2凹陷區域)。其次，藉由CVD(Chemical Vapor Deposition)法等在n型矽半導體基板1上全面性地沈積絕緣膜3之後，以CMP處理進行表面的平坦化。CMP處理時，為了防止對n型矽半導體基板1的損傷，有必要留下在凹陷區域以外的區域(包含電晶體晶胞區域10的非凹陷區域)上沈積的絕緣膜3。非凹陷區域變廣的話，CMP處理後的絕緣膜3的膜厚的變動會變大，然而在閘極導線區域12下方，與終端構造同樣地形成凹陷區域，如第8圖所示的佈局，由於各電晶體晶胞區域10是藉由閘極導線區域12分割成複數個區域(非凹陷區域也藉由閘極導線下的凹陷區域)，所以可減低n型矽半導體基板1的表面的整體的絕緣膜3的膜厚的變動。
如上所述，在閘極導線區域下形成凹陷區域，再藉由在該凹陷區域填充絕緣膜，可減低CMP處理後絕緣膜的膜厚變動，使減低電力半導體裝置的特性的變動成為可能。再者，由於閘極電極4下的絕緣膜3是填充於n型矽半導體基板1的凹陷區域，所以可減低晶圓製程時，由絕緣膜3導致的高度落差，而提升照相製版的聚焦裕度(focus margin)。
<實施形態2>
第2圖為顯示本發明實施形態2之電力半導體裝置的閘極導線區域構造的剖面圖。如第2圖所示，本發明的實施形態2的特徵在於，在形成於n型矽半導體基板1的凹陷區域(第2凹陷區域)下，設置以注入量大約1.0E12atoms/cm2 的離子注入所形成的低不純物濃度的p型井區域9(第2不純物區域)。其他構造與實施形態1相同，所以省略其說明。
在終端構造為RESURF構造的情況，在終端構造的凹陷區域(第1凹陷區域)下以注入量大約1.0E12atoms/cm2 的離子注入所形成的p型RESURF層(第1的不純物區域)。藉由使p型RESURF層與p型井區域9的不純物濃度成為相同(亦即，較電晶體晶胞區域10的p型活性區域還低不純物濃度的p型區域)，可省略為了Al-Si電極6(閘極導線區域)下的p型井區域9的形成必要的照相製版處理以及離子植入處理。
如上所述，除了實施形態1的效果以外，可省略為了p型井區域9的形成必要的照相製版處理以及離子植入處理。
(實施形態3)
本發明的實施形態3的特徵在於，Al-Si電極6(閘極墊區域)是配置在填充於形成在n型矽半導體基板1(半導體基板)的凹陷區域(第3凹陷區域)的絕緣膜3上。
第4圖為顯示習知電力半導體裝置的閘極墊的構造剖面圖。如第4圖所示，習知技術是在n型矽半導體基板1上、中介著絕緣膜3以及層間膜5配置Al-Si電極6(閘極墊區域)。在Al-Si電極6上藉由導線接合等電性連接閘極驅動電路。如上述所述，習知形成於n型矽半導體基板1上的絕緣膜的膜厚為絕緣膜3的膜厚與層間膜5的膜厚的總和，所以具有晶圓製程時因絕緣膜圖案使高度落差變大的問題。
針對上述問題，第3圖所示的本實施形態3的電力半導體裝置的閘極墊之中，在Al-Si電極6(閘極墊區域)下，填充著形成於n型矽半導體基板1的凹陷區域的絕緣膜3。因此，可減低晶圓製程時因絕緣膜圖案導致的高度落差。並且，此時的閘極導線區域為本實施形態1或2任一者皆可。
如上所述，藉由將Al-Si電極6配置於形成在n型矽半導體基板1的凹陷區域的絕緣膜3上的構造，可減低晶圓製程時絕緣膜圖案導致的高度落差。
並且，本實施形態3的閘極導線區域為本實施形態1或2其中之一的構造。
(實施形態4)
第5圖為具有溫度感測二極體的一般IGBT的晶片佈局區域的一個例子的上視圖。第8圖為一般IGBT的晶片佈局具有溫度感測二極體區域14以及溫度感測二極體墊15。再者，第6圖為本發明實施形態4之電力半導體裝置的溫度感測二極體區域14的構造剖面圖。
如第5圖以及第6圖所示，在溫度感測二極體區域14，配置有摻雜的多晶矽膜16等構成的薄膜PN二極體之溫度感測二極體。PN二極體在輸出特性方面具有溫度依存性，藉由監測溫度感測二極體的輸出特性，可監測本實施形態4的電力半導體裝置的溫度。再者，溫度感測二極體墊15為用以電性連接溫度感測二極體區域14與外部控制電路所設置的電極墊。
再者，如第6圖所示，摻雜的多晶矽膜16(溫度感測二極體區域14)是形成於位於n型矽半導體基板1的凹陷區域(第4凹陷區域)的絕緣膜3上。再者，雖然圖未顯示，然而溫度感測二極體墊15是配置於形成在n型矽半導體基板1的凹陷區域(第5凹陷區域)的絕緣膜3上。
本實施形態4的溫度感測二極體區域的構造(第6圖)與習知的溫度感測二極體區域的構造(第7圖)比較，習知的絕緣膜3是形成於n型矽半導體基板1上，所以晶圓製程時會產生絕緣膜3的圖案導致的落差。然而，本實施形態4的絕緣膜3是填充於形成在n型矽半導體基板1的凹陷區域之中，所以可減低晶圓製程時的絕緣膜圖案而導致的高度落差。
如上所述，藉由將溫度感測二極體區域14以及溫度感測二極體墊15各自配置在填充於形成在n型矽半導體基板1的凹陷區域(第4、第5凹陷區域)的絕緣膜3上的構造，可減低晶圓製程時的絕緣膜圖案導致的高度落差。
並且，本實施形態4之中的閘極導線區域以及閘極墊為本實施形態1~3其中之一或者其組合的構造。
(實施形態5)
本發明的實施形態5的特徵在於，使用碳化矽(SiC)基板、氮化鎵(GaN)基板等矽半導體基板以外的半導體基板，取代本實施形態1~4的矽半導體基板。
如上所述，即使使用矽半導體基板以外的半導體基板，可得到與實施形態1~4同樣的效果。
1．．．n型矽半導體基板
2．．．p型井區域
3．．．絕緣膜
4．．．閘極電極
5．．．層間膜
6．．．Al-Si電極
7．．．p型集極層
8．．．集極電極
9．．．p型井區域
10．．．電晶體晶胞區域
11．．．終端區域
12．．．閘極導線區域
13．．．閘極墊
14．．．溫度感測二極體區域
15．．．溫度感測二極體墊
16．．．摻雜多晶矽膜
20．．．p型陽極區域
21．．．p型RESURF區域
22．．．陽極
24．．．n型通道停止區域
25．．．陰極電極
26．．．Al-Si電極
第1圖為顯示本發明實施形態1之電力半導體裝置的閘極導線區域構造的剖面圖。
第2圖為顯示本發明實施形態2之電力半導體裝置的閘極導線區域構造的剖面圖。
第3圖為顯示本發明實施形態3之電力半導體裝置的閘極導線區域構造的剖面圖。
第4圖為顯示習知電力半導體裝置的閘極墊的構造剖面圖。
第5圖為具有溫度感測二極體的一般IGBT的晶片佈局區域的一個例子的上視圖。
第6圖為本發明實施形態4之電力半導體裝置的溫度感測二極體區域的構造剖面圖。
第7圖為習知電力半導體裝置的溫度感測二極體區域的構造剖面圖。
第8圖為一般IGBT的晶片佈局的一個例子的上視圖。
第9圖為前提技術之電力半導體裝置的閘極導線區域的剖面圖。
第10圖為顯示前提技術之終端構造的一個例子。
第11圖為顯示前提技術的CMP處理後的絕緣膜的膜厚分佈的圖。
第12圖為顯示前提技術的CMP處理後的絕緣膜的膜厚分佈的圖。
1．．．n型矽半導體基板
2．．．p型井區域
3．．．絕緣膜
4．．．閘極電極
5．．．層間膜
6．．．Al-Si電極
7．．．p型集極層
8．．．集極電極

Claims (5)

  1. 一種電力半導體裝置，其為在填充於形成在半導體基板<1>的第1凹陷區域的絕緣膜<3>上具有設置場效平板的終端構造，且並聯複數個單位晶胞<10>的電力半導體裝置，包括：配置與上述複數個單位晶胞<10>的各個閘極電極電性連接的閘極導線區域<12>；以及與上述閘極導線區域<12>電性連接的閘極墊區域<13>；其特徵在於：上述閘極導線區域<12>是配置在填充於形成在半導體基板<1>的第2凹陷區域的上述絕緣膜<3>上，其中上述第1凹陷區域下及第2凹陷區域下分別設置第1不純物區域及第2不純物區域<9>；上述第1不純物區域及第2不純物區域<9>各自為比起上述單位晶胞的P型活性區域還低的不純物濃度的P型區域。
  2. 如申請專利範圍第1項所述之電力半導體裝置，其中上述第1不純物區域及上述第2不純物區域<9>各自為注入量大約1.0E12atoms/cm2 的離子注入所形成。
  3. 如申請專利範圍第1項所述之電力半導體裝置，其中上述閘極墊區域<13>是配置在填充於形成在半導體基板<1>的第3凹陷區域的上述絕緣膜<3>上。
  4. 如申請專利範圍第1項所述之電力半導體裝置，更 包括配置溫度感測二極體之溫度感測二極體區域<14>以及與該溫度感測二極體區域<14>電性連接的溫度感測二極體墊<15>，上述溫度感測二極體區域<14>配置在填充於形成在半導體基板<1>的第4凹陷區域的上述絕緣膜<3>上，且上述溫度感測二極體墊<15>配置在填充於形成在半導體基板<1>的第5凹陷區域的上述絕緣膜<3>上。
  5. 如申請專利範圍第1項所述之電力半導體裝置，其中上述半導體基板<1>為矽(Si)基板、碳化矽(SiC)基板、氮化鎵(GaN)基板的其中之一。
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JP2011210801A (ja) 2011-10-20
JP5601863B2 (ja) 2014-10-08
US20110233544A1 (en) 2011-09-29
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