CN101960586B - 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法 - Google Patents

使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法 Download PDF

Info

Publication number
CN101960586B
CN101960586B CN2008801275042A CN200880127504A CN101960586B CN 101960586 B CN101960586 B CN 101960586B CN 2008801275042 A CN2008801275042 A CN 2008801275042A CN 200880127504 A CN200880127504 A CN 200880127504A CN 101960586 B CN101960586 B CN 101960586B
Authority
CN
China
Prior art keywords
substrate
stiffener
chip
hole
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008801275042A
Other languages
English (en)
Chinese (zh)
Other versions
CN101960586A (zh
Inventor
泽基·切利克
扎菲尔·库特卢
维萨·山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
LSI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Corp filed Critical LSI Corp
Publication of CN101960586A publication Critical patent/CN101960586A/zh
Application granted granted Critical
Publication of CN101960586B publication Critical patent/CN101960586B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
CN2008801275042A 2008-02-28 2008-11-20 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法 Active CN101960586B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/038,911 US7968999B2 (en) 2008-02-28 2008-02-28 Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
US12/038,911 2008-02-28
PCT/US2008/012957 WO2009108171A1 (en) 2008-02-28 2008-11-20 Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive

Publications (2)

Publication Number Publication Date
CN101960586A CN101960586A (zh) 2011-01-26
CN101960586B true CN101960586B (zh) 2012-07-18

Family

ID=41012540

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008801275042A Active CN101960586B (zh) 2008-02-28 2008-11-20 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法

Country Status (7)

Country Link
US (1) US7968999B2 (enExample)
EP (1) EP2248165B1 (enExample)
JP (1) JP5226087B2 (enExample)
KR (1) KR101177039B1 (enExample)
CN (1) CN101960586B (enExample)
TW (1) TWI379364B (enExample)
WO (1) WO2009108171A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090321925A1 (en) * 2008-06-30 2009-12-31 Gealer Charles A Injection molded metal ic package stiffener and package-to-package interconnect frame
US8247900B2 (en) * 2009-12-29 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip package having enhanced thermal and mechanical performance
US9254532B2 (en) 2009-12-30 2016-02-09 Intel Corporation Methods of fabricating low melting point solder reinforced sealant and structures formed thereby
US20110292612A1 (en) * 2010-05-26 2011-12-01 Lsi Corporation Electronic device having electrically grounded heat sink and method of manufacturing the same
US8823407B2 (en) 2012-03-01 2014-09-02 Integrated Device Technology, Inc. Test assembly for verifying heat spreader grounding in a production test
US9041192B2 (en) * 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
US8946871B2 (en) 2012-11-07 2015-02-03 Lsi Corporation Thermal improvement of integrated circuit packages
US9607951B2 (en) 2013-08-05 2017-03-28 Mediatek Singapore Pte. Ltd. Chip package
US9282649B2 (en) * 2013-10-08 2016-03-08 Cisco Technology, Inc. Stand-off block
US9735043B2 (en) 2013-12-20 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and process
CN105514080B (zh) * 2014-10-11 2018-12-04 意法半导体有限公司 具有再分布层和加强件的电子器件及相关方法
US9460980B2 (en) * 2015-02-18 2016-10-04 Qualcomm Incorporated Systems, apparatus, and methods for heat dissipation
JP6569375B2 (ja) * 2015-08-11 2019-09-04 株式会社ソシオネクスト 半導体装置、半導体装置の製造方法及び電子装置
US20170053858A1 (en) * 2015-08-20 2017-02-23 Intel Corporation Substrate on substrate package
US20170170087A1 (en) 2015-12-14 2017-06-15 Intel Corporation Electronic package that includes multiple supports
US20170287799A1 (en) * 2016-04-01 2017-10-05 Steven A. Klein Removable ic package stiffener
CN107708328A (zh) * 2017-06-27 2018-02-16 安徽华东光电技术研究所 提高芯片充分接地和散热的焊接方法
JP6579396B2 (ja) * 2017-07-18 2019-09-25 株式会社ダイレクト・アール・エフ 半導体装置、及び基板
US20190206839A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Electronic device package
US11081450B2 (en) * 2019-09-27 2021-08-03 Intel Corporation Radiation shield around a component on a substrate
CN115116860B (zh) * 2022-06-17 2025-10-28 北京比特大陆科技有限公司 芯片封装方法及芯片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841194A (en) * 1996-03-19 1998-11-24 Matsushita Electric Industrial Co., Ltd. Chip carrier with peripheral stiffener and semiconductor device using the same
US6528892B2 (en) * 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
CN1755721A (zh) * 2004-10-01 2006-04-05 微软公司 组件化和可扩展的工作流模型

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736074A (en) * 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
JP2770820B2 (ja) * 1996-07-01 1998-07-02 日本電気株式会社 半導体装置の実装構造
US6051888A (en) * 1997-04-07 2000-04-18 Texas Instruments Incorporated Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package
US6011304A (en) * 1997-05-05 2000-01-04 Lsi Logic Corporation Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid
US6114761A (en) 1998-01-20 2000-09-05 Lsi Logic Corporation Thermally-enhanced flip chip IC package with extruded heatspreader
JP2000114413A (ja) * 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
US6985363B2 (en) * 2000-10-02 2006-01-10 Matsushita Electric Industrial Co., Ltd. Card type recording medium and production method therefor
US6639321B1 (en) 2000-10-06 2003-10-28 Lsi Logic Corporation Balanced coefficient of thermal expansion for flip chip ball grid array
US6407334B1 (en) * 2000-11-30 2002-06-18 International Business Machines Corporation I/C chip assembly
KR100394809B1 (ko) 2001-08-09 2003-08-14 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US6472762B1 (en) 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
US6987032B1 (en) * 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
JP4639600B2 (ja) * 2004-02-04 2011-02-23 凸版印刷株式会社 半導体パッケージ
JP2006013029A (ja) * 2004-06-24 2006-01-12 Toppan Printing Co Ltd 半導体パッケージ
JP4860994B2 (ja) * 2005-12-06 2012-01-25 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841194A (en) * 1996-03-19 1998-11-24 Matsushita Electric Industrial Co., Ltd. Chip carrier with peripheral stiffener and semiconductor device using the same
US6528892B2 (en) * 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
CN1755721A (zh) * 2004-10-01 2006-04-05 微软公司 组件化和可扩展的工作流模型

Also Published As

Publication number Publication date
TWI379364B (en) 2012-12-11
EP2248165B1 (en) 2017-01-18
JP2011513970A (ja) 2011-04-28
KR101177039B1 (ko) 2012-08-27
KR20100126708A (ko) 2010-12-02
EP2248165A4 (en) 2012-04-18
WO2009108171A1 (en) 2009-09-03
TW200937539A (en) 2009-09-01
US20090218680A1 (en) 2009-09-03
US7968999B2 (en) 2011-06-28
CN101960586A (zh) 2011-01-26
JP5226087B2 (ja) 2013-07-03
EP2248165A1 (en) 2010-11-10

Similar Documents

Publication Publication Date Title
CN101960586B (zh) 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法
KR100734816B1 (ko) 전자 소자 캐리어를 위한 최적화된 덮개의 장착
KR100384260B1 (ko) 반도체장치 및 그 제조방법
TWI529878B (zh) 集成電路封裝件及其裝配方法
CN100499052C (zh) 平面栅格阵列封装器件及其制作方法
US6356453B1 (en) Electronic package having flip chip integrated circuit and passive chip component
CN1181524C (zh) 在圆片面上形成集成电路封装的方法
US6546620B1 (en) Flip chip integrated circuit and passive chip component package fabrication method
JP2003068931A (ja) 半導体パッケージ及びその製造方法
CN103779302B (zh) 具有大焊盘的封装集成电路及其形成方法
JP3622435B2 (ja) 半導体装置とその製造方法
US7833837B2 (en) Chip scale package and method for manufacturing the same
US6819566B1 (en) Grounding and thermal dissipation for integrated circuit packages
CN101252108A (zh) 具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法
JP3565090B2 (ja) 半導体装置の製造方法
TW201207961A (en) Semiconductor package device using underfill material and packaging method thereof
JP2003100948A (ja) 半導体装置及びその製造方法
JP2003347352A (ja) 不導体接着材によって基板にicチップをボンディングする方法、および、この方法により形成されたアセンブリ
US7235429B2 (en) Conductive block mounting process for electrical connection
JP2010157610A (ja) 半導体装置
JPS6095943A (ja) プラグインパツケ−ジとその製造方法
JPH0851128A (ja) バンプトアレイtabパッケージ
JPS5951140B2 (ja) 半導体装置
CN101226910A (zh) 一致化凸块接合高度的高频集成电路封装构造及制造方法
KR20020043755A (ko) 반도체 패키지의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160725

Address after: Singapore Singapore

Patentee after: Avago Technologies General IP (Singapore) Pte. Ltd.

Address before: California, USA

Patentee before: LSI Corp.