CN101930986B - 半导体器件、摄像机模块及半导体器件的制造方法 - Google Patents

半导体器件、摄像机模块及半导体器件的制造方法 Download PDF

Info

Publication number
CN101930986B
CN101930986B CN2010102132755A CN201010213275A CN101930986B CN 101930986 B CN101930986 B CN 101930986B CN 2010102132755 A CN2010102132755 A CN 2010102132755A CN 201010213275 A CN201010213275 A CN 201010213275A CN 101930986 B CN101930986 B CN 101930986B
Authority
CN
China
Prior art keywords
mentioned
semiconductor substrate
semiconductor device
metal film
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2010102132755A
Other languages
English (en)
Other versions
CN101930986A (zh
Inventor
松尾美惠
萩原健一郎
小松公
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN101930986A publication Critical patent/CN101930986A/zh
Application granted granted Critical
Publication of CN101930986B publication Critical patent/CN101930986B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • H01L27/14627Microlenses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685Process for coatings or optical elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125Reinforcing structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0235Shape of the redistribution layers
    • H01L2224/02351Shape of the redistribution layers comprising interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01038Strontium [Sr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0106Neodymium [Nd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

本发明提供一种半导体器件、摄像机模块及半导体器件的制造方法。半导体器件具备:半导体基板,在第1面上形成半导体元件;布线图形,形成于上述半导体基板的与上述第1面相反侧的第2面侧,至少在一部分包含接地线;贯通电极,从上述第1面到上述第2面贯通上述半导体基板,电连接上述半导体元件和上述布线图形;以及金属膜,形成于上述半导体基板的上述第2面与上述布线图形所延伸存在的面之间,与上述接地线电连接。

Description

半导体器件、摄像机模块及半导体器件的制造方法
相关申请的交叉引用
本申请享有2009年6月22日所申请的日本专利申请2009-148098的优先权,该日本专利申请的全部内容在本申请中引用。
技术领域
本发明涉及半导体器件、摄像机模块及半导体器件的制造方法,特别涉及使用固体摄像元件的半导体器件、摄像机模块及半导体器件的制造方法。
背景技术
近年来,随着电子设备的小型化及轻型化,特别是便携式电话机等所使用的摄像机模块小型化的要求日渐增高。与之相伴,作为摄像机模块的封装,采用具备BGA(球栅阵列:Ball Grid Array)型端子的CSP(芯片尺寸封装:Chip Scale Package)构造的封装的情况越发增多。对于具备BGA型端子的摄像机模块而言,例如在半导体基板上的与形成摄像元件的面(以下将其称为上面)相反侧的面(以下将其称为背面)上形成布线图形,经由基板内或者侧面上所形成的电极来电连接基板背面的布线图形和基板上面的摄像元件。借此,可以将形成摄像元件后的半导体基板薄形化,结果,使摄像机模块进一步的小型化及薄形化成为可能(例如参见日本特开2007-189198号公报)。
但是,在采用现有技术的摄像机模块中,来自基板背面的光经过基板入射于其上面所形成的摄像元件上,发生在摄像图像上产生重影(ghost)或者映入基板背面的布线图形等问题。作为解决这种问题的技术,存在一种例如在基板背面上形成遮挡来自被摄体以外的光的光反射层或光吸引层的技术(例如参见日本特开2007-189198号公报)。
但是,对于上述以往那种把与基板上面所形成的摄像元件之间的电连接利用贯通基板的贯通电极引出基板背面的结构来说,在半导体基板和基板背面的布线图形之间产生寄生电容及寄生电阻,因此高频信号的波形变钝。为此,产生难以使固体摄像元件高速工作这样的问题。这种问题即便用金属层形成例如形成于基板背面的遮光用层,也无法解决。也就是说,即便在基板背面上形成了金属层,也因为该金属层电浮动,所以上述那种因寄生电容及寄生电阻而产生的问题得不到解决。
发明内容
半导体器件具备:半导体基板,在第1面上形成半导体元件;布线图形,形成于上述半导体基板的与上述第1面相反侧的第2面侧,至少在一部分中包含接地线;贯通电极,从上述第1面到上述第2面贯通上述半导体基板,电连接上述半导体元件和上述布线图形;以及金属膜,形成于上述半导体基板的上述第2面与上述布线图形延伸存在的面之间,和上述接地线电连接。
摄像机模块具备:下述的半导体器件;透镜单元,配设于上述半导体器件的第1面侧;以及壳体,保持上述半导体器件和上述透镜单元;上述半导体器件具备:半导体基板,在第1面上具备半导体元件;布线图形,位于上述半导体基板的与上述第1面相反侧的第2面侧,至少在一部分中包含接地线;贯通电极,从上述第1面到上述第2面贯通上述半导体基板,电连接上述半导体元件和上述布线图形;以及金属膜,位于上述半导体基板的上述第2面与上述布线图形延伸存在的面之间,与上述接地线电连接。
半导体器件的制造方法包含下述步骤:形成接触孔,该接触孔将在第1面上具备半导体元件的半导体基板从上述第1面贯通到与该第1面相反侧的第2面;在上述半导体基板的上述第2面侧形成和该半导体基板电连接的金属膜;形成使上述金属膜的一部分露出并且覆盖该金属膜的绝缘膜;在上述绝缘膜上形成布线图形,并且在上述接触孔内形成贯通上述半导体基板的贯通电极,该布线图形至少包含通过上述露出部分与上述金属膜电连接的接地线。
根据本发明的实施方式,能够实现避免重影及布线图形等的映入并且可高速工作的半导体器件及摄像机模块,以及可高速工作的半导体器件的制造方法。
附图说明
图1是表示根据本发明实施方式1的摄像机模块的概略结构的示意剖面图。
图2是表示根据本发明实施方式1的半导体器件的概略结构的示意剖面图。
图3是表示根据本发明实施方式1的半导体器件的概略结构的俯视图。
图4A是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其1)。
图4B是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其2)。
图4C是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其3)。
图4D是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其4)。
图4E是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其5)。
图4F是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其6)。
图4G是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其7)。
图4H是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其8)。
图4I是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其9)。
图4J是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其10)。
图4K是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其11)。
图4L是表示根据本发明实施方式1的摄像机模块的制造方法的工序图(其12)。
图5是表示根据本发明实施方式1的变形例1-1的半导体器件的概略结构的俯视图。
图6是表示根据本发明实施方式1的变形例1-2的半导体器件的概略结构的剖面图。
图7A是表示根据本发明实施方式1的变形例1-3的摄像机模块的制造方法的工序图(其1)。
图7B是表示根据本发明实施方式1的变形例1-3的摄像机模块的制造方法的工序图(其2)。
图7C是表示根据本发明实施方式1的变形例1-3的摄像机模块的制造方法的工序图(其3)。
图7D是表示根据本发明实施方式1的变形例1-3的摄像机模块的制造方法的工序图(其4)。
图8是表示根据本发明实施方式2的半导体器件的概略结构的俯视图。
图9是表示图8所示的半导体器件的概略结构的B-B剖面图。
图10是表示根据本发明实施方式3的半导体器件的概略结构的俯视图。
图11是表示图10所示的半导体器件的概略结构的C-C剖面图。
具体实施方式
下面,参照附图,详细说明根据本发明实施方式的半导体器件、摄像机模块及半导体器件的制造方法。还有,并不是由下面的实施方式来限定本发明。另外,在下面的实施方式中使用的半导体器件及摄像机模块的剖面图是示意图,层的厚度和宽度之间的关系以及各层的厚度比率等和实际的器件不同。再者,实施方式中所示的层厚度是一例,并不限定于此。
根据下面实施方式的半导体器件具备:半导体基板,在第1面上具备半导体元件;布线图形,位于上述半导体基板的与上述第1面相反侧的第2面侧,至少在一部分中包含接地线;贯通电极,从上述第1面到上述第2面贯通上述半导体基板,电连接上述半导体元件和上述布线图形;以及金属膜,位于上述半导体基板的上述第2面与上述布线图形延伸存在的面之间,与上述接地线电连接。
另外,根据下面实施方式的摄像机模块具备:下述的半导体器件;透镜单元,配设于上述半导体器件的第1面侧;以及壳体,保持上述半导体器件和上述透镜单元;上述半导体器件具备:半导体基板,在第1面上具备半导体元件;布线图形,位于上述半导体基板的与上述第1面相反侧的第2面侧,至少在一部分中包含接地线;贯通电极,从上述第1面到上述第2面贯通上述半导体基板,电连接上述半导体元件和上述布线图形;以及金属膜,位于上述半导体基板的上述第2面与上述布线图形延伸存在的面之间,与上述接地线电连接。
另外,根据下面实施方式的半导体器件的制造方法包含下述步骤:形成接触孔,该接触孔将在第1面上具备半导体元件的半导体基板从上述第1面一直贯通到和该第1面相反侧的第2面;在上述半导体基板的上述第2面侧形成和该半导体基板电连接的金属膜;形成使上述金属膜一部分露出并且覆盖该金属膜的绝缘膜;在上述绝缘膜上形成布线图形,并且在上述接触孔内形成贯通上述半导体基板的贯通电极,该布线图形至少包括通过上述露出部分与上述金属膜电连接的接地线。
实施方式1
下面,使用附图来详细说明本发明实施方式1所涉及的半导体器件、摄像机模块及半导体器件的制造方法。图1是表示根据本实施方式1的摄像机模块1的概略结构的示意剖面图。还有,在图1中表示,在半导体器件11的半导体基板的与形成固体摄像元件11A的面垂直的面上剖开摄像机模块1时的剖面图。
如图1所示,摄像机模块1具备:半导体器件11,包含固体摄像元件11A;玻璃罩12,配设于半导体器件11中固体摄像元件11A的受光面(下面将其称为第1面)侧;接合层13,将玻璃罩12固定至半导体器件11;透镜单元14,隔着玻璃罩12配设于半导体器件11中固体摄像元件11A的第1面侧;摄像机壳体15,收纳固定玻璃罩12的半导体器件11和透镜单元14。在半导体器件11中和形成固体摄像元件11A后的面相反(下面将其称为第2面)侧,安装有焊料球16作为外部连接端子。
在上面,固体摄像元件11A例如是由CMOS(互补金属氧化物半导体:Complementary Metal Oxide Semiconductor)传感器或CCD(电荷耦合器件:Charge Coupled Device)传感器等构成的半导体元件。另外,透镜单元14包含:1个以上的透镜141,使从摄像机壳体15的光学窗口15A所入射的光在固体摄像元件11A的受光面上成像;以及透镜保持架142,保持透镜141。
下面,使用图2及图3来详细说明根据本实施方式1的半导体器件11。图2是表示根据本实施方式1的半导体器件11的概略结构的示意剖面图。另外,图3是表示半导体器件11概略结构的俯视图。但是,为了说明的方便,在图3中选取半导体器件11的一部分的层进行表示。另外,图2是图3中的A-A剖面图。
如图2所示,半导体器件11具备:半导体基板111,在第1面侧形成固体摄像元件11A;过滤层112,形成于半导体基板111的第1面上;聚光用的微透镜阵列113,隔着过滤层112,形成于半导体基板111的第1面侧的与固体摄像元件11A对应的位置上;电极焊盘114,形成于半导体基板111的第1面侧,和固体摄像元件11A电连接;贯通电极116a,从第1面向第2面贯通半导体基板111,把和电极焊盘114之间的电连接引出到半导体基板111的第2面侧;布线图形116,形成于半导体基板111的第2面侧;绝缘膜115,防止半导体基板111与布线图形116及贯通电极116a直接接触;GND平面117,形成于半导体基板111的第2面与布线图形116所延伸存在的面(或者层)之间;GND触点116b,贯通绝缘膜115,电连接布线图形116和GND平面117;绝缘树脂制的阻焊件118,保护半导体基板111形成了布线图形116的第2面侧;以及作为外部连接端子的焊料球16,通过阻焊件118,与布线图形116进行电接触。另外,在半导体器件11上,还具备:玻璃罩12,配设于半导体基板111的第1面侧;以及接合层13,将玻璃罩12固定至半导体基板111。
作为半导体基板111,可以使用例如厚度薄到100μm以下的硅(111)基板。另外,固体摄像元件11A例如在设为CMOS传感器时,具备1个像素由1个以上的半导体元件构成,并且该像素按2维阵列状在半导体基板111的第1面上排列多个的结构。再者,至少在半导体基板111的第1面的形成了固体摄像元件11A的区域,形成包含与RGB的像素相应的滤色器及钝化层的过滤层112。还有,过滤层112还可以包含遮光膜,该遮光膜覆盖半导体基板111的第1面的未形成固体摄像元件11A的区域。
在过滤层112的与半导体基板111相反侧的面上,利用接合层13来固定玻璃罩12。接合层13形成在与未形成固体摄像元件11A的区域对应的区域。
在半导体基板111的第1面侧,形成了与固体摄像元件11A电连接的电极焊盘114。作为电极焊盘114,例如可以使用铜(Cu)膜。但是,不限定于此,还能够使用钛(Ti)膜及其他的金属膜或合金膜或者它们的层叠膜等各种导电体膜。
该电极焊盘114通过贯通半导体基板111的贯通电极116a,与半导体基板111的第2面侧所形成的布线图形116电连接。也就是说,半导体基板111的第1面上所形成的固体摄像元件11A通过第1面侧所形成的未图示的布线及电极焊盘114以及贯通电极116a,被引出到半导体基板111的第2面侧。还有,布线图形116包括:信号线,与作为信号输入输出端子的焊料球16电连接;以及接地线,与作为接地端子(GND)的焊料球16电连接。
贯通电极116a形成于贯通半导体基板111的第1通孔(也称为接触孔)V1内及过滤层112上所形成的第2通孔V2内,和通过第2通孔V2露出的电极焊盘114电连接。在第1通孔V1内的表面上,形成绝缘膜115,以此来防止贯通电极116a和半导体基板111之间的直接接触。另外,绝缘膜115还延伸到半导体基板111的第2面上,以此来防止第2面侧的布线图形116和半导体基板111之间的直接接触。
贯通电极116a和布线图形116例如作为同一导电层形成。作为该导电层,例如可以使用将Ti和Cu的层叠膜作为基底层的Cu膜。另外,其膜厚例如可以设为5μm左右。
在形成了布线图形116的半导体基板111的第2面侧,形成绝缘性的阻焊件118,用来在装配焊料球16时使液状的焊料自调整于指定的位置,并且保护半导体基板111不受热。该阻焊件118例如可以使用具备感光性的环氧类绝缘树脂来形成。另外,在阻焊件118上,形成着有选择地装配焊料球16的第4通孔V4。
在半导体基板111的第2面上,也就是在半导体基板111和绝缘膜115之间,形成例如由膜厚为100nm左右的Ti膜构成的GND平面117。但是,不限定于此,而可以使用其他的金属膜或合金膜或者它们的层叠膜等各种导电体膜。该GND平面117如图3所示,至少形成在与形成了包含固体摄像元件11A的半导体元件的第1面中的区域(元件区域)对应的第2面中的区域AR上。因此,在本实施方式1中,例如跨半导体基板111的第2面整体来形成。但是,在本实施方式1中,至少不形成在半导体基板111上所形成的第1通孔V1内部及周围。换言之,GND平面117从第2面侧观察,在第1通孔V1开口。
另外,GND平面117通过GND触点116b,电连接于第2面侧所形成的布线图形116之中的接地线上。这里,GND触点116b例如可以作为布线图形116之中形成于绝缘膜115内的部分。所谓布线图形116之中形成于绝缘膜115内的部分指的是,以使GND平面117露出的方式形成在绝缘膜115上的第3通孔V3内的部分。但是,不限定于此,例如也可以另行设置贯通绝缘膜115的电极。还有,在图3中,用实线只表示出形成于第2面侧的布线图形116之中的接地线,对于与接地端子(GND)之外的端子连接的信号线等布线则用虚线进行了表示。
这样,通过跨半导体基板111的形成了布线图形116的一侧的面(第2面)整面来形成接地的导电层,即便基板本身是高电阻,也能够将半导体基板111可靠地保持为接地电位,并且可以防止在半导体基板111和布线图形116之间产生寄生电容或寄生电阻。其结果为,因为可以防止在布线图形116上传播的高频信号的波形变钝,所以能够实现可高速工作的半导体器件11。另外,由于通过在布线图形116和半导体基板111之间配置保持为接地电位的导电层,就可以在导电层上遮断来自半导体元件等的电噪声输入到布线图形116上,因而能够实现高性能的半导体器件11及摄像机模块1。
再者,作为GND平面117,例如使用至少可遮挡可见光的膜。通过对GND平面117使用遮光性的膜,就可以防止来自半导体基板111背面(第2面)的光经过半导体基板111入射至其上面(第1面)所形成的固体摄像元件11A。因此,能够避免在摄像图像上产生重影或者基板背面的布线图形被映入等问题的发生。另外,虽然在对于薄型化的含有硅的半导体基板111例如由焊料球16施加了外部的应力时,在硬且脆的硅上易于产生裂纹,但是根据本实施方式1,因为成为由作为GND平面117的金属进行了内衬的复合体基板,所以还可以获得机械强度增大并且可靠性较高的半导体器件11。
下面,和附图一起详细说明根据本实施方式1的摄像机模块1的制造方法。图4A~图4L是表示根据本实施方式1的摄像机模块1的制造方法的工序图。还有,在根据本实施方式1的半导体器件11的制造方法中,虽然使用对1个晶片制入多个半导体器件的所谓W-CSP(晶片水平芯片尺寸封装:Wafer Level Chip Size Package)技术,但是在下面为了说明的简单,将着眼于1个芯片(半导体器件11)。
在本制造方法中,首先在硅晶片等半导体基板111A的第1面侧形成固体摄像元件11A之后,通过在第1面上依次形成布线及过滤层112、微透镜阵列113,获得图4A所示的那种剖面结构。还有,在图4A中,选取形成于半导体基板111第1面上的布线之中的电极焊盘114来进行表示。
接着,通过在过滤层112及形成了微透镜阵列113的过滤层112上涂敷感光性的接合剂,对其进行构图,来形成接合层13。还有,该接合层13除了对半导体基板111A(111)固定玻璃罩12的作为接合部的功能之外,还作为在玻璃罩12和微透镜阵列113之间确保空隙所用的隔层来发挥作用。通过在玻璃罩12和微透镜阵列113之间确保空隙,就可以防止各微透镜的聚光效果受损。接下来,通过将半导体基板111A在翻转后的状态下与透明的玻璃罩12进行粘合,获得图4B所示的那种剖面结构。
接着,如图4C所示,将半导体基板111A从第2面侧进行薄形化。在该薄形化中,例如可以通过将磨削、CMP(化学机械抛光:ChemicalMechanical Polishing)和湿法蚀刻根据需要加以组合来实施。另外,优选的是,薄形化后半导体基板111的膜厚大致为50~100μnm以下。因此,能够维持半导体器件11的刚性,同时实现进一步的小型化及薄形化,并且可以通过下述的GND平面117有效释放半导体基板111中蓄积的电荷,结果,能够提高半导体器件11的特性。
接着,在薄形化的半导体基板111的第2面上采用光刻法来形成抗蚀剂R1。该抗蚀剂R1具备在和电极焊盘114对应的位置,也就是形成第1通孔V1的区域上形成开口A1的图形。接下来,通过利用抗蚀剂R1来作为掩模的RIE(反应离子蚀刻:Reactive Ion Etching)将半导体基板111从第2面侧进行蚀刻,如图4D所示,形成将半导体基板111从第1面一直贯通到第2面的第1通孔V1。
接着,在剥离抗蚀剂R1之后,通过在形成了第1通孔V1的半导体基板111的第2面上,例如使用溅射法来堆积Ti,如图4E所示,形成覆盖半导体基板111的第2面的金属膜117A。此时,金属膜117A的膜厚例如可以设为100nm左右。还有,作为堆积的金属,除Ti之外,还可以使用钽(Ta)、Cu、镍(Ni)或铁(Fe)等。但是,若考虑到金属给半导体基板111带来的影响,则优选的是,使用Ti或Ta等给半导体基板111带来的影响小的金属。另外,在作为堆积的金属使用了可硅化的金属时,因为通过在半导体基板111和金属膜117A之间的界面上使之进行硅化反应,它们之间的电连接变得良好,所以能够进一步有效实施来自半导体基板111的电荷经过GND平面117的释放。
接着,在用金属膜117A所覆盖的半导体基板111的第2面侧,采用光刻法来形成抗蚀剂R2。该抗蚀剂R2具备在第1通孔V1及其周围形成开口A2的图形。另外,作为抗蚀剂R2形成时对位用的标记,例如可以使用第1通孔V1内所形成的金属膜117A的凹形。接下来,通过利用抗蚀剂R2来作为掩模的湿法蚀刻或RIE将金属膜117A从第2面侧进行蚀刻,如图4F所示,去除第1通孔V1内及第1通孔V1周边的金属膜117A。
还有,第1通孔V1周边的去除部分只要是至少可吸收形成抗蚀剂R2时的曝光极限(margin)的程度的范围的金属膜117A即可。另外,在相对于曝光极限具有足够的余量来去除第1通孔V1周边的金属膜117A时,也可以在形成第1通孔V1之前形成GND平面117。也就是说,也可以更换图4D所示的第1通孔形成工序和图4E~图4F所示的GND平面形成工序的顺序。这种情况下,虽然因为半导体基板111的第2面较为平坦,所以有时对金属膜构图用的抗蚀剂进行开口时的位置偏差变大,但是因为如上所述具有足够的余量来去除第1通孔V1周边的金属膜117A,所以可以防止在第1通孔V1内部(特别是形成第2通孔V2的部分)残留GND平面117用的金属膜117A,结果为,可以避免固体摄像元件11A经由电极焊盘114不必要地接地。还有,在形成GND平面117之后的工序中,能够将第1通孔V1周围的GND平面117的开口利用在对位中。
如上所述,若在半导体基板111的第2面上形成了GND平面117,则接着在剥离抗蚀剂R2之后,如图4G所示,在形成了GND平面117的半导体基板111的第2面上使绝缘膜115A成膜。绝缘膜115A既可以是硅氧化膜(SiO2)或硅氮化膜(SiN)等无机绝缘膜,也可以是绝缘树脂等有机绝缘膜。例如在无机绝缘膜的场合,可以使用CVD(化学气相沉积:ChemicalVapor Deposition)等来形成绝缘膜115A。另外,在有机绝缘膜的场合,可以使用喷墨印刷技术等来形成绝缘膜115A。
接着,在形成了绝缘膜115A的半导体基板111的第2面侧,采用光刻法来形成抗蚀剂R3。该抗蚀剂R3具备在第1通孔V1底部形成开口A3的图形。另外,该图形包括后面形成的布线图形116的与接地线对应的位置上所形成的开口A4。接下来,通过利用抗蚀剂R3来作为掩模的RIE对绝缘膜115A(也可以根据需要包括过滤层12在内)进行蚀刻,以此如图4H所示,将使半导体基板111的第1面侧所形成的电极焊盘114露出的第2通孔V2形成于第1通孔V1底部,并且在布线图形116的与接地线对应的位置上形成使GND平面117露出的第3通孔V3。这样,因为通过由同一工序形成用于取得与电极焊盘114之间的电连接的第2通孔V2以及用于取得与GND平面117之间的电连接的第3通孔V3,所以能够实现工序的简单化。
接着,在剥离抗蚀剂R3之后,如图4I所示,在形成了第2通孔V2及第3通孔V3的半导体基板111的第2面上形成布线图形116。还有,在该布线图形116中,还包含形成于第1通孔V1内及第2通孔V2内的贯通电极116a以及形成于第3通孔V3内的GND触点116b。包括贯通电极116a及GND触点116b在内的布线图形116的形成例如可以使用电解镀法。作为具体的例子,首先将作为势垒金属发挥作用的Ti膜和电镀时作为籽晶层发挥作用的Cu膜,例如采用溅射法形成于半导体基板111的第2面侧整体上,接下来,例如通过实施光刻工序,在Cu膜上,形成以布线图形116的图形形状开口的抗蚀剂。接下来,通过利用该抗蚀剂来作为掩模并且利用Cu膜作为籽晶层的电解镀法,使Cu膜生长。随后,在将作为掩模利用的抗蚀剂剥离之后,利用以电解镀法生长的Cu膜来作为掩模,并且通过蚀刻对作为籽晶层的Cu膜及作为势垒金属的Ti膜进行构图。借此,形成由Cu构成的布线图形116。接着,在形成了布线图形116的半导体基板111的第2面侧涂敷阻焊件的溶液,使其干燥后通过光刻工序及蚀刻工序进行构图,以此如图4J所示,形成在装配焊料球16的位置上形成了第2通孔V4的阻焊件118。
接着,通过使用现有的焊料球装配装置,如图4K所示,在形成了阻焊件118的半导体基板111的第2面侧的指定位置的第4通孔V4内装载焊料球16。接着,通过例如使用金刚石切割器或激光将半导体基板111沿着划线区域SR(参见图3)进行切割,如图4L所示,将在半导体晶片上形成为2维阵列状的半导体器件11单片化。随后,通过将单片化的半导体器件11和透镜单元14一起,嵌入摄像机壳体15中,来制造具备图1所示那种剖面结构的摄像机模块1。
如上,根据本实施方式1的半导体器件11具备:半导体基板111,在第1面上形成作为半导体元件的固体摄像元件11A;布线图形116,形成于半导体基板111的与第1面相反侧的第2面侧,至少在一部分包含接地线;贯通电极116a,将半导体基板111从第1面一直贯通到第2面,电连接固体摄像元件11A和布线图形116;GND平面117,形成于半导体基板111的第2面与布线图形116所延伸存在的面(或者层)之间,与半导体基板111及布线图形116的接地线电连接。也就是说,在本实施方式1中,使半导体基板111和布线图形116之间介入了作为遮光膜发挥作用的接地电位的GND平面117。因此,可以抑制半导体基板111和布线图形116之间的电容耦合,并且防止来自半导体基板111背面(第2面)的光经过半导体基板111入射至其上面(第1面)所形成的固体摄像元件11A。其结果为,能够避免重影及布线图形等的映入,并且实现可高速工作的半导体器件11及摄像机模块1。
变形例1-1
另外,在上述实施方式1中,作为采用光刻法对GND平面117进行构图时的曝光所使用的对位用标记,利用了第1通孔V1部分的形状。但是,例如图5所示,也可以在GND平面117(金属膜117A)上设置对位用的开口117a。下面,将该情形作为本实施方式1的变形例1-1,使用附图进行详细说明。
图5是表示根据本变形例1-1的半导体器件11-1的概略结构的俯视图。但是,为了说明的方便,在图5中选取半导体器件11-1的一部分的层来进行表示。如图5所示,根据本变形例1-1的半导体器件11-1在半导体基板111上与设置未图示的对位用标记的位置对应的GND平面117的指定区域,形成有使下层的绝缘膜115露出的开口117a。
如上所述,作为半导体元件的固体摄像元件11A从单片化后半导体基板111的第1面的外缘开始,形成于指定距离内侧的元件区域。在本变形例1-1中,在GND平面117的从半导体基板111的第2面侧观察与元件区域对应的区域AR的指定区域上形成开口117a。例如,将开口117a形成于把半导体器件11-1单片化时作为切割部分的切割线上。借此,可以避免布线图形116和半导体基板111之间的电容耦合增加,并且在曝光时利用半导体基板111上所设置的对位用标记。
该开口117a例如在形成金属膜117A时通过使用剥离(lift-off)法来形成。也就是说,在本变形例1-1中,在半导体基板111的第2面上使金属膜117A成膜之前,事先在单片化时切割的划线区域SR上使用光刻法来形成抗蚀剂。随后,通过在形成了抗蚀剂的半导体基板111的第2面上例如使用溅射法堆积Ti等金属,来形成金属膜117A,接下来通过使用丙酮等的剥离液将抗蚀剂去除,把抗蚀剂上的金属膜117A的一部分一起去除(剥离)。借此,在划线区域SR上形成开口117a。
另外,如同本变形例1-1那样,事先在对GND平面117进行构图之前的金属膜117A上形成开口117a,由此能够根据该开口117a正确实施曝光时的对位,所以能够减小将金属膜117A对GND平面117进行构图时第1通孔V1周围的曝光极限。还有,其他的结构、制造方法及效果因为和上述实施方式相同,所以这里省略详细的说明。
变形例1-2
另外,在上述实施方式1中,去除了第1通孔V1内的金属膜117A。也就是说,在第1通孔V1内,成为GND平面117不延伸存在的结构。但是,例如图6所示,GND平面117也可以延伸到第1通孔V1内的侧面。换言之,GND平面117也可以包含第1通孔V1内的侧面上所形成的通孔内GND平面117b。下面,将该情形作为本实施方式1的变形例1-2,使用附图进行详细说明。
图6是表示根据本变形例1-2的半导体器件11-2概略结构的剖面图。还有,为了说明的方便,在图6中表示与图3中的线A-A对应的部分(线B-B)的半导体器件11-2的剖面。如图6所示,根据本变形例1-2的半导体器件11-2具备从半导体基板111的第2面延伸到第1通孔V1的侧面上的GND平面117及通孔内GND平面117b。借此,可以防止第1通孔V1内的贯通电极116a和半导体基板111产生电容耦合,结果为,能够进一步提高半导体器件11-2的特性。
还有,在本变形例1-2中,也和上述变形例1-1相同,可以在划线区域SR的GND平面117上形成开口117a。另外,其他的结构、制造方法及效果因为和上述实施方式或其变形例相同,所以这里省略详细的说明。
变形例1-3
另外,在上述实施方式及其变形例中,在从金属膜117A对GND平面117的构图中使用了光刻工序及蚀刻工序。但是,不限定于此,例如也可以使用剥离法来形成GND平面117。下面,将该情形作为本实施方式1的变形例1-3,使用附图进行详细说明。其中,有关和上述实施方式1相同的工序,则通过引用其说明,来省略其详细的说明。
图7A~图7D是表示根据本变形例1-3的摄像机模块1的制造方法的工序图。在本制造方法中,首先经过和在上面使用图4A~图4C所说明的工序相同的工序,以此将形成了固体摄像元件11A、过滤层112、微透镜阵列113及电极焊盘114的半导体基板111A从第2面侧进行薄形化。还有,在半导体基板111上,已经利用接合层13粘合了玻璃罩12。
接着,如图7A所示,在薄形化的半导体基板111的第2面上采用光刻法来形成抗蚀剂R21。该抗蚀剂R21具有以GND平面117的图形形状为正的反图形形状。也就是说,抗蚀剂R21至少形成于形成第1通孔V1的区域上。其中,在本变形例1-3中,优选的是,抗蚀剂R21以半导体基板111的第2面为基准,具备所谓倒锥形状的剖面。该倒锥形状例如通过调整曝光时的焦点深度及曝光光量就能够实现。
接着,通过在形成了抗蚀剂R21的半导体基板111的第2面上例如采用溅射法来堆积Ti,如图7B所示,在半导体基板111的第2面上和抗蚀剂R21的上表面上形成金属膜117B。接下来,例如使用丙酮等的剥离液去除抗蚀剂R21。由此,将抗蚀剂R21上的金属膜117B与抗蚀剂R21一起去除(剥离),其结果为,如图7C所示,在半导体基板111的第2面上残留被构图的GND平面117。此时,因为事先使抗蚀剂R21的剖面形状成为倒锥形状,所以可以使GND平面117的端部成为锥形状。借此,可以防止在半导体器件11的工作时在GND平面117的端部集中电场,结果为,能够提高半导体器件11的包括耐压特性在内的电特性。
接着,在形成了GND平面117的半导体基板111的第2面上采用光刻法来形成抗蚀剂R22。该抗蚀剂R22和在上述实施方式1中使用图4所说明的抗蚀剂R1相同,具备在和电极焊盘114对应的位置,也就是形成第1通孔V1的区域上形成了开口A22的图形。接下来,通过利用抗蚀剂R22来作为掩模的RIE将半导体基板111从第2面侧进行蚀刻,以此如图7D所示,形成将半导体基板111从第1面一直贯通到第2面的第1通孔V1。
接下来,经过和在上面使用图4E~图4H所说明的工序相同的工序,以此将半导体基板111单片化,该半导体基板111在过滤层112上形成第2通孔V2,并且形成了绝缘膜115、布线图形116、阻焊件118及焊料球16,该绝缘膜115形成了第3通孔V3,该布线图形116包含贯通电极116a及GND触点116b。随后,和上述实施方式1相同,通过将单片化的半导体器件11和透镜单元14一起嵌入摄像机壳体15中,来制造具备图1所示的那种剖面结构的摄像机模块1。
如上,在本变形例1-3中,因为在将半导体基板111的第2面用金属膜117B覆盖之前,形成用来对GND平面117进行构图的抗蚀剂R21,所以能够容易且正确地实施曝光时的对位。其结果为,因为能够形成GND平面117使之进一步覆盖半导体基板111的第2面的更宽大的范围,所以能够使半导体器件11的特性得到进一步提高。
还有,其他的结构、制造方法及效果因为和上述实施方式或其变形例相同,所以这里省略详细的说明。
实施方式2
下面,使用附图来详细说明本实施方式2所涉及的半导体器件、摄像机模块及半导体器件的制造方法。在下面的说明中,对于和上述实施方式或其变形例相同的结构,附上相同的符号,省略其重复的说明。
图8是表示根据本实施方式2的半导体器件21的概略结构的俯视图。图9是表示图8所示的半导体器件21的概略结构的B-B剖面图。其中,为了说明的方便,在图9中选取半导体器件21的一部分的层来进行表示。
如图8及图9所示,半导体器件21中的GND平面217不形成在从单片化时切割的面与第2面所形成的边开始具备指定距离的宽度的划线区域SR上。换言之,GND平面217形成为,覆盖从单片化后半导体基板111的第2面周围的边隔开指定距离的区域AR内。
因为作为这种结构,所以采用本实施方式2,可以避免切割时GND平面217被剥除。其结果为,能够防止因GND平面的剥除导致的漏电流发生及装置特性变坏。还有,其他的结构、制造方法及效果因为和上述实施方式或其变形例相同,所以这里省略详细的说明。
实施方式3
下面,使用附图来详细说明本实施方式3所涉及的半导体器件、摄像机模块及半导体器件的制造方法。在下面的说明中,对于和上述实施方式或其变形例相同的结构,附上相同的符号,省略其重复的说明。
图10是表示根据本实施方式3的半导体器件31的概略结构的俯视图。图11是表示图10所示的半导体器件31的概略结构的C-C剖面图。其中,为了说明的方便,在图11中选取半导体器件31一部分的层来进行表示。
如图10及11所示,半导体器件31中的GND平面317形成为覆盖下述区域,该区域在从半导体基板111的第2面与单片化时切割的面所形成的边隔开指定距离的区域AR内,并且比将在区域AR的端部排列成行状的第1通孔V1的靠第2面中心的端连结的线更靠内侧。或者说,GND平面317不形成在单片化时切割的划线区域SR及将排列了多个的第1通孔V1围住的带状通孔排列区域VR上。
这样,在本实施方式3中,贯通电极116a与半导体基板111的第2面周围的边之中任一条以上的边接近排列,GND平面317形成在从半导体基板111的第2面侧观察比将排列的贯通电极116a的第2面中心侧的端连结起来的线更靠内侧的区域上。因此,根据本实施方式3,因为可以避免在切割时GND平面317被剥除,并且能够使GND平面317的构图形状简单化,所以能够实现半导体器件31的设计容易化及制造的简单化。还有,其他的结构、制造方法及效果因为和上述实施方式或其变形例相同,所以这里省略详细的说明。
如同上面所说明的那样,根据本发明的实施方式,能够实现避免重影及布线图形等的映入并且可高速工作的半导体器件及摄像机模块、以及可高速工作的半导体器件的制造方法。
进一步的效果及变形例可以由从业人员轻易导出。因而,本发明更为广泛的方式并不限定为如上所示及所述的特定详细及代表性的实施方式。从而,能够在不脱离由附加的权利要求及其等同物所定义的总体发明概念精神或者范围的状况下,进行各种各样的变更。

Claims (15)

1.一种半导体器件,具备:
半导体基板,在第1面上具备半导体元件;
布线图形,位于上述半导体基板的与上述第1面相反侧的第2面侧,至少一部分包括接地线;
贯通电极,从上述第1面到上述第2面贯通上述半导体基板,将上述半导体元件和上述布线图形电连接;
绝缘膜,防止半导体基板与布线图形及贯通电极直接接触;以及
金属膜,位于上述半导体基板的上述第2面与上述绝缘膜之间,与上述接地线电连接。
2.如权利要求1所述的半导体器件,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述金属膜在上述接触孔开口。
3.如权利要求2所述的半导体器件,其中,
上述开口与上述金属膜的边缘连续。
4.如权利要求1所述的半导体器件,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述金属膜覆盖该第2面及上述接触孔的内侧面。
5.如权利要求1所述的半导体器件,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述接触孔排列在该第2面的外缘附近,
从上述第2面侧观察,上述金属膜的端部比上述接触孔的排列更靠内侧。
6.一种摄像机模块,具备:
半导体器件,该半导体器件具备半导体基板、布线图形、贯通电极、绝缘膜和金属膜,该半导体基板在第1面上具备半导体元件,该布线图形位于上述半导体基板的与上述第1面相反侧的第2面侧,至少一部分包括接地线,该贯通电极从上述第1面到上述第2面贯通上述半导体基板,将上述半导体元件和上述布线图形电连接,该绝缘膜防止半导体基板与布线图形及贯通电极直接接触,该金属膜位于上述半导体基板的上述第2面与上述绝缘膜之间,与上述接地线电连接;
透镜单元,配置在上述半导体器件的上述第1面侧;以及
壳体,保持上述半导体器件和上述透镜单元。
7.如权利要求6所述的摄像机模块,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述金属膜在上述接触孔开口。
8.如权利要求7所述的摄像机模块,其中,
上述开口与上述金属膜的边缘连续。
9.如权利要求6所述的摄像机模块,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述金属膜覆盖该第2面及上述接触孔的内侧面。
10.如权利要求6所述的摄像机模块,其中,
上述贯通电极位于贯通上述半导体基板的接触孔内,
从上述第2面侧观察,上述接触孔排列在该第2面的外缘附近,
从上述第2面侧观察,上述金属膜的端部比上述接触孔的排列更靠内侧。
11.一种半导体器件的制造方法,包括以下步骤:
形成接触孔,该接触孔从半导体基板的第1面到与该第1面相反侧的第2面贯通上述半导体基板,该半导体基板在上述第1面上具备半导体元件;
在上述半导体基板的上述第2面侧形成与该半导体基板电连接的金属膜;
形成使上述金属膜的一部分露出并且覆盖该金属膜的绝缘膜;
在上述绝缘膜上形成至少包括经由上述露出部分与上述金属膜电连接的接地线的布线图形,并且在上述接触孔内形成贯通上述半导体基板的贯通电极。
12.如权利要求11所述的半导体器件的制造方法,其中,
上述金属膜形成为从上述第2面侧观察在上述接触孔开口。
13.如权利要求12所述的半导体器件的制造方法,其中,
上述开口与上述金属膜的边缘连续。
14.如权利要求11所述的半导体器件的制造方法,其中,
上述金属膜形成为从上述第2面侧观察覆盖该第2面及上述接触孔的内侧面。
15.如权利要求11所述的半导体器件的制造方法,其中,
从上述第2面侧观察,上述接触孔排列在该第2面的外缘附近,
从上述第2面侧观察,上述金属膜的端部形成为比上述接触孔的排列更靠内侧。
CN2010102132755A 2009-06-22 2010-06-22 半导体器件、摄像机模块及半导体器件的制造方法 Expired - Fee Related CN101930986B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP148098/2009 2009-06-22
JP2009148098A JP5150566B2 (ja) 2009-06-22 2009-06-22 半導体装置およびカメラモジュール

Publications (2)

Publication Number Publication Date
CN101930986A CN101930986A (zh) 2010-12-29
CN101930986B true CN101930986B (zh) 2013-03-13

Family

ID=43354008

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102132755A Expired - Fee Related CN101930986B (zh) 2009-06-22 2010-06-22 半导体器件、摄像机模块及半导体器件的制造方法

Country Status (4)

Country Link
US (1) US20100321544A1 (zh)
JP (1) JP5150566B2 (zh)
CN (1) CN101930986B (zh)
TW (1) TWI430423B (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5498684B2 (ja) * 2008-11-07 2014-05-21 ラピスセミコンダクタ株式会社 半導体モジュール及びその製造方法
US8314498B2 (en) * 2010-09-10 2012-11-20 Aptina Imaging Corporation Isolated bond pad with conductive via interconnect
JP5958732B2 (ja) 2011-03-11 2016-08-02 ソニー株式会社 半導体装置、製造方法、および電子機器
US8890191B2 (en) 2011-06-30 2014-11-18 Chuan-Jin Shiu Chip package and method for forming the same
JP2013041878A (ja) 2011-08-11 2013-02-28 Sony Corp 撮像装置およびカメラモジュール
FR2985088B1 (fr) * 2011-12-23 2015-04-17 Commissariat Energie Atomique Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication
CN107770462B (zh) * 2011-12-28 2020-09-22 株式会社尼康 拍摄元件和拍摄装置
JP5810921B2 (ja) * 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
JP2015103787A (ja) * 2013-11-28 2015-06-04 凸版印刷株式会社 固体撮像装置及びその製造方法
JP6299406B2 (ja) * 2013-12-19 2018-03-28 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
EP2889901B1 (en) 2013-12-27 2021-02-03 ams AG Semiconductor device with through-substrate via and corresponding method
KR102214512B1 (ko) * 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지
JP6191728B2 (ja) 2015-08-10 2017-09-06 大日本印刷株式会社 イメージセンサモジュール
JP2016001759A (ja) * 2015-09-16 2016-01-07 凸版印刷株式会社 半導体装置
US10541262B2 (en) 2015-10-28 2020-01-21 China Wafer Level Csp Co., Ltd. Image sensing chip packaging structure and packaging method
US20180301488A1 (en) * 2015-10-28 2018-10-18 China Wafer Level Csp Co., Ltd. Image sensing chip packaging structure and packaging method
US9778191B2 (en) * 2016-02-05 2017-10-03 Personal Genomics, Inc. Optical sensing module
US10475834B1 (en) * 2017-10-06 2019-11-12 Facebook Technologies, Llc Apparatuses, systems, and methods for disrupting light at a back-side of an image sensor array
JP2019160847A (ja) * 2018-03-07 2019-09-19 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置および固体撮像素子
US10880462B2 (en) * 2019-01-30 2020-12-29 Audio Technology Switzerland S.A. Miniature video recorder
CN111968955B (zh) * 2020-08-27 2021-10-12 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN116682837B (zh) * 2023-08-02 2023-10-24 武汉楚兴技术有限公司 一种半导体结构及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101038926A (zh) * 2005-12-15 2007-09-19 三洋电机株式会社 半导体装置
CN101268552A (zh) * 2005-08-03 2008-09-17 美光科技公司 减少来自红外辐射的图像伪影的背面硅晶片设计
CN101308860A (zh) * 2007-05-15 2008-11-19 索尼株式会社 固态摄像器件及其制造方法以及摄像设备

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249632A (ja) * 2002-02-22 2003-09-05 Sony Corp 固体撮像素子およびその製造方法
JP4223851B2 (ja) * 2003-03-31 2009-02-12 ミツミ電機株式会社 小型カメラモジュール
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4534634B2 (ja) * 2004-07-05 2010-09-01 ソニー株式会社 固体撮像装置
JP4483442B2 (ja) * 2004-07-13 2010-06-16 ソニー株式会社 固体撮像素子と固体撮像装置、固体撮像素子の製造方法
JP2006228837A (ja) * 2005-02-15 2006-08-31 Sharp Corp 半導体装置及びその製造方法
JP2007165696A (ja) * 2005-12-15 2007-06-28 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4302751B2 (ja) * 2007-03-29 2009-07-29 Okiセミコンダクタ株式会社 半導体光センサ
JP5301108B2 (ja) * 2007-04-20 2013-09-25 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2009010288A (ja) * 2007-06-29 2009-01-15 Sanyo Electric Co Ltd 半導体装置
JP2009099591A (ja) * 2007-10-12 2009-05-07 Toshiba Corp 固体撮像素子及びその製造方法
JP4799543B2 (ja) * 2007-12-27 2011-10-26 株式会社東芝 半導体パッケージ及びカメラモジュール
KR20090108233A (ko) * 2008-04-11 2009-10-15 삼성전자주식회사 카메라 모듈의 제조 방법, 이에 의해 제작된 카메라 모듈및 상기 카메라 모듈을 포함하는 전자 시스템
JP5198150B2 (ja) * 2008-05-29 2013-05-15 株式会社東芝 固体撮像装置
KR100982270B1 (ko) * 2008-08-08 2010-09-15 삼성전기주식회사 카메라 모듈 및 이의 제조 방법
JP2010267736A (ja) * 2009-05-13 2010-11-25 Panasonic Corp 固体撮像素子

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101268552A (zh) * 2005-08-03 2008-09-17 美光科技公司 减少来自红外辐射的图像伪影的背面硅晶片设计
CN101038926A (zh) * 2005-12-15 2007-09-19 三洋电机株式会社 半导体装置
CN101308860A (zh) * 2007-05-15 2008-11-19 索尼株式会社 固态摄像器件及其制造方法以及摄像设备

Also Published As

Publication number Publication date
TW201117345A (en) 2011-05-16
TWI430423B (zh) 2014-03-11
JP2011003863A (ja) 2011-01-06
JP5150566B2 (ja) 2013-02-20
CN101930986A (zh) 2010-12-29
US20100321544A1 (en) 2010-12-23

Similar Documents

Publication Publication Date Title
CN101930986B (zh) 半导体器件、摄像机模块及半导体器件的制造方法
CN101937894B (zh) 具有贯通电极的半导体器件及其制造方法
JP5754239B2 (ja) 半導体装置
KR101032182B1 (ko) 반도체 패키지 및 카메라 모듈
US7981727B2 (en) Electronic device wafer level scale packages and fabrication methods thereof
CN102856336B (zh) 晶片封装体及其形成方法
JP6019099B2 (ja) 半導体装置の製造方法
US10991667B2 (en) Isolation structure for bond pad structure
US8232202B2 (en) Image sensor package and fabrication method thereof
US20160056196A1 (en) Conduction layer for stacked cis charging prevention
EP2802005A1 (en) Semiconductor device and method for manufacturing same
JP2010199589A (ja) イメージセンサー装置および半導体イメージセンサー装置の製造方法
CN102386192B (zh) 制造光学传感器的方法、光学传感器和包括其的照相机
KR20060132490A (ko) 관통 전극을 갖는 반도체 장치 및 그 제조 방법
US20090050995A1 (en) Electronic device wafer level scale packges and fabrication methods thereof
JP2011071239A (ja) 半導体装置の製造方法
CN109564929A (zh) 固态成像器件、固态成像器件的制造方法以及电子设备
EP2636065B1 (en) Rear-face illuminated solid state image sensors
TW200926376A (en) Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same
JP2009283503A (ja) 半導体装置及びその製造方法
KR20060122767A (ko) 3차원 구조 이미지 센서 패키지 소자
JP2011014674A (ja) 固体撮像装置の製造方法
CN101355039A (zh) 图像感测元件封装体及其制作方法
CN107221516B (zh) 一种气密性影像芯片封装结构及其制作方法
CN104396016B (zh) 固体摄像装置的制造方法及固体摄像装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130313

Termination date: 20160622

CF01 Termination of patent right due to non-payment of annual fee