CN101877348B - 用于堆叠的管芯嵌入式芯片堆积的系统和方法 - Google Patents

用于堆叠的管芯嵌入式芯片堆积的系统和方法 Download PDF

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CN101877348B
CN101877348B CN2010101395448A CN201010139544A CN101877348B CN 101877348 B CN101877348 B CN 101877348B CN 2010101395448 A CN2010101395448 A CN 2010101395448A CN 201010139544 A CN201010139544 A CN 201010139544A CN 101877348 B CN101877348 B CN 101877348B
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chip
layer
polymer lamination
additional
distribution layer
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CN101877348A (zh
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P·A·麦康奈利
K·M·迪罗歇
D·P·坎宁安
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General Electric Co
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General Electric Co
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Abstract

本发明名称为“用于堆叠的管芯嵌入式芯片堆积的系统和方法”。一种嵌入式芯片封装(ECP)包括沿垂直方向结合在一起以形成层压堆叠的多个重分布层，每个重分布层具有其中形成的通路。嵌入式芯片封装还包括嵌入在层压堆叠中的第一芯片和附连到层压堆叠并相对于第一芯片沿垂直方向堆叠的第二芯片，每个芯片具有多个芯片焊盘。嵌入式芯片封装还包括：置于层压堆叠的最外面的重分布层上的输入/输出(I/O)系统(86)；以及电耦合到I/O系统以将第一芯片和第二芯片电连接到I/O系统的多个金属互连。所述多个金属互连的每个延伸穿过相应的通路以与相邻重分布层上的金属互连、或第一芯片或第二芯片上的芯片焊盘形成直接金属连接。

Description

用于堆叠的管芯嵌入式芯片堆积的系统和方法
技术领域
一般来说，本发明的实施例涉及集成电路封装，更具体来说，涉及嵌入式芯片堆积(embedded chip build-up)，其使用直接到芯片接合焊盘(pad)或电组件连接焊盘的低阻抗金属互连，从而允许更高的器件速度、更低的功耗和更小的尺寸。嵌入式芯片封装可制造成具有堆叠的3D布置中的多个芯片或电子组件。所述多个芯片或电子组件通过布线穿过多个层压重分布层的金属互连而电连接到输入/输出系统。 
背景技术
随着集成电路变得越来越小并产生更好的操作性能，用于集成电路(IC)封装的封装技术已对应地从引线式封装演进到基于层压的球栅阵列(BGA)封装、到芯片级封装(CSP)、再到倒装芯片(flipchip)封装，并且现在演进到嵌入式芯片堆积封装。IC芯片封装技术的进步由对于实现更好性能、更大程度微型化和更高可靠性的日益增长的需求来驱动。新的封装技术还必须为大规模制造的目的提供批量生产的可能性，从而允许实现规模经济。 
在芯片级封装合并多个堆叠的芯片的情况下，芯片通常被线接合到衬底，这导致高的电阻、电感和电容，从而造成降级的器件速度和更高的功耗。倒装芯片管芯无法容易地进行3D堆叠，并且大部分限于并排平面管芯布置，这些布置使用大封装面积或封装堆叠，从而造成高的3D结构。按顺序堆叠并线接合的芯片无法作为单独的封装芯片进行预先测试，由此造成复合器件最终测试损耗和组装成品率损耗，这增加了生产成本。 
IC芯片封装要求的进步还对现有嵌入式芯片堆积工艺提出挑战。即，在许多当前嵌入式芯片封装中期望具有增加数量的重分布层，其中八个或更多重分布层是公共的。在标准嵌入式芯片堆积工艺中，首先将一个或多个管芯置于IC衬底上，随后按逐层方式施加重分布层，这个工艺可导致再布线和互连系统中的翘曲，从而要求使用模制的环氧应力平衡层或金属加强件。 
因此，需要允许在改善电互连性能的情况下以堆叠的布置施加多个管芯的嵌入式芯片制作的方法。还需要提供更短的制造周期时间并允许施加多个重分布层、同时能将封装的翘曲最小化而不使用加强件的嵌入式芯片制作。 
发明内容
本发明的实施例通过提供一种芯片制作的方法来克服上述缺点，在该方法中，嵌入式芯片封装中的芯片或电组件以堆叠的布置来提供，并通过直接金属连接而连接到输入/输出(I/O)系统。其中具有金属互连的多个图案化的层压层将每个芯片或电子组件直接连接到I/O系统。 
根据本发明的一个方面，一种嵌入式芯片封装包括沿垂直方向结合在一起以形成层压堆叠的多个重分布层，其中每个重分布层包括在其中形成的多个通路(via)。该嵌入式芯片封装还包括：嵌入在层压堆叠中并包括多个芯片焊盘的第一芯片；包括多个芯片焊盘的第二芯片，它附连到层压堆叠并相对于第一芯片沿垂直方向堆叠；以及置于层压堆叠的最外面的重分布层上的输入/输出(I/O)系统。嵌入式芯片封装还包括电耦合到I/O系统并配置成将第一芯片和第二芯片电连接到I/O系统的多个金属互连，其中所述多个金属互连的每个延伸穿过相应的通路以与相邻重分布层上的金属互连和第一或第二芯片上的芯片焊盘这两者之一形成直接金属连接。 
根据本发明的另一方面，一种形成嵌入式芯片封装的方法包括提 供初始的聚合物层压层和紧固到该层的第一芯片，第一芯片在其上具有芯片焊盘。该方法还包括：图案化初始的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的一部分向下延伸穿过相应的通路并直接金属化到第一芯片上的芯片焊盘；提供附加芯片；以及提供多个附加的聚合物层压层，其中所述多个附加的聚合物层压层的一部分包括在其中形成以用于放置第一芯片和附加芯片之一的芯片开口。该方法还包括：将附加芯片和所述多个附加的聚合物层压层中的每个选择性地耦合到初始的聚合物层压层；以及在耦合所述多个附加的聚合物层压层的每个之后，选择性地图案化该附加的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的每个延伸穿过相应的通路，并直接金属化到相邻的聚合物层压层上的金属互连和附加芯片上的芯片焊盘这两者之一。该方法还包括将多个输入/输出(I/O)连接电耦合到所述多个附加的聚合物层压层的最外面的聚合物层压层上的金属互连，其中这些I/O连接通过所述多个金属互连而电连接到第一芯片和附加芯片。 
根据本发明的又一方面，一种用于制造晶片级封装的方法包括：提供多个芯片，每个芯片具有其上形成的芯片焊盘；以及提供多个聚合物层压层，其中所述多个聚合物层压层的一部分的每个包括在其中形成以用于在其中放置所述多个芯片之一的芯片开口。该方法还包括使用所述多个芯片和所述多个聚合物层压层来组装晶片级封装，其中组装晶片级封装包括：将第一芯片施加到初始的聚合物层压层；以及图案化初始的聚合物层压层以包括多个通路和多个金属互连，其中所述多个金属互连的每个向下延伸穿过相应的通路以将初始的聚合物层压层电耦合到第一芯片。组装晶片级封装还包括：以堆叠的布置将附加的聚合物层压层和附加芯片选择性地施加到初始的聚合物层压层和第一芯片；以及在施加每个附加的聚合物层压层之后，图案化该附加的聚合物层压层以形成多个通路和向下延伸穿过这些通路的多个金属互连，以使得每个附加的聚合物层压层中的金属互连将该聚合 物层压层电耦合到之前施加的附加的聚合物层压层或之前施加的附加芯片。 
根据以下有关于附图来提供的本发明的优选实施例的详细描述，将更容易地理解这些和其它优点和特征。 
附图说明
附图示出目前预期用于实现本发明的实施例。 
图中： 
图1是根据本发明一个实施例的多个嵌入式芯片封装的俯视图。 
图2-10是根据本发明一个实施例的嵌入式芯片封装在制造/堆积工艺的各个阶段期间的示意截面侧视图。 
图11是根据本发明另一个实施例的嵌入式芯片封装的示意截面侧视图。 
图12是根据本发明另一个实施例的嵌入式芯片封装的示意截面侧视图。 
具体实施方式
本发明提供一种形成嵌入式芯片封装的方法。通过使用图案化的层压重分布层并相对于这些图案化的层放置芯片或电组件来制造嵌入式芯片封装。嵌入式芯片封装中的芯片/电组件以堆叠的布置来提供，并通过图案化的层压重分布层中形成的金属互连提供的直接金属连接而连接到输入/输出(I/O)系统。 
本发明的实施例针对嵌入式芯片封装(ECP)的堆积，ECP之中包括多个芯片(即，管芯)和/或电组件，它们嵌入在多个图案化的层压重分布层内并按3D堆叠的布置来布置。虽然下文在图1-12的实施例中将嵌入在ECP中的芯片和/或电组件特定称为芯片，但应理解，可在ECP中用其它电组件替代这些芯片，并且因此，本发明的实施例不只限于ECP中的芯片/管芯的堆叠。即，应将下文描述的ECP实施 例中的芯片的使用理解为涵盖可在ECP中以堆叠的布置来提供的其它电组件，如电阻器、电容器、电感器、或其它类似器件。 
参照图1，根据本发明的一个示范性实施例示出多个制造的ECP10或嵌入式芯片模块。每个ECP 10包括与多个重分布层14(即，层压层)连接并嵌入在其中的一个或多个芯片12(即，管芯)。每个芯片12由诸如硅或GaAs的半导体材料形成，并且制备成使得在它的表面上形成集成电路(IC)布局。所述多个重分布层14中的每个是能相对于芯片12放置的预先形成的层压薄片或薄膜的形式。重分布层14可由Kapton 
Figure GSA00000052825200051
Ultem 
Figure GSA00000052825200052
聚四氟乙烯(PTFE)、或另一个聚合物薄膜(如液晶聚合物(LCP)或聚酰亚胺材料)形成。如图1所示，每个ECP 10通过在相邻ECP 10之间的区域中切片穿过重分布层14而形成。 
参照图2-10，根据本发明的一个实施例阐述一种用于制造多个嵌入式芯片封装(ECP)10的技术。如图2所示，嵌入式芯片堆积工艺从初始的重分布层16的完整框架(frame)开始，初始的重分布层16被提供并安装在框架18上以允许在其上执行附加的制造步骤。如上所述，初始的重分布层16是柔性聚合物层压层的形式，如Kapton Ultem 
Figure GSA00000052825200054
聚四氟乙烯(PTFE)或另一个聚合物/聚酰亚胺薄膜，并具有允许由其生产多个ECP 10的尺寸。初始的重分布层16上包括预先图案化的区域20和未图案化的区域22，其中未图案化的区域22对应于其中将放置芯片的芯片区域。 
图3A-3B中示出初始的重分布层16的完整框架的一部分。根据本发明的一个实施例，初始的重分布层16作为“预先图案化的”层来提供，其在预先图案化的区域20中具有其上形成的多个基底金属互连(base metal interconnect)18，如图3A中所示。将粘合层24施加到初始的重分布层16的一面，并将芯片26(即，第一芯片)置于未图案化的区域22中。在本发明的一个示范性实施例中，芯片26具有减小的厚度，以使得芯片的总厚度是初始的重分布层16和/或随后 施加的重分布层的厚度的约1到3倍。因此，这个“超薄”芯片26的厚度远小于总ECP 10的厚度，这将在以下各图中说明。 
如图3B中所示，在施加芯片26之后，进一步图案化初始的重分布层16以形成多个通路28，这些通路28钻通形成该重分布层的聚合物材料。通路28形成在对应于基底金属互连18的位置，以便暴露基底金属互连18。附加通路28向下钻至芯片上的焊盘30，以便暴露这些焊盘。根据一个示范性实施例，通路28是通过激光烧蚀或激光打孔工艺而形成的。备选的是，还将认识到，通路28可通过其它方法来形成，这些方法包括：等离子体蚀刻、光界定(photo-definition)或机械打孔工艺。接着，金属层/材料32(例如，金属籽晶(seed metal)和/或铜)通过例如溅射或电镀工艺被施加到重分布层16上，并且然后形成金属互连34。根据本发明的一个实施例，对金属层/材料32进行图案化和蚀刻，以便形成从初始的重分布层16的前/顶表面36向下延伸穿过通路28的金属互连34。因此，金属互连34形成与基底金属互连18的电连接以及到芯片焊盘30的直接金属电连接。 
现在参照图4，在制造技术的下一步骤中，将附加的重分布层38、40层压到初始的重分布层16上。附加的重分布层38、40包括分别施加到初始的重分布层16的前表面和后表面的未切割的重分布层38和预先切割的重分布层40。在将预先切割的重分布层层压到初始的重分布层16之前，形成穿过预先切割的重分布层的芯片开口42(或多个芯片开口)。芯片开口42的尺寸和形状与将要放置到其中的芯片(即，芯片26)的尺寸和形状基本匹配。如图4中所示，预先切割的重分布层40的结果的形状是“窗口框架”构造的形状。虽然图4中将预先切割的重分布层40示为具有与芯片26的厚度匹配的厚度的单个层，但还认识到，也可施加总厚度与芯片26的厚度匹配的多个(例如，2个或3个)重分布层，而不是单个预先切割的重分布层40。 
如图4中所示，例如通过层压、旋涂(spin)或喷射(spray)工艺将粘合层24施加到未切割的重分布层38和预先切割的重分布层40 中每一层的将要附着到初始的重分布层16的那一面上。因此，根据本发明的一个示范性实施例，初始的重分布层16形成“中心”重分布层，而附加的重分布层38、40施加到初始的重分布层16的前/顶表面36和后/底表面44。这样的双面层压工艺用于减小传给初始的重分布层16的应力，并防止其翘曲。如图4中所示，与初始的重分布层16相比，预先切割的重分布层40具有增加的厚度。根据一个实施例，预先切割的重分布层40的厚度等于芯片26的厚度，使得芯片26的后/底表面46与预先切割的重分布层40的后/底表面48对齐。 
现在参照图5，在附加的重分布层38、40的每个中形成多个通路28。还形成/图案化金属互连34以向下延伸穿过通路28并穿过每个附加的重分布层38、40，使得将附加的重分布层38、40的每个电连接到初始的重分布层16。如图5中所示，对于沿第一方向50从初始的重分布层16的前/顶表面36延伸出来的未切割的重分布层38，从与第一方向50相反的第二方向52形成(即，钻出、激光烧蚀出)通路28。即，自顶向下形成未切割的重分布层38中的通路28。相反，对于沿第二方向52从初始的重分布层16的后/底表面44延伸出来的预先切割的重分布层40，从第一方向50钻出通路28。即，自底向上钻出预先切割的重分布层40中的通路28。 
如图6中所示，在制造技术的下一步骤中，将未图案化的预先切割的重分布层56和未图案化的未切割的重分布层58形式的另外的重分布层56、58添加到初始的重分布层16和重分布层38、40。将粘合层24施加到预先切割的重分布层56和未切割的重分布层58中的每个以提供接合材料。将预先切割的重分布层56施加/层压到沿第一方向50从初始的重分布层16的前/顶表面36延伸出来的重分布层38上。将未切割的重分布层58施加/层压到沿第二方向52从初始的重分布层16的后/底表面44延伸出来的重分布层40上以及芯片26的后/底表面46上。在制造工艺/技术的下一步骤中，如图7中所示，在附加的重分布层56、58的每个中形成多个通路28。还形成/图案化金属互连34 以向下延伸穿过通路28并穿过附加的重分布层56、58的每个，使得将附加的重分布层56、58的每个电连接到之前施加的重分布层38、40和初始的重分布层16。 
现在参照图8，在本发明的一个示范性实施例中，在ECBU工艺的下一步，添加附加的超薄芯片60、62。经由粘合层24分别将顶部芯片60和底部芯片62附连到附加的重分布层64、66。如图8中所示，将顶部芯片60施加到未切割、未图案化的重分布层64的面向现有嵌入式芯片组装(embedded chip assembly)70的表面68上。在将顶部芯片60置于粘合层24和重分布层64上之后，可执行真空层压和压力烘焙固化(pressure bake curing)工艺以将芯片60紧固到其上。然后，将粘合层24施加到顶部芯片60的底表面72和重分布层64的表面68以允许随后将顶部芯片/重分布层结构60、64放置到嵌入式芯片组装70。 
在制备和放置顶部芯片/重分布层结构60、64之前、期间或之后，将底部芯片62(经由粘合剂24)施加到未切割、未图案化的重分布层66的背对嵌入式芯片组装70的表面74上。在将底部芯片62放置到粘合层24和重分布层66上之后，可执行真空层压和压力烘焙固化工艺以将芯片62紧固到其上。在将底部芯片62紧固到重分布层66上之后，对重分布层66进行图案化以在其中形成多个通路28并形成向下延伸穿过通路28至底部芯片62上的焊盘30的金属互连34。即，金属互连34向下延伸至焊盘30以形成到底部芯片62的芯片焊盘30的直接金属电连接。 
然后，将粘合层24施加到重分布层66的面向嵌入式芯片组装70的表面76以允许随后将底部芯片/重分布层结构62、66放置到嵌入式芯片组装70。如图9中所示，在组装上执行重分布层64、66的附加图案化以及另外的重分布层78的放置。此附加图案化中包括的是重分布层64的图案化，其中对金属互连34进行图案化/蚀刻以向下延伸穿过通路28，使得形成到顶部芯片60的芯片焊盘30的直接金属电连 接。应认识到，随后可将任何数量的附加的重分布层78添加到组装70。重分布层的附加图案化和放置允许在组装中进一步布线，如基于ECP 10的设计要求所确定的。 
现在参照图10，在ECBU工艺的下一步骤中，将焊接掩膜层80施加到最外面的重分布层82。最外面的重分布层82上的焊接掩膜允许连接多个输入/输出(I/O)互连84。根据本发明的一个实施例，如图10中所示，将I/O互连84施加到最顶部的重分布/层压层82上的焊接掩膜以形成I/O系统互连86。在一个实施例中，将I/O互连84形成为焊接到焊接掩膜的球(即，焊球)。但是，还将预想到，可附连其它形式的I/O互连84，如电镀凸点、柱状凸点、金柱凸点(gold studbump)、金属填充聚合物凸点、或线接合连接/焊盘，以使得可在ECP10和它将附连到的母板(未示出)之间形成可靠的连接。 
由上述多个重分布层提供的金属互连34的重分布允许在ECP 10的顶表面上形成增加数量的I/O互连84。即，例如，由于金属互连34的重分布，可在ECP 10上更密集地装入焊接连接84。因此，在ECP 10上形成与常规焊球相比具有减小的间距和高度的焊接连接84。例如，焊接连接84可形成为具有180微米的高度和80微米的间距。在柔性聚合物层压/重分布层上以这样的尺寸形成焊接连接84减小了ECP 10与它将安装到的母板(未示出)之间的连接结合应力，从而还免去了对于现有技术中通常执行的将ECP 10焊接到母板之后将在焊接连接84、ECP 10和母板之间施加的底部填充环氧混合物的需要。 
如图10中进一步所示，并且根据本发明一个实施例，将表面安装无源器件88附连到另一个最外面的重分布层90(即，最底部的重分布层)。表面安装器件88可以是例如焊接到最外面的重分布层90上的金属互连34上的电容器、电阻器或电感器的形式。还将散热器92附连到最外面的重分布层90和底部芯片62以驱散来自ECP 10的热量。散热器92可由例如单片或两片铜片形成，该铜片通过导热粘合剂24粘合到最外面的重分布层90以及底部芯片62的后表面94。 备选的是，应认识到，可将附加的重分布层施加到最外面的重分布层90的底部芯片62周围的位置(即，在附加的重分布层中形成以接纳芯片62的芯片开口)，以使得ECP 10具有平坦后/底表面，从而允许将附加的I/O系统互连放置/连接到该表面。 
因此，如图10中所示的结果的ECP 10其中包括堆叠的3D布置中的多个芯片26、60、62，每个芯片具有通过金属互连34到I/O系统互连86的直接金属电连接。芯片26、60、62相对于彼此沿垂直方向堆叠，以便形成沿垂直方向的堆叠的芯片布置。如上所述，应理解，可在ECP 10中用其它电组件(电阻器、电容器、电感器等)替代芯片26、60、62，并且ECP 10中3D布置中的这些电组件的堆叠视为在本发明的范围内。 
现在参照图11，根据本发明的另一实施例，示出具有粘合到彼此并嵌入在层压重分布层102内的第一芯片98和第二芯片100的ECP96。更具体来说，第一芯片98的非活动表面104(即，后表面)粘合到第二芯片100的非活动表面106。 
如图12中所示，根据本发明的另一实施例，ECP 106包括布置/施加在共同水平面内的第一芯片108和第二芯片110。根据图12的实施例，第一和第二芯片108、110中的每个芯片的厚度均与单个重分布层112的厚度匹配，但还认识到，芯片108、110的厚度可等于总厚度与芯片108、110的厚度匹配的多个(例如，2个或3个)重分布层的厚度。第一和第二芯片108、110中的每个芯片置于重分布层112中形成的单独的芯片开口114内，以便布置在相同的水平面中。在重分布层112中图案化多个通路28和向下延伸穿过通路28的多个金属互连34，以使得金属互连延伸到第一和第二芯片108、110中的每个芯片上的焊盘30。即，金属互连34向下延伸至焊盘30以形成到第一和第二芯片108、110的芯片焊盘30的直接金属电连接。在相同平面(即，重分布层112)上并排嵌入第一和第二芯片108、110允许减少ECP 106中重分布层的数量，从而有助于减小ECP 106的总厚度并减 小相关联的生产成本。 
根据本发明的附加实施例，认识到，ECBU工艺可作为单面的堆积来执行，其中沿一个方向从初始的重分布层和芯片堆积附加芯片和重分布层。另外，认识到，可在ECP中包含比图10和图12的ECP中示出的芯片更多或更少的芯片。还预想到其它特征，例如ECP的两个外表面上的I/O连接和穿过ECP的电源和地平面。 
根据本发明的附加实施例，还认识到，上述ECP 10的实施例可与倒装芯片或线接合的芯片组合使用。上述ECP的3D堆叠的芯片布置的实现可与倒装芯片或线接合的芯片组合以相对于常规独立倒装芯片或线接合的芯片改善芯片封装的性能、微型化和可靠性，以及对于倒装芯片或线接合的芯片的堆叠能力。 
因此，根据本发明的一个实施例，一种嵌入式芯片封装包括沿垂直方向结合在一起以形成层压堆叠的多个重分布层，其中每个重分布层包括在其中形成的多个通路。该嵌入式芯片封装还包括：嵌入在层压堆叠中并包括多个芯片焊盘的第一芯片；包括多个芯片焊盘的第二芯片，它附连到层压堆叠并相对于第一芯片沿垂直方向堆叠；以及置于层压堆叠的最外面的重分布层上的输入/输出(I/O)系统。嵌入式芯片封装还包括电耦合到I/O系统并配置成将第一芯片和第二芯片电连接到I/O系统的多个金属互连，其中所述多个金属互连的每个延伸穿过相应的通路以与相邻重分布层上的金属互连和第一或第二芯片上的芯片焊盘这两者之一形成直接金属连接。 
根据本发明的另一个实施例，一种形成嵌入式芯片封装的方法包括提供初始的聚合物层压层和紧固到该层的第一芯片，第一芯片在其上具有芯片焊盘。该方法还包括：图案化初始的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的一部分向下延伸穿过相应的通路并直接金属化到第一芯片上的芯片焊盘；提供附加芯片；以及提供多个附加的聚合物层压层，其中所述多个附加的聚合物层压层的一部分包括在其中形成以用于放置第一芯片和附加芯片 之一的芯片开口。该方法还包括：将附加芯片和所述多个附加的聚合物层压层中的每个选择性地耦合到初始的聚合物层压层；以及在耦合所述多个附加的聚合物层压层的每个之后，选择性地图案化该附加的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的每个延伸穿过相应的通路，并直接金属化到相邻的聚合物层压层上的金属互连和附加芯片上的芯片焊盘这两者之一。该方法还包括将多个输入/输出(I/O)连接电耦合到所述多个附加的聚合物层压层的最外面的聚合物层压层上的金属互连，其中这些I/O连接通过所述多个金属互连而电连接到第一芯片和附加芯片。 
根据本发明的又一个实施例，一种用于制造晶片级封装的方法包括：提供多个芯片，每个芯片具有其上形成的芯片焊盘；以及提供多个聚合物层压层，其中所述多个聚合物层压层的一部分的每个包括在其中形成以用于在其中放置所述多个芯片之一的芯片开口。该方法还包括使用所述多个芯片和所述多个聚合物层压层来组装晶片级封装，其中组装晶片级封装包括：将第一芯片施加到初始的聚合物层压层；以及图案化初始的聚合物层压层以包括多个通路和多个金属互连，其中所述多个金属互连的每个向下延伸穿过相应的通路以将初始的聚合物层压层电耦合到第一芯片。组装晶片级封装还包括：以堆叠的布置将附加的聚合物层压层和附加芯片选择性地施加到初始的聚合物层压层和第一芯片；以及在施加每个附加的聚合物层压层之后，图案化该附加的聚合物层压层以形成多个通路和向下延伸穿过这些通路的多个金属互连，以使得每个附加的聚合物层压层中的金属互连将该聚合物层压层电耦合到之前施加的附加的聚合物层压层或之前施加的附加芯片。 
虽然仅关于有限数量的实施例详细描述了本发明，但应容易理解，本发明不限于这些公开的实施例。相反，本发明可修改成合并此前未描述的任何数量的变型、更改、替换或等效布置，但是它们与本发明的精神和范围相适应。另外，虽然描述了本发明的各种实施例， 但要理解，本发明的方面可只包括所描述的一些实施例。因此，本发明不应视为由以上描述所限制，而是仅由随附权利要求的范围来限制。 
部件列表： 
10嵌入式芯片封装(ECP) 
12芯片/管芯 
14重分布层 
16初始的重分布层 
18框架 
20预先图案化的区域 
22未图案化的区域 
24粘合层 
26芯片 
28通路 
30芯片焊盘 
32金属层/材料 
34金属互连 
36初始的重分布层前/顶表面 
38未切割的重分布层 
40预先切割的重分布层 
42芯片开口 
44初始的重分布层后/底表面 
46芯片后/底表面 
48预先切割的重分布层后/底表面 
50第一方向 
52第二方向 
56未图案化的预先切割的重分布层 
58未图案化的未切割的重分布层 
60附加芯片 
62附加芯片 
64重分布层 
66重分布层 
68重分布层表面 
70嵌入式芯片组装 
72芯片底表面 
74表面 
76表面 
78重分布层 
80焊接掩膜层 
82最外面的重分布层 
84输入/输出(I/O)互连 
86I/O系统互连 
88表面安装无源器件 
90最外面的重分布层 
92散热器 
94后表面 
96嵌入式芯片封装(ECP) 
98第一芯片 
100第二芯片 
102重分布层 
104非活动表面 
106非活动表面 
108第一芯片 
110第二芯片 
112单个重分布层 
114芯片开口。 

Claims (24)

1.一种嵌入式芯片封装，包括：
多个聚合物层压重分布层，沿垂直方向结合在一起以形成层压堆叠，其中每个聚合物层压重分布层包括在其中形成的多个通路；
第一芯片，嵌入在所述层压堆叠中并包括多个芯片焊盘；
第二芯片，附连到所述层压堆叠并相对于所述第一芯片沿垂直方向堆叠，所述第二芯片包括多个芯片焊盘；
输入/输出I/O系统，置于所述层压堆叠的最外面的聚合物层压重分布层上；以及
多个金属互连，电耦合到所述I/O系统并配置成将所述第一芯片和所述第二芯片电连接到所述I/O系统，其中所述多个金属互连的每个延伸穿过相应的通路并且被直接金属化到所述第一和第二芯片上的芯片焊盘和相邻的聚合物层压重分布层上的金属互连之一。
2.如权利要求1所述的嵌入式芯片封装，还包括安置在所述多个聚合物层压重分布层的每个聚合物层压重分布层之间的粘合层。
3.如权利要求1所述的嵌入式芯片封装，其中所述多个金属互连的一部分延伸到所述最外面的聚合物层压重分布层的外表面上。
4.如权利要求3所述的嵌入式芯片封装，其中所述最外面的聚合物层压重分布层包括最顶部的重分布层和最底部的重分布层中的至少一个；并且
其中所述I/O系统置于所述多个金属互连的所述部分上。
5.如权利要求1所述的嵌入式芯片封装，还包括附连到所述层压堆叠的另一最外面的聚合物层压重分布层上的所述多个金属互连的一部分的电容器、电感器和电阻器中的至少一个。
6.如权利要求5所述的嵌入式芯片封装，还包括附连到所述层压堆叠的所述另一最外面的聚合物层压重分布层的散热器。
7.如权利要求1所述的嵌入式芯片封装，其中所述多个聚合物层压重分布层包括：
中心重分布层，具有沿第一方向面向的第一表面和沿与所述第一方向相反的第二方向面向的第二表面；
至少一个第一附加的重分布层，粘合到所述中心重分布层的第一表面并沿所述第一方向延伸出来；
至少一个第二附加的重分布层，粘合到所述中心重分布层的第二表面并沿所述第二方向延伸出来；
其中粘合到所述中心重分布层的第一表面的所述至少一个第一附加的重分布层中的每个包括多个通路和多个金属互连，所述多个金属互连延伸穿过所述通路并延伸到所述第一附加的重分布层的背对所述中心重分布层的表面上；并且
其中粘合到所述中心重分布层的第二表面的所述至少一个第二附加的重分布层中的每个包括多个通路和多个金属互连，所述多个金属互连延伸穿过所述通路并延伸到所述第二附加的重分布层的背对所述中心重分布层的表面上。
8.如权利要求1所述的嵌入式芯片封装，其中所述多个聚合物层压重分布层的一部分包括在其中形成的芯片开口，所述多个聚合物层压重分布层的所述部分中的相应聚合物层压重分布层中的芯片开口的尺寸设计成在其中接纳所述第一芯片和所述第二芯片之一。
9.如权利要求8所述的嵌入式芯片封装，其中具有在其中形成的所述芯片开口的所述聚合物层压重分布层的每个的厚度等于置于其芯片开口中的芯片的厚度。
10.如权利要求1所述的嵌入式芯片封装，其中所述第一芯片的非活动表面粘合到所述第二芯片的非活动表面。
11.一种形成嵌入式芯片封装的方法，包括：
提供初始的聚合物层压层和紧固到该层的第一芯片，所述第一芯片在其上具有芯片焊盘；
图案化所述初始的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的一部分向下延伸穿过相应的通路并被直接金属化到所述第一芯片上的所述芯片焊盘；
提供附加芯片；
提供多个附加的聚合物层压层，其中所述多个附加的聚合物层压层的一部分包括在其中形成以用于放置所述第一芯片和所述附加芯片之一的芯片开口；
将附加芯片和所述多个附加的聚合物层压层中的每个选择性地耦合到所述初始的聚合物层压层；
在耦合所述多个附加的聚合物层压层的每个之后，选择性地图案化所述附加的聚合物层压层以包括多个通路和多个金属互连，以使得所述多个金属互连的每个延伸穿过相应的通路，并被直接金属化到相邻的聚合物层压层上的金属互连和所述附加芯片上的芯片焊盘之一；以及
将多个输入/输出I/O连接电耦合到所述多个附加的聚合物层压层的最外面的聚合物层压层上的金属互连，其中所述I/O连接通过所述多个金属互连而电连接到所述第一芯片和所述附加芯片。
12.如权利要求11所述的方法，还包括通过激光切割和芯片打孔操作之一来形成所述芯片开口。
13.如权利要求11所述的方法，其中选择性地耦合所述多个附加的聚合物层中的每个包括：将附加的聚合物层耦合到所述初始的聚合物层压层的前表面以及将附加的聚合物层耦合到所述初始的聚合物层压层的后表面。
14.如权利要求13所述的方法，其中图案化所述附加的聚合物层压层的每个包括：
从第一方向在所述初始的聚合物层压层的前表面上在所述至少一个附加的聚合物层的每个中形成所述多个通路；以及
从第二方向在所述初始的聚合物层压层的后表面上在所述至少一个附加的聚合物层的每个中形成所述多个通路。
15.如权利要求11所述的方法，其中形成所述多个金属互连包括：
在所述聚合物层压层上沉积金属材料；以及
图案化和蚀刻所述金属材料以形成所述金属互连。
16.如权利要求11所述的方法，还包括在邻近的聚合物层压层之间以及在每个芯片和邻近的聚合物层压层之间施加层压粘合剂、喷射涂层粘合剂以及旋压粘合剂之一。
17.如权利要求11所述的方法，还包括将无源器件施加到另一最外面的聚合物层压层上的金属互连，所述无源器件包括电容器、电感器以及电阻器中的至少一个。
18.如权利要求17所述的方法，还包括将散热器附连到另一最外面的聚合物层压层。
19.如权利要求11所述的方法，其中选择性地施加所述附加芯片包括将所述附加芯片直接粘合到所述第一芯片，以使得所述附加芯片的非活动表面粘合到所述第一芯片的非活动表面。
20.如权利要求11所述的方法，其中图案化所述初始的聚合物层压层和所述附加的聚合物层压层的每个包括在其中激光钻出所述多个通路。
21.一种用于制造晶片级封装的方法，包括：
提供多个芯片，所述多个芯片的每个芯片具有其上形成的芯片焊盘；
提供多个聚合物层压层，其中所述多个聚合物层压层的一部分的每个包括在其中形成以用于在其中放置所述多个芯片之一的芯片开口；以及
使用所述多个芯片和所述多个聚合物层压层来组装晶片级封装，其中组装所述晶片级封装包括：将第一芯片施加到初始的聚合物层压层；图案化所述初始的聚合物层压层以包括多个通路和多个金属互连，所述多个金属互连的每个向下延伸穿过相应的通路以将所述初始的聚合物层压层电耦合到所述第一芯片；以堆叠的布置将附加的聚合物层压层和附加芯片选择性地施加到所述初始的聚合物层压层和所述第一芯片；以及
在施加每个附加的聚合物层压层之后，图案化该附加的聚合物层压层以形成多个通路和向下延伸穿过这些通路的多个金属互连，以使得所述附加的聚合物层压层的每层中的金属互连将该聚合物层压层电耦合到之前施加的聚合物层压层或之前施加的芯片。
22.如权利要求21所述的方法，还包括将多个输入/输出I/O连接互连到最外面的聚合物层压层上的金属互连。
23.如权利要求21所述的方法，其中选择性地施加附加的聚合物层压层包括：使用双面层压工艺将附加的聚合物层压层层压到所述初始的聚合物层压层。
24.如权利要求21所述的方法，还包括：
在所述多个聚合物层压层的所述部分的每个中形成所述芯片开口；以及
其中，选择性地施加所述附加的聚合物层压层包括：以堆叠的布置施加所述附加的聚合物层压层，使得所述芯片开口的中心被垂直对齐。
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EP2228824A1 (en) 2010-09-15
US8008125B2 (en) 2011-08-30
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