WO2014185204A1 - 部品内蔵基板及び通信モジュール - Google Patents
部品内蔵基板及び通信モジュール Download PDFInfo
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- WO2014185204A1 WO2014185204A1 PCT/JP2014/060577 JP2014060577W WO2014185204A1 WO 2014185204 A1 WO2014185204 A1 WO 2014185204A1 JP 2014060577 W JP2014060577 W JP 2014060577W WO 2014185204 A1 WO2014185204 A1 WO 2014185204A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0141—Liquid crystal polymer [LCP]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
Definitions
- the present invention relates to a component built-in substrate in which a plurality of components are built in a multilayer substrate and a communication module using the same.
- Patent Document 1 describes a structure in which two ICs are built in a multilayer printed board formed by alternately laminating a plurality of insulating layers and conductor layers.
- each IC is arranged in different layers of the multilayer printed board.
- the electrodes (terminals) of each IC are routed to other internal circuits or to the outside via internal wiring formed in the multilayer printed board.
- a component built-in substrate having two built-in components (ICs) like the multilayer printed board shown in Patent Document 1 when both external connection electrodes are on the mounting surface, they are arranged on the surface facing the mounting surface.
- the internal wiring from the IC and the internal wiring from the IC arranged on the mounting surface side are concentrated on the mounting surface side.
- the number of electrodes (terminals) in the IC increases, the number of internal wirings increases, and the internal wirings are more densely arranged on the mounting surface side, making it difficult to route the internal wirings.
- an area corresponding to the space may be secured in the multilayer printed board, but the outer shape of the multilayer printed board becomes large.
- an object of the present invention is to provide a component-embedded substrate and a communication module that do not increase in size even if a plurality of components are embedded.
- the component-embedded substrate of the present invention includes a plurality of built-in components that are electrically connected to a multilayer substrate in which a plurality of resin films are laminated, and has a mounting electrode formed on one main surface.
- the component-embedded substrate of the present invention is located in a layer close to the mounting electrode and includes a first built-in component including a terminal to be electrically connected, and the mounting electrode rather than the layer in which the first built-in component is located.
- a second built-in component provided with terminals that are electrically connected to each other, and the resin film is made of a thermoplastic resin, and the number of terminals of the first built-in component is More than the number of terminals of the second built-in component, the area of the first built-in component is smaller than the area of the second built-in component in plan view.
- the terminals of the first built-in component and the terminals of the second built-in component are electrically connected to the mounting electrodes via internal wirings. That is, most of the internal wiring from the first built-in component and the internal wiring from the second built-in component go to the mounting surface where the mounting electrode is provided. As a result, the internal wiring is concentrated on the mounting surface side of the multilayer substrate, and it is difficult to route the internal wiring. Since the number of terminals of the first built-in component is larger than the number of terminals of the second built-in component, the internal wiring is more difficult to route.
- the first built-in component has a smaller area than the second built-in component and is disposed closer to the mounting surface than the second built-in component, so that a space for routing the internal wiring is mounted on the multilayer board. It can be secured on the surface side.
- the component built-in substrate can be enlarged in the outer shape of the multilayer board to secure a space for routing the internal wiring, or the internal wiring can be divided into upper and lower layers.
- the first built-in component and the second built-in component can be built without increasing the number of layers for detouring, that is, with the size remaining small.
- a multilayer substrate is formed when a plurality of sheets containing a thermoplastic resin (for example, polyimide or liquid crystal polymer) are laminated and thermocompression bonded together.
- a thermoplastic resin for example, polyimide or liquid crystal polymer
- a conventional build-up method in which resin layers are laminated one by one as a build-up layer requires a certain amount of thickness for a base material that becomes a core layer.
- the multilayer substrate stacking method of the present invention does not require a base material to be a core layer. As a result, the multilayer substrate can be reduced in thickness. Further, since the multilayer substrate of the present invention does not need to be laminated one by one, it is simpler than the conventional build-up method.
- the first built-in component may overlap the second built-in component, or may all overlap the second built-in component.
- the more the first built-in component and the second built-in component overlap the smaller the area of one main surface of the multilayer substrate can be reduced. Even in this case, since the area of the first built-in component is smaller than the area of the second built-in component, and the first built-in component is arranged closer to the mounting surface than the second built-in component, the space for routing the internal wiring The component-embedded substrate can be further downsized while ensuring the above.
- terminal of the first built-in component and the terminal of the second built-in component may include those that are electrically connected to an interlayer connection conductor formed on the multilayer substrate.
- the component-embedded substrate is thinner than when a layer coated with solder is provided.
- the second built-in component may be less likely to radiate electromagnetic waves than the first built-in component.
- the second built-in component arranged on the side facing the mounting surface serves as an electromagnetic shield, so that the electromagnetic waves are not easily radiated outside the component built-in substrate.
- the first built-in component is an RFIC that processes a high-frequency signal
- the second built-in component includes a component built-in substrate that is a secure IC having a security function
- a communication module is obtained.
- FIG. 3 is a top view, a cross-sectional view along AA, and a bottom view of the component-embedded substrate 1 according to the first embodiment.
- FIG. 4 is a top view of the secure IC 11 and a top view of the RFIC 13. It is side surface sectional drawing of the state which decomposed
- 1 is a circuit block diagram of a communication module 300 including a component built-in substrate 1 according to Embodiment 1.
- the component-embedded substrate 1 according to the first embodiment will be described with reference to FIGS.
- FIG. 1A is a top view of the component built-in substrate 1 according to the first embodiment
- FIG. 1B is a cross-sectional view taken along the line AA of the component built-in substrate 1.
- FIG. 1C is a bottom view of the component built-in substrate 1. In FIG. 1C, only the mounting electrodes 17 that are essential for the description are shown.
- FIG. 2A is a top view of the secure IC 11
- FIG. 2B is a top view of the RFIC 13.
- the surface in the + Z direction is the upper surface of the component-embedded substrate 1
- the surface in the -Z direction is the lower surface.
- the component-embedded substrate 1 is, for example, a rectangular parallelepiped, and has a width direction (+ X, ⁇ X direction in the drawing) and a depth direction (+ Y, ⁇ Y in the drawing). Is shorter in the height direction (in the + Z and -Z directions in the figure) than in the direction.
- the actual component-embedded substrate 1 has an extremely low height (for example, 0.5 mm), but in FIG. 1B, it is exaggerated to be higher than the actual height for explanation.
- the component built-in substrate 1 includes a multilayer substrate 10, a plurality of mounting electrodes 17, and a plurality of wirings 18.
- the multilayer substrate 10 is a rectangular parallelepiped, and is formed by laminating insulating resin films 100 to 105 (details will be described later).
- the plurality of mounting electrodes 17 are respectively provided on the lower surface of the multilayer substrate 10 as shown in FIG. 1 (B) and FIG. 1 (C).
- the plurality of wirings 18 are respectively provided on the upper surface of the multilayer substrate 10.
- the plurality of mounting electrodes 17 and the plurality of wirings 18 are each made of a conductive material (for example, a metal foil made of copper (Cu)).
- the multilayer substrate 10 includes a secure IC 11, an RFIC 13, a plurality of interlayer connection conductors 15, and a plurality of conductor patterns 16 inside.
- the secure IC 11 and the RFIC 13 each have a plate shape. As shown in FIGS. 2A and 2B, the secure IC 11 has a larger main surface area than the RFIC 13.
- the RFIC 13 is arranged in a lower direction ( ⁇ Z direction) than the secure IC 11 as shown in FIG. That is, the RFIC 13 is arranged in a layer closer to the plurality of mounting electrodes 17 than the secure IC 11.
- the RFIC 13 is mounted in the multilayer substrate 10 so that the main surface is covered with the secure IC 11 when viewed in plan.
- the secure IC 11 includes a memory 110 (see FIG. 4).
- the secure IC 11 is an IC having a security function and prevents cloning of authentication information stored in the internal memory 110.
- the RFIC 13 is an IC having a function of modulating / demodulating a high frequency signal and controlling communication with the outside.
- the secure IC 11 includes a terminal 12A and a terminal 12B on the upper surface (surface in the + Z direction).
- the RFIC 13 includes terminals 14A to 14P on the upper surface (surface in the + Z direction). That is, the RFIC 13 includes more terminals than the secure IC 11.
- the number of terminals of the secure IC 11 and the number of terminals of the RFIC 13 are not limited to the numbers of terminals illustrated in FIGS. 2A and 2B, respectively.
- Each IC may be provided with a dummy terminal that is not connected to the internal wiring such as the interlayer connection conductor 15, but such a terminal is not included in the number of terminals of the present invention. .
- the plurality of interlayer connection conductors 15 have substantially columnar shapes extending in the + Z and ⁇ Z directions, respectively.
- Each of the plurality of interlayer connection conductors 15 is made of a conductive material (for example, a material containing tin (Sn) or silver (Ag) as a main component).
- Each of the plurality of conductor patterns 16 has a flat film shape and is disposed so as to be parallel to the upper surface of the component-embedded substrate 1.
- Each of the plurality of conductor patterns 16 is made of a conductive material (for example, a metal foil made of copper (Cu)). The plurality of conductor patterns 16 are electrically connected to the plurality of interlayer connection conductors 15, respectively.
- the plurality of wirings 18 provided on the upper surface of the multilayer substrate 10 are also electrically connected to the plurality of interlayer connection conductors 15, respectively.
- the plurality of mounting electrodes 17 are also electrically connected to the plurality of interlayer connection conductors 15, respectively.
- the plurality of interlayer connection conductors 15, the plurality of conductor patterns 16, and the plurality of wirings 18 constitute a circuit that connects the secure IC 11 and the RFIC 13 to the plurality of mounting electrodes 17.
- the terminals 12A and 12B provided on the upper surface of the secure IC 11 are electrically connected to a plurality of interlayer connection conductors 15 as shown in FIG.
- the terminals 14A and 14B provided on the upper surface of the RFIC 13 are electrically connected to the plurality of interlayer connection conductors 15, respectively.
- the terminals 14C to 14P of the RFIC 13 are also electrically connected to the plurality of interlayer connection conductors 15, respectively. That is, the number of terminals electrically connected to the plurality of mounting electrodes 17 in the RFIC 13 is larger than the number of terminals electrically connected to the plurality of mounting electrodes 17 in the secure IC 11.
- the terminal 12A, the terminal 12B, and the terminals 14A to 14P may be electrically connected to each other via the interlayer connection conductor 15, the conductor pattern 16, and the wiring 18, but most of them are the interlayer connection conductor 15 and the conductor.
- Each of the plurality of mounting electrodes 17 is electrically connected via the pattern 16 and the wiring 18.
- the RFIC 13 has a smaller area than the secure IC 11 in plan view of the component-embedded substrate 1, and the RFIC 13 is disposed on the mounting surface side of the secure IC 11, so according to the difference in area between the secure IC 11 and the RFIC 13.
- a space for routing the internal wiring can be secured on the mounting surface side of the multilayer substrate 10. Therefore, even if a plurality of ICs are built in the component built-in substrate 1, the plurality of ICs and the plurality of mounting electrodes 17 can be connected by appropriately drawing the internal wiring.
- the RFIC 13 having a small outer shape is arranged on the mounting surface side, so that the component built-in substrate 1 can secure a space for routing the internal wiring. Therefore, without increasing the area of the layers of the multilayer substrate 10 or increasing the number of layers of the multilayer substrate 10 in order to bypass internal wiring to upper and lower layers, that is, an IC having a small size and a large number of terminals. Multiple components can be built in.
- the RFIC 13 is entirely overlapped with the secure IC 11. For this reason, compared with the case where RFIC13 does not overlap with secure IC11, the area of the layer (XY plane) of multilayer substrate 10 may be smaller. That is, it is possible to further reduce the size of the component-embedded substrate 1 while securing a space for routing the internal wiring.
- the routing of the internal wiring is further complicated. Specifically, the internal wiring must be routed outside the region other than the RFIC 13 in a plan view of the multilayer substrate 10. However, if the configuration of the present embodiment is used, the internal wiring can be appropriately routed even in such a mounting mode.
- FIG. 3 is a side cross-sectional view of the component-embedded substrate 1 in an exploded state.
- the multilayer substrate 10 is formed by laminating the insulating resin films 100 to 105.
- the insulating resin films 100 to 105 are each made of a thermoplastic resin (for example, polyimide or liquid crystal polymer).
- a copper film is applied to one side of the insulating resin films 100 to 105.
- the plurality of wirings 18 and the plurality of conductor patterns 16 are formed by patterning each of the surfaces of the insulating resin films 100 to 105 to which the copper films are attached.
- the plurality of interlayer connection conductors 15 are provided with holes penetrating the insulating resin films 100 to 105 from the surface opposite to the copper bonding surface of the insulating resin films 100 to 105, and the through holes are filled with a conductive paste. It is formed by solidifying.
- the secure IC 11 is temporarily press-bonded to the lower surface (the surface in the ⁇ Z direction) of the insulating resin film 100.
- the insulating resin film 101 is formed with a cavity 106 in which the secure IC 11 temporarily bonded to the insulating resin film 100 is stored.
- the cavity 106 is formed by a hole that penetrates the insulating resin film 101.
- the RFIC 13 is temporarily pressure-bonded to the lower surface (the surface in the ⁇ Z direction) of the insulating resin film 103.
- the insulating resin film 104 is formed with a cavity 107 in which the RFIC 13 temporarily bonded to the insulating resin film 103 is stored.
- the cavity 107 is formed by a hole that penetrates the insulating resin film 104.
- the insulating resin films 100 to 105 are each thermocompression bonded after being laminated.
- each of the insulating resin films 100 to 105 softens and flows, and fills the cavity 106 and the cavity 107.
- the secure IC 11 and the RFIC 13 are fixed, and the multilayer substrate 10 is formed.
- the conductive paste described above is solidified to form a plurality of interlayer connection conductors 15.
- the conventional build-up method in which the resin layers are laminated one by one as the build-up layer requires a certain amount of thickness for the base material that becomes the core layer.
- the method for laminating the multilayer substrate 10 does not require a base material to be a core layer.
- the multilayer substrate 10 can be reduced in thickness.
- the multilayer substrate 10 does not need to be laminated one by one, it is simpler than the build-up method.
- the plurality of interlayer connection conductors 15 are solidified and joined to the terminals 12A, 12B, and 14A to 14P, respectively.
- the plurality of interlayer connection conductors 15 are likely to be pressed. As a result, the plurality of interlayer connection conductors 15 are more strongly bonded to the terminal 12A, the terminal 12B, and the terminals 14A to 14P, respectively.
- the plurality of interlayer connection conductors 15 are not only connected to the conductor pattern 16 and the wiring 18 but also to the terminal 12A, the terminal 12B, and the terminals 14A to 14P. Also join more strongly.
- the RFIC 13 Since the RFIC 13 is covered with the secure IC 11 and the surface of the RFIC 13 with the terminals 14A to 14P (the surface in the + Z direction) and the lower surface of the secure IC 11 (the surface in the ⁇ Z direction) face each other in parallel, the RFIC 13
- the terminals 14A to 14P are uniformly applied with the pressure during thermocompression bonding of the multilayer substrate 10. Therefore, the bonding reliability between the terminals 14A to 14P of the RFIC 13 and the plurality of interlayer connection conductors 15 can be improved.
- the secure IC 11 having a larger area in plan view than the RFIC 13 is disposed so as to overlap with the plane (+ Z direction plane) where the terminals 14A to 14P of the RFIC 13 are located.
- the joint reliability with the conductor 15 can be further improved.
- interlayer connection conductor 15, the wiring 18, the conductor pattern 16, the terminal 12A, the terminal 12B, and the terminals 14A to 14P can be joined at the same time when the insulating resin films 100 to 105 are thermocompression bonded.
- FIG. 4 is a circuit block diagram of the communication module 300 including the component built-in substrate 1.
- the communication module 300 includes a component built-in substrate 1 and a mounting substrate 200.
- the mounting substrate 200 is a mounting substrate that realizes an RF circuit, on which a circuit element group for realizing the RF circuit is mounted. Further, the component built-in substrate 1 is mounted on the mounting substrate 200.
- the RFIC 13 is connected to the filter element 201 of the mounting substrate 200, and the secure IC 11 is connected to the RFIC 13.
- the memory 110 is built in the secure IC 11 and is not directly read / written from other than the secure IC 11.
- the RFIC 13 processes high-frequency signals, it is easier to radiate electromagnetic waves than the secure IC 11.
- the electromagnetic wave radiated from the RFIC 13 in the + Z direction is electromagnetically shielded by the secure IC 11 arranged in the + Z direction from the RFIC 13 as shown in FIG. Hard to leak out of 1.
- the secure IC 11 since the secure IC 11 has a larger area than the RFIC 13 and covers the RFIC 13 in a plan view of the component-embedded substrate 1, the secure IC 11 can perform electromagnetic shielding more effectively.
- the component built-in substrate 1 includes the secure IC 11 and the RFIC 13, but a component that easily radiates electromagnetic waves is disposed near the plurality of mounting electrodes 17, and a component that does not easily radiate electromagnetic waves is disposed on the plurality of mounting electrodes 17. It may be a mode of being arranged far away. In this aspect, the electromagnetic wave hardly leaks to the outside on the side opposite to the mounting surface side of the component-embedded substrate 1.
- the RFICs 13 are covered with the secure ICs 11. However, a part of the RFICs 13 may be overlapped.
- the RFIC 13 and the secure IC 11 are used as the first built-in component and the second built-in component, respectively.
- other built-in components can be used.
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Abstract
Description
10…多層基板
11…セキュアIC
13…RFIC
12A、12B、14A~14P…端子
15…層間接続導体
16…導体パターン
17…実装電極
18…配線
100~105…絶縁性樹脂フィルム
106、107…空洞部
110…メモリ
201…フィルタ素子
200…実装基板
300…通信モジュール
Claims (6)
- 樹脂フィルムが複数積層された多層基板に電気的に接続されている複数の内蔵部品が内蔵され、一主面に実装電極が形成された部品内蔵基板であって、
前記実装電極に近い層に位置し、電気的に接続される端子を備える第1の内蔵部品と、
前記第1の内蔵部品が位置する層よりも前記実装電極から離れた層に位置し、電気的に接続される端子を備える第2の内蔵部品と、を備え、
前記樹脂フィルムは、熱可塑性樹脂からなり、
前記第1の内蔵部品の端子の数は、前記第2の内蔵部品の端子の数より多く、
平面視において、前記第1の内蔵部品の面積は、前記第2の内蔵部品の面積より小さい
部品内蔵基板。 - 平面視において、前記第1の内蔵部品は、前記第2の内蔵部品に重複する
請求項1に記載の部品内蔵基板。 - 平面視において、前記第1の内蔵部品は、すべて前記第2の内蔵部品に重複する
請求項2に記載の部品内蔵基板。 - 前記第1の内蔵部品の端子及び前記第2の内蔵部品の端子は、前記多層基板に形成された層間接続導体に電気的に接続されるものを含む、
請求項1乃至請求項3のいずれかに記載の部品内蔵基板。 - 前記第2の内蔵部品は、前記第1の内蔵部品に比べて電磁波を放射しにくい
請求項2乃至請求項4のいずれかに記載の部品内蔵基板。 - 前記第1の内蔵部品は、高周波信号を処理するRFICであり、
前記第2の内蔵部品は、セキュリティ機能を備えたセキュアICである
請求項1乃至請求項5のいずれかに記載の部品内蔵基板を構成要素として含む
通信モジュール。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201490000446.8U CN205093051U (zh) | 2013-05-14 | 2014-04-14 | 部件内置基板以及通信模块 |
JP2014533294A JP5692473B1 (ja) | 2013-05-14 | 2014-04-14 | 部品内蔵基板及び通信モジュール |
US14/939,102 US9629249B2 (en) | 2013-05-14 | 2015-11-12 | Component-embedded substrate and communication module |
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JP2013102054 | 2013-05-14 | ||
JP2013-102054 | 2013-05-14 |
Related Child Applications (1)
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US14/939,102 Continuation US9629249B2 (en) | 2013-05-14 | 2015-11-12 | Component-embedded substrate and communication module |
Publications (1)
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WO2014185204A1 true WO2014185204A1 (ja) | 2014-11-20 |
Family
ID=51898185
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PCT/JP2014/060577 WO2014185204A1 (ja) | 2013-05-14 | 2014-04-14 | 部品内蔵基板及び通信モジュール |
Country Status (4)
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US (1) | US9629249B2 (ja) |
JP (1) | JP5692473B1 (ja) |
CN (1) | CN205093051U (ja) |
WO (1) | WO2014185204A1 (ja) |
Cited By (1)
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WO2017149983A1 (ja) * | 2016-03-01 | 2017-09-08 | ソニー株式会社 | 半導体装置、電子モジュール、電子機器、および半導体装置の製造方法 |
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JP7004004B2 (ja) * | 2017-10-26 | 2022-01-21 | 株式会社村田製作所 | 多層基板、インターポーザおよび電子機器 |
KR102671975B1 (ko) * | 2019-08-29 | 2024-06-05 | 삼성전기주식회사 | 전자부품 내장기판 |
KR20210076586A (ko) * | 2019-12-16 | 2021-06-24 | 삼성전기주식회사 | 전자부품 내장기판 |
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Also Published As
Publication number | Publication date |
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CN205093051U (zh) | 2016-03-16 |
JPWO2014185204A1 (ja) | 2017-02-23 |
JP5692473B1 (ja) | 2015-04-01 |
US20160066428A1 (en) | 2016-03-03 |
US9629249B2 (en) | 2017-04-18 |
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