CN101681850B - 焊接装置以及焊接方法 - Google Patents
焊接装置以及焊接方法 Download PDFInfo
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- CN101681850B CN101681850B CN2008800060838A CN200880006083A CN101681850B CN 101681850 B CN101681850 B CN 101681850B CN 2008800060838 A CN2008800060838 A CN 2008800060838A CN 200880006083 A CN200880006083 A CN 200880006083A CN 101681850 B CN101681850 B CN 101681850B
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 199
- 230000007246 mechanism Effects 0.000 claims abstract description 79
- 239000002270 dispersing agent Substances 0.000 claims abstract description 59
- 238000010438 heat treatment Methods 0.000 claims abstract description 34
- 238000005245 sintering Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims description 194
- 239000002184 metal Substances 0.000 claims description 194
- 229910000679 solder Inorganic materials 0.000 claims description 124
- 230000004907 flux Effects 0.000 claims description 117
- 239000002082 metal nanoparticle Substances 0.000 claims description 78
- 239000007767 bonding agent Substances 0.000 claims description 75
- 238000003466 welding Methods 0.000 claims description 62
- 239000011248 coating agent Substances 0.000 claims description 29
- 238000000576 coating method Methods 0.000 claims description 29
- 230000008859 change Effects 0.000 claims description 18
- 235000011837 pasties Nutrition 0.000 claims description 18
- 238000002788 crimping Methods 0.000 claims description 12
- 230000009471 action Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000011230 binding agent Substances 0.000 abstract 2
- 239000002105 nanoparticle Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 58
- 238000005476 soldering Methods 0.000 description 24
- 239000003795 chemical substances by application Substances 0.000 description 22
- 238000002347 injection Methods 0.000 description 21
- 239000007924 injection Substances 0.000 description 21
- 230000000694 effects Effects 0.000 description 17
- 230000008569 process Effects 0.000 description 14
- 238000010521 absorption reaction Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000032258 transport Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 9
- 238000001179 sorption measurement Methods 0.000 description 8
- 239000004568 cement Substances 0.000 description 7
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000003475 lamination Methods 0.000 description 7
- 230000008646 thermal stress Effects 0.000 description 7
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000002904 solvent Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000004927 fusion Effects 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 241000196324 Embryophyta Species 0.000 description 3
- -1 alkyl hydrosulfide Chemical compound 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000010023 transfer printing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 2
- 235000011613 Pinus brutia Nutrition 0.000 description 2
- 241000018646 Pinus brutia Species 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- SNRUBQQJIBEYMU-UHFFFAOYSA-N dodecane Chemical compound CCCCCCCCCCCC SNRUBQQJIBEYMU-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001815 facial effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000009940 knitting Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- BGHCVCJVXZWKCC-UHFFFAOYSA-N tetradecane Chemical compound CCCCCCCCCCCCCC BGHCVCJVXZWKCC-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000003973 alkyl amines Chemical class 0.000 description 1
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005520 electrodynamics Effects 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 238000009766 low-temperature sintering Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002798 polar solvent Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- CMXPERZAMAQXSF-UHFFFAOYSA-M sodium;1,4-bis(2-ethylhexoxy)-1,4-dioxobutane-2-sulfonate;1,8-dihydroxyanthracene-9,10-dione Chemical compound [Na+].O=C1C2=CC=CC(O)=C2C(=O)C2=C1C=CC=C2O.CCCCC(CC)COC(=O)CC(S([O-])(=O)=O)C(=O)OCC(CC)CCCC CMXPERZAMAQXSF-UHFFFAOYSA-M 0.000 description 1
- 238000000935 solvent evaporation Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008093 supporting effect Effects 0.000 description 1
- 229940116411 terpineol Drugs 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/06—Solder feeding devices; Solder melting pans
- B23K3/0607—Solder feeding devices
- B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/11318—Manufacturing methods by local deposition of the material of the bump connector in liquid form by dispensing droplets
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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Abstract
本发明涉及焊接装置以及焊接方法。在使用金属纳米焊剂接合半导体芯片(12)的电极及电路线路板(19)的电极的焊接装置(10)中,包括:凸块形成机构(20),将金属纳米焊剂的微液滴射出到电极上,形成凸块;一次接合机构(50),将半导体芯片(12)的凸块推压到电路线路板(19)的凸块上,以非导通状态一次接合各电极;二次接合机构(80),包含将一次接合的各凸块朝接合方向加压的加压器,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。由此,减小接合载荷,同时能以简便方法有效地进行各电极的接合。
Description
技术领域
本发明涉及使用金属纳米焊剂(nano paste)使得电极接合的焊接(bonding)装置以及焊接方法。
背景技术
为了接合半导体芯片等电子器件的电极和电路线路板上的电路图案的电极,如特开平9-326416号公报所记载那样,使用以下方法:在半导体芯片等电子器件的电极焊接点(pad)上形成焊锡凸块,将形成的焊锡凸块朝着电路线路板的电极朝下配置,进行加热接合。又,如特开平10-150075号公报所记载那样,使用以下倒装式接合(flip chip bonding)方法:在半导体芯片等电子器件的电极面上形成的金凸块表面上涂布导电性接合剂,使得半导体芯片翻转,将金凸块朝着电路线路板的电极压接后,加热接合部位,使得半导体芯片的电极与电路线路板的电路图案的电极接合。
但是,如特开平9-326416号公报所记载的现有技术那样,使用焊锡欲三维叠层接合时,因加热使得先接合的接合部熔融,有时导致接合可靠性低下。因此,作为不使用焊锡凸块使得各电极接合的方法,提议使用包含金属超微粒的金属焊剂的各种各样方法。
在特开平9-326416号公报中,提出以下方法:将银的超微粉末分散在溶剂中,调制银微粒焊剂,在电路线路板的端子电极上形成银微粒焊剂球,用面朝下方法使得半导体元件的电极接合在电路线路板的端子电极上形成的球上之后,使得银微粒焊剂中的甲苯等溶剂蒸发后,以100~250℃的温度烧成,使得半导体元件和电路线路板电接合。记载着该方法场合,当将烧成温度设为200~250℃时,在热风炉进行30分钟烧成,能实现电接合。
在特开2006-54212号公报中,记载着以下方法:在线路板的电极表面上印刷包含平均粒径30nm以下的金属纳米粒子及分散剂的金属纳米粒子焊剂后,加热固化金属纳米焊剂,在线路板的电极表面形成金属纳米粒子烧成的金属纳米粒子膜,将半导体芯片的电极上形成的凸块用超声波焊接在该金属纳米粒子膜上,进行金属接合。在该接合方法中,通过加热装置将涂布在线路板电极上的金属纳米粒子焊剂加热到250℃,通过保持60分钟的加热养护,金属纳米粒子互相热粘接,在电极上形成金属纳米粒子膜。
在特开2006-202938号公报中,公开了以下方法:使得由平均粒径100nm以下的金属构成的超微粒分散在有机系溶剂中,形成金属纳米焊剂,使用该金属纳米焊剂,接合半导体元件的金属层和金属线路板。在该接合方法中,包含在半导体元件的金属层及金属线路板及金属纳米焊剂中的金属由金、银、铂、铜、镍、铬、铁、铅、锆之中某种金属、或包含上述金属中至少一种的合金、或上述金属或合金的混合物构成,通过加热,加压,或上述组合,使得上述溶剂挥发,凝集上述超微粒形成接合层,使得上述接合层介在,接合半导体元件的金属层和金属线路板。
在特开2006-202938号公报中,记载着金属纳米焊剂使用银纳米焊剂,使得半导体元件的银的金属层接合在铜的金属线路板上场合,对半导体元件和金属线路板加压,成为数百kPa~数MPa左右的表面压力,通过进行300℃左右的加热,能进行半导体元件的银的金属层和铜的金属线路板的接合。
又,在特开平10-150075号公报中,关于使用导电性接合剂的倒装式接合方法,记载着半导体芯片的电极上形成的金凸块的高度均化为偏差范围成为5μm以内,通过正确地控制使得该半导体芯片翻转时与导电性接合剂的距离,能在金凸块顶端转印适量的导电性接合剂,能防止跨接或接合不良等缺陷。
在特开平9-326416号公报、特开2006-202938号公报所记载的现有技术中,在使用金属纳米焊剂接合半导体元件的电极等场合,需要对接合面加压,同时,在200~300℃左右温度下保持30~60分钟。但是,在半导体芯片向电路线路板的焊接中,必须在短时间处理大量的半导体芯片的接合,因此,在接合工序中途,这种长时间的保持使得制造效率显著低下。
在特开2006-54212号公报中记载的线路板电极上,形成金属纳米粒子膜,将半导体芯片的电极上形成的凸块用超声波焊接在该金属纳米粒子膜上,进行金属接合的方法,由于通过超声波焊接使得金属之间接合,因此,接合时施加在半导体芯片及电路线路板上的力变大。另一方面,根据近年对半导体装置的薄型化要求,半导体芯片及电路线路板的厚度非常薄,存在焊接时因接合载荷引起损伤的可能性,要求降低接合载荷。
在特开平10-150075号公报所记载的现有技术中,需要涂布使得半导体芯片的电极和电路线路板的电极接合的导电性接合剂的装置、工序,此外,为了使得各电极良好地接合,需要抑制在半导体芯片的电极上形成的金凸块的高度偏差,同时,在微小的金凸块顶端转印适量的导电性接合剂,由于形成金凸块以及转印导电性接合剂时的金凸块的位置控制,装置很复杂。
发明内容
本发明就是为解决上述现有技术所存在的问题而提出来的,本发明的目的在于,提供降低半导体芯片的电极和线路板的电极之间的接合载荷、同时能以简便方法有效地进行各电极接合的装置以及方法。
本发明的焊接装置系接合半导体芯片的电极及线路板的电极的焊接装置,其特征在于,该焊接装置包括:
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接装置系接合半导体芯片的电极及线路板的电极的焊接装置,其特征在于,该焊接装置包括:
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在各电极上形成凸块,使得所述凸块互相压接,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热各凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接装置系三维安装半导体芯片的焊接装置,其特征在于,该焊接装置包括:
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在半导体芯片的电极上形成凸块,将在一半导体芯片的电极上形成的凸块推压到另一半导体芯片的电极上形成的凸块上,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,将凸块加热到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接装置系接合半导体芯片的电极及线路板的电极的焊接装置,其特征在于,该焊接装置包括:
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,将在某一方的电极上形成的凸块推压到在另一方的电极上形成的金属突起上,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
在本发明的焊接装置中,合适的是,加压器包含对向配置、保持半导体芯片或线路板的保持板,驱动至少一方的保持板朝着接合方向进退的保持板驱动部,以及控制保持板驱动部的进退动作的加压控制部;所述加压控制部设有加压力变更手段,根据时间通过保持板驱动部驱动保持板进退,使得施加到凸块上的加压力变化。又,合适的是,加压力变更手段包含缩颈形成手段,在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
在本发明的焊接装置中,合适的是,二次接合机构是在内部包含将一次接合的凸块朝接合方向加压的加压器的加热炉。又,合适的是,设有多个二次接合机构。
本发明的焊接方法系接合半导体芯片的电极及线路板的电极的焊接方法,其特征在于,该焊接方法包括:
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接方法系接合半导体芯片的电极及线路板的电极的焊接方法,其特征在于,该焊接方法包括:
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在各电极上形成凸块,使得所述凸块互相压接,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热各凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接方法系三维安装半导体芯片的焊接方法,其特征在于,该焊接方法包括:
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在半导体芯片的电极上形成凸块,将在一半导体芯片的电极上形成的凸块推压到另一半导体芯片的电极上形成的凸块上,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,将凸块加热到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
本发明的焊接方法系接合半导体芯片的电极及线路板的电极的焊接方法,其特征在于,该焊接方法包括;
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上形成的金属突起上,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
在本发明的焊接方法中,合适的是,二次接合工序在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
本发明的焊接装置及焊接方法具有减小半导体芯片的电极和线路板的电极之间的接合载荷、同时能以简便方法有效地进行各电极的接合的效果。
附图说明
图1是表示本发明实施形态的焊接装置的平面图。
图2是表示本发明实施形态的焊接装置的凸块形成机构的立体图。
图3表示本发明实施形态的焊接装置的一次接合机构。
图4是表示本发明实施形态的焊接装置的焊接台的一次接合的立体图。
图5是表示本发明实施形态的焊接装置的加压加热炉的截面图。
图6是表示通过本发明实施形态的焊接方法接合电路线路板和半导体芯片的工序的说明图。
图7是表示通过本发明实施形态的焊接方法进行接合工序的工序流程图。
图8是表示通过本发明另一实施形态的焊接方法三维叠层接合半导体芯片工序的说明图。
图9是表示通过本发明另一实施形态的焊接方法三维叠层接合半导体芯片工序的说明图。
图10是表示通过本发明另一实施形态的焊接方法在接合部的金属层形成缩颈工序的说明图。
图11是表示通过本发明另一实施形态的焊接方法在接合部的金属层形成缩颈工序的流程图。
图12是表示通过本发明另一实施形态的焊接方法接合电路线路板和半导体芯片的工序的说明图。
图13是表示通过本发明另一实施形态的焊接方法接合电路线路板和半导体芯片的工序的说明图。
图14是表示通过本发明另一实施形态的焊接方法接合电路线路板和半导体芯片的工序的说明图。
具体实施方式
下面参照附图说明本发明的较佳的实施形态。如图1所示,本实施形态的焊接装置10包括配置在框架11中的凸块(bump)形成机构20,底充(underfill)剂涂布机构40,一次接合机构50,二次接合机构80。二次接合机构80包括第一加压加热炉81及第二加压加热炉84两个加压加热炉。在图1中,在焊接装置10的左侧的材料供给侧,设有供给晶片18的晶片库13,以及供给电路线路板(substrate)19的线路板库14,在图1中,在焊接装置10的右侧的制品输出侧,设有储存所完成制品的制品库17。晶片库13,凸块形成机构20以及一次接合机构50由晶片输送用导轨15连接为能运送作为材料的晶片18,线路板库14,凸块形成机构20,底充剂涂布机构40,一次接合机构50以及二次接合机构80由输送线路板19的线路板输送用导轨16连接为能将作为材料的电路线路板顺序运送到各机构。又,线路板输送用导轨16通过二次接合机构入口导轨93与二次接合机构80连接,构成为能从一次接合机构50将电路线路板19输送到二次接合机构80,二次接合机构出口导轨94连接二次接合机构80的出口和制品库17,构成为能将半导体芯片12接合结束的电路线路板19从二次接合机构80运送到制品库17。又,在以下说明中,将图1中箭头X所示的、由焊接装置10的各输送导轨15、16运送晶片18或线路板19的方向设为X方向,将图1中箭头Y所示的、与各输送导轨15、16垂直方向设为Y方向,将图1中与纸面垂直的高度方向设为Z方向。
晶片库13在壳体中设有用于收纳晶片18的架,所述晶片形成多个芯片,根据需要将晶片18载置在与晶片库13连接的输送导轨15或没有图示的输送装置上,输出到凸块形成机构20。晶片18的大小大多用8英寸。直径8英寸的晶片18能形成半导体芯片12约400个左右。又,晶片18可以在背面粘接例如粘接带,使得晶片18芯片化,通过分割成各半导体芯片12的芯片化工序,在半导体芯片12之间残留未切断部,在粘接例如粘接带的背面侧能一体地保持各半导体芯片12,即使被芯片化,各半导体芯片12也不分离,构成为能一体地处理晶片18。
线路板库14在壳体中设有用于收纳多个电路线路板19的架,根据需要将电路线路板19载置在与线路板库14连接的线路板输送用导轨16上,输出到凸块形成机构20。电路线路板是在玻璃环氧树脂等的树脂线路板上印刷通过铜等金属连接半导体芯片12的连接电路。
作为材料的半导体芯片12也可以不是作为晶片18供给,而是通过芯片化,分离为各半导体芯片12,使得各半导体芯片12排列在盘上供给。这种场合,可以与线路板库14同样,设有具有收纳多个盘的架的盘库。又,也可以构成焊接装置10,分别设有多个晶片厍13、线路板库14,使得材料供给总是不停止。
如图2及图1所示,凸块形成机构20包括安装在基体21上的晶片凸台22,线路板凸台23,XY驱动机25。所述XY驱动机25沿X、Y方向驱动用于射出金属纳米焊剂的微液滴的射出头26。
晶片凸台22设在两根晶片输送用导轨15a、15b之间,具有在其上面真空吸附晶片18、能固定成平面状的大小,在其上面设有没有图示的真空吸附孔。真空吸附孔与没有图示的真空装置连接。又,线路板凸台设在两根线路板输送用导轨16a、16b之间,具有在其上面真空吸附线路板19、能固定成平面状的大小。线路板凸台23也与晶片凸台22同样,在其上面设有没有图示的真空吸附孔,各真空吸附孔与共用真空装置连接。
XY驱动机25设有射出头26,Y方向框架27,两个门形框架24。Y方向框架设有沿与各输送导轨15、16垂直的Y方向导向的导向件,射出头26滑动自如地安装在Y方向框架上,通过安装在射出头26或Y方向框架27的伺服电机进行Y方向驱动。Y方向框架27的两侧由两个门形框架24支承,使得Y方向框架27能沿X方向滑动自如,通过设在门形框架24或Y方向框架27的伺服电机进行X方向驱动。凸块形成控制部501根据来自没有图示的摄像装置等的位置检测器的位置信号,驱动XY驱动机25的各伺服电机,实行射出头26的位置控制。又,凸块形成控制部501控制从射出喷嘴射出的金属纳米焊剂的微液滴的大小或微液滴的射出间隔。在本实施形态中,说明使用伺服电机作为驱动源,但各驱动源并不局限于伺服电机,也可以使用线性电机、步进电机等其他型式的驱动源。
射出头26从前端的射出喷嘴26a以金属纳米焊剂的微液滴射出储存的金属纳米焊剂,例如,由喷墨头等构成,由压电薄膜或压电驱动器射出微液滴。只要射出头26可以射出微液滴,并不局限于喷墨头,由例如分配器头或微吸管等构成也很合适。
如图1所示,底充剂涂布机构40包括XY台41,分配器头42,分配器臂43,分配器单元44,分配台45。
XY台41在其上面支承分配器头42,使得分配器头42朝着X、Y两方向滑动自如,分配器头42通过安装在XY台41或分配器头42的伺服电机在XY面内被驱动。在分配器头42的前端,安装分配器臂43,在分配器臂43上安装分配器单元44。在分配器头42上安装Z方向电机,通过驱动分配器臂43回转,沿上下方向驱动安装在前端的分配器单元,调整分配器单元44的离开电路线路板19的Z方向高度。分配器单元44设有没有图示的储存底充剂的储存部,以及从前端排出底充剂的排出喷嘴,使得底充剂排出的空气压力配管与储存部连接。又,分配台45设在两根线路板输送用导轨16a、16b之间,构成为在其上面真空吸附线路板19、能固定成平面状。
载置在线路板输送用导轨16、从凸块形成机构20运送来的线路板19若来到分配台45位置,则通过真空吸附固定在分配台45,驱动分配器头42及分配器臂43,使得与分配器单元44的排出喷嘴位置一致,将底充剂涂布在线路板19的接合面侧。
在本实施形态中,说明涂布底充剂在与线路板凸台23不同的分配台45实行,但是并不局限于此,既可以通过真空吸附固定在线路板凸台23时,将底充剂涂布在线路板表面,也可以通过真空吸附将晶片18固定在晶片凸台22时,将底充剂涂布在晶片18上的半导体芯片12上。这种场合,底充剂涂布机构40配置在框架11中,使得安装在分配器臂43前端的分配器单元44能位于晶片凸台22、线路板凸台23之上。又,在本实施形态中,说明底充剂涂布机构40具有能通过XY台41朝两方向移动的分配器头42,但是,并不局限于此,只要能使得分配器单元44移动到所定位置,并不局限于XY台41,也可以组合线性导向器等构成移动机构。
如图1所示,一次接合机构50包括保持晶片的晶片架70,进行半导体芯片12的拾取及反转的半导体芯片拾取部60,将半导体芯片12焊接在线路板19上的焊接部58。
如图1所示,晶片架70将从晶片凸台22运送来的晶片18水平地真空吸附在晶片台71上保持着。如图3所示,在晶片台71内部,设有芯片顶起单元72,将包含在晶片18中的多个半导体芯片12之一朝着Z方向顶起,使其与其他半导体芯片12产生阶梯差。又,晶片台71通过设在下部的回转驱动机构73以及连接轴74,能驱动其回转。
如图1所示,半导体芯片拾取部60与晶片架70邻接设置,包括XY台61,拾取头62,拾取臂63,拾取工具64。XY台61在其上面支承拾取头62,使其朝着X、Y两方向滑动自如,拾取头62由安装在XY台61或拾取头62的伺服电机驱动在XY面内移动。在拾取头62前端安装拾取臂63,在拾取臂63安装拾取工具64。在拾取头62上安装Z方向电机,通过驱动拾取臂63回转,使得安装在前端的拾取工具64沿晶片18的接离方向移动。
如图3所示,拾取工具64设有吸附筒夹(collet)67,绕回转轴66回转。吸附筒夹67在吸附面上具有真空吸附用的吸附孔69,使得该吸附孔69成为真空,同时,通过芯片顶起单元72的顶起动作,使得半导体芯片12真空吸附在吸附筒夹67上,不接触半导体芯片12的电极上的凸块,在吸附半导体芯片12状态下,通过使得绕回转轴66回转,能使得半导体芯片12反转。
如图1所示,焊接部58与线路板输送用导轨16邻接设置,包括XY台51,焊接头52,焊接臂53,焊接工具54。XY台51在其上面支承焊接头52,使其朝着X、Y两方向滑动自如,焊接头52由安装在XY台51或焊接头52的伺服电机驱动在XY面内移动。在焊接头52前端安装焊接臂53,在焊接臂53安装焊接工具54。在焊接头52上安装Z方向电机,通过驱动焊接臂53回转,使得安装在前端的焊接工具54沿线路板19的接离方向移动。
又,如图3及图1的点划线所示,焊接部58和半导体芯片拾取部60配置在以下那样的位置:使得焊接工具54与拾取工具64接近,能将通过吸附筒夹67回转被反转的半导体芯片12交接给设有真空吸附用的吸附孔59的焊接工具54。
如图3及图4所示,焊接台55设在两根线路板输送用导轨16a、16b之间,构成为在其上面真空吸附线路板19、能固定成平面状。
如图4所示,在焊接工具54设有面部56以及超声波振子57。设在焊接工具54的接合面侧的面部56构成为能保持半导体芯片12,将其推压到线路板19上。在面部56的半导体芯片12的吸附面上,设有真空吸附用的吸附孔59,构成为能通过真空吸附保持半导体芯片12。又,在焊接工具54的长度方向一端安装超声波振子57,构成为能通过其超声波加振使得面部56沿焊接工具54长度方向振动。焊接部58构成为通过没有图示的检测位置用的摄像装置,检测线路板19的位置,能将半导体芯片12推压在所定位置。
如图3所示,焊接部58的XY台51,焊接头52,半导体芯片拾取部60的XY台61,拾取头62,晶片架70的芯片顶起单元72,回转驱动机构73分别与焊接控制部502连接,根据焊接控制部502的指令被驱动。
在本实施形态中,说明半导体芯片拾取部60设有XY台61,在其上配置拾取头62,使其朝着X、Y方向移动,焊接部58设有XY台51,在其上配置焊接头52,使其朝着X、Y方向移动,同时,能驱动安装在各头62,52的各臂63,53前端的拾取工具64,焊接工具54沿上下方向移动,但是,只要能使得拾取工具64,焊接工具54移动到所定位置,本发明并不局限于上述结构,例如,也可以组合多个线性导向器,将拾取工具64,焊接工具54移动到所定位置。又,通过使得晶片架70的回转动作和半导体芯片拾取部60的拾取动作协同,构成为使得拾取头62仅仅沿Y方向移动,也非常合适。
在本实施形态中,通过半导体芯片拾取部60的吸附筒夹67回转,使得半导体芯片12反转,将反转的半导体芯片12直接交接给焊接工具54,使得反转的半导体芯片12保持在焊接工具54,但是,本发明并不局限于上述结构,也可以暂时将从晶片18拾取的半导体芯片12吸附在没有图示的回转台上,使得该回转台反转,以使得半导体芯片12反转的状态吸附在拾取台上面,进行交接,由焊接工具54及附反转的半导体芯片12进行焊接。
如图5所示,第一加压加热炉81,第二加压加热炉84包括从上下夹入电路线路板19及半导体芯片12的上部保持板82a,85a,以及下部保持板82b,85b,驱动各上部保持板82a,85a沿半导体芯片12的接合方向进退的驱动器83,86,加热内部的加热器89。各驱动器83,86通过驱动轴87及球接头88与上部保持板82a,85a连接,能均等地对电路线路板19及半导体芯片12加压。又,下部保持板82b,85b固定在第一加压加热炉81,第二加压加热炉84的壳体上。上部保持板82a,85a及下部保持板82b,85b设有真空吸附电路线路板19或半导体芯片12的真空吸附孔91a,91b。各真空吸附孔91a,91b与没有图示的真空装置连接。又,第一加压加热炉81,第二加压加热炉84设有将电路线路板19运入各保持板82,85的运入口95,以及将电路线路板19运出的运出口96。二次接合机构入口导轨93与第一加压加热炉81,第二加压加热炉84的各运入口95连接,二次接合机构出口导轨94与第一加压加热炉81,第二加压加热炉84的各运出口96连接。
各驱动器83,86与加压控制部503连接,根据加压控制部503的指令驱动各驱动器83,86。各驱动器83,86既可以是例如电动式,也可以通过油缸等驱动进退。又,加热器89也与加压控制部连接,控制第一加压加热炉81,第二加压加热炉84内的温度。加热器89既可以由例如电热丝构成,也可以将由设在外部的热风发生器等产生的高温热风导入第一加压加热炉81,第二加压加热炉84内,进行内部加热。又,也可以直接将加热器安装在上部保持板82a,85a及下部保持板82b,85b,一边将半导体芯片12朝着线路板19加压,一边加热半导体芯片12及线路板19,进行各凸块200的加热。
下面,说明本实施形态的焊接装置动作,在说明焊接装置整体动作前,说明在电极12a上形成凸块200,一次接合,二次接合。
如图6(a)所示,在电极12a上形成凸块200是从射出头26的射出喷嘴26a向电极12a射出金属纳米焊剂的微液滴100进行的。金属纳米焊剂由使得导电性金属微细化的金属纳米粒子103构成,在金属纳米焊剂的分散剂的表面,金属纳米粒子103能保持分散状态,使得上述分散剂以涂布状态分散在糊状的粘接剂101中。作为构成金属纳米粒子103的微细化的导电性金属,可以使用例如金,银,铜,铂,钯,镍,铝等。作为涂布在金属纳米粒子103表面的分散剂,可以使用烷基胺、烷基硫醇、烷基二醇等。又,糊状的粘接剂101可使用将起着作为有机粘接剂作用的热硬化性树脂成分,含有在室温附近不容易蒸发的沸点较高的非极性溶剂或低极性溶剂中制得,所述溶剂可以列举例如萜品醇、干洗溶剂汽油、二甲苯、甲苯、十四烷、十二烷等的分散溶剂。
如图6(a)所示,若从射出头26的射出喷嘴26a射出金属纳米焊剂的微液滴100,则微液滴附着在电极12a表面。并且,通过射出金属纳米焊剂的微液滴100使其叠层,在电极12a上能形成前端变细的锥形凸块200。从射出头26射出的金属纳米焊剂的微液滴的射出位置、间隔等由凸块形成控制部形成适合半导体芯片12种类的凸块形状。通过使用例如用于喷墨那样的射出头作为射出头26,可以在短时间内射出许多微液滴100叠层。这样,在线路板19及半导体芯片12的各电极19a,12a上形成凸块200后,通过图1所示的半导体芯片拾取部60将半导体芯片12从晶片18拾取、反转后,将反转的半导体芯片12保持在焊接工具54,如图6(b)所示,使得各电极12a,19a的凸块200的位置一致。
如图6(c)所示,各电极12a,19a的凸块200的位置一致后,使得图3所示的焊接工具54朝着线路板19往下移动,使得形成在半导体芯片12的电极12a的凸块200与形成在线路板19的电极19a的凸块200压接,进行一次接合。该一次接合时压接表面压力设为以往技术中将金属凸块接合到金属电极时必要的表面压力的1/100~1/200左右的微小表面压力。若在这种微小表面压力下,使得凸块200之间压接,则能仅仅使得形成凸块200表面的粘接剂之间压接,分散在粘接剂中的含有的金属纳米粒子103之间不接合状态。在该接合中,仅仅粘接剂之间压接,因此,各电极12a和19a之间,不会电导通,成为非导通状态。又,在该一次接合时,通过使得安装在焊接工具54上的超声波振子振动,保持在焊接工具54上的半导体芯片12沿横向振动,位于接合线201附近的各凸块的前端部分互相摩擦。由此,各凸块200的接合线201附近的温度上升。于是,凸块200的表面的粘接剂之间熔接,能使得一次接合能可靠地接合。但是,通过所述超声波振子等的加温可以加热到比粘接剂的有机物质挥发除去的粘接剂除去温度低的温度。
一次接合仅仅凸块200表面的粘接剂101之间接合,其粘接力弱,但能成为半导体芯片12不与线路板19分离程度的强度。又,若能成为半导体芯片12不与线路板19分离程度的强度,则即使形成在半导体芯片12的多个电极12a上的凸块200与形成在线路板19的多个电极19a上的凸块200没有全部相互接合,也没有关系,只要一部分接合就行。因此,即使不是高精度地形成凸块200的高度,对于一次接合也足够。又,通过喷墨方式那样的简便方法能形成凸块200,能使得凸块形成机构简单化。
如图6(d)所示,在半导体芯片12一次接合在线路板19上的状态下,使得半导体芯片12朝着线路板19沿接合方向加压凸块200,同时,在加热炉中,将凸块200的温度加热到比涂布到粘接剂及金属纳米粒子表面的分散剂的除去温度高的温度,例如150~250℃左右。于是,通过挥发除去粘接剂101中的有机物质,分散剂也因温度上升从金属纳米粒子103表面脱离而除去,金属纳米粒子103之间直接接触,开始金属纳米粒子103特有的低温烧结。
另一方面,若如上所述进行加热及加压,由于涂布在构成金属纳米焊剂的粘接剂101及金属纳米粒子表面的分散剂中包含的有机成分,金属纳米粒子103的表面和电极12a,19a的金属表面被氧化还原,因金属纳米粒子103凝集开始互相结合。结果,各电极12a,19a因金属层300接合,各电极之间成为导通状态。这样,通过在低温下加压烧结金属纳米粒子103,通过金属层300使得电极12a,19a之间导通接合,这是二次接合。在二次接合中,通过比通常金属的熔融温度低很多的温度,使得金属纳米粒子103之间烧结,但加压烧结后的金属层300具有不上升到与通常金属相同温度不熔融的特性。又,通过同时加热及加压,能除去残存在金属纳米粒子103之间的气体,能得到精细的金属层300。
又,通过图1所示的底充剂涂布机构40涂布底充剂场合,一次接合时,底充剂充填在半导体芯片12和线路板19之间的间隙,在二次接合中充填的底充剂热硬化粘接半导体芯片12及线路板19。通过该底充剂能使得半导体芯片12和线路板19之间的接合强度增大。
下面说明本发明的焊接装置的整体动作。如图7的步骤S101所示,从晶片库13输出的晶片18运送到晶片凸台22,通过真空吸附固定在晶片凸台22上。接着,如图7的步骤S102及图6(a)所示,朝着晶片18的各半导体芯片12的各电极12a,从射出喷嘴26a射出金属纳米焊剂的微液滴100,形成凸块200。凸块200的形成由图2所示的凸块形成控制部501控制。若向晶片18的全部半导体芯片12的电极12a形成凸块200结束,则如图7的步骤S103所示,将晶片18运送到晶片架70。运送到晶片架70的晶片18被真空吸附固定在晶片台71上。
如图7的步骤S104以及图3所示,焊接控制部502通过芯片顶起单元72顶起所选择的半导体芯片12使其上升,不使得拾取臂63前端的吸附筒夹67与上升的半导体芯片12的电极上的凸块200接触,拾取半导体芯片12。接着,如图7的步骤S105以及图3的点划线所示,焊接控制部502使得拾取臂63上升,使得吸附筒夹67作180度回转,使得半导体芯片12反转,使得拾取头62朝着焊接头52侧移动到交接位置。
如图7的步骤S106以及图3的点划线所示,焊接控制部502使得焊接头52朝着拾取头62移动,使得焊接工具54的位置直到交接位置后,开放吸附筒夹67的吸附面的真空,同时,能真空吸附焊接工具54的吸附面,从吸附筒夹67向焊接工具54交接半导体芯片12。
另一方面,如图7的步骤S201以及图1所示,从线路板库14输出线路板19,运送到线路板凸台23,通过真空吸附固定在线路板凸台23上。接着,如图7的步骤S202及图6(a)所示,凸块形成控制部501控制使得从射出喷嘴26a向线路板19的各电极19a射出金属纳米焊剂的微液滴100,形成凸块200。若向线路板19的全部电极19a形成凸块200结束,则如图7的步骤S203所示,将线路板19运送到底充剂涂布机构40,通过真空吸附固定在分配台45上。接着,如图7的步骤S204以及图1所示,从分配器单元44前端的喷嘴向形成凸块200的线路板19排出底充剂,将底充剂涂布在线路板19上。如图7的步骤S205以及图1所示,完成涂布底充剂的线路板19运送到焊接台55,通过真空吸附固定在焊接台55上。
如图7的步骤S206以及图3,图4所示,焊接控制部502移动焊接头52,使得保持在焊接工具54上的半导体芯片12的电极12a上形成的凸块200位置,与形成在线路板19的电极19a上形成的凸块200位置一致。接着,焊接控制部502使得焊接臂53往下移动,将保持在焊接工具54上的半导体芯片12的电极12a上形成的凸块200推压到形成在线路板19的电极19a上形成的凸块200上。焊接控制部502控制焊接头52的Z方向电机,使得压接时的加压力成为通常金属凸块之间接合时的加压力的1/100~1/200左右的压力。此时,焊接控制部502使得超声波振子57振动,使得半导体芯片12侧的凸块200与线路板19侧的凸块200的接触面摩擦,产生摩擦热,如图6(c)所示,进行各凸块200的粘接剂之间接合的一次接合。在该一次接合中,各凸块的加热是使得超声波振子57振动产生摩擦热,但是,各凸块表面的加热手段只要使得其表面温度比室温高、比粘接剂的有机物质挥发的粘接剂除去温度低的温度,能使其上升到粘接剂软化程度的温度,也可以不使用超声波振子57加热,例如,局部喷吹温风使得温度上升,或通过放射热等进行加热。又,通过使得半导体芯片12压接在线路板19上,底充剂充填在半导体芯片12和线路板19之间的间隙。
该一次接合是以小的载荷将半导体芯片12压接在线路板19上的接合,处理时间非常短,能以一秒以下时间接合各半导体芯片12。因此,能使得一次接合成为高速处理。
半导体芯片12经一次接合的线路板19由图1所示的二次接合机构入口导轨93运送到第一加压加热炉81,第二加压加热炉84中某个。如图7的步骤S207所示,当第一加压加热炉81没有处于加热中,能运入线路板19场合,如图7的步骤S208所示,线路板19由二次接合机构入口导轨93横向运送到第一加压加热炉81,运入到第一加压加热炉81的各保持板82a,82b之间。又,如图7的步骤S207所示,当第一加压加热炉81处于加热中,不能运入线路板19场合,如图7的步骤S209所示,线路板19由二次接合机构入口导轨93横向运送到第二加压加热炉84,运入到第二加压加热炉84的各保持板85a,85b之间。
如图7的步骤S210及图5所示,若线路板19运送到第一加压加热炉81的保持板82a,82b之间或第二加压加热炉84的保持板85a,85b之间,则加压控制部503驱动上述驱动器83,86,使得上部保持板82a,82b往下移动,将半导体芯片12推压在线路板19上,朝接合方向对各电极12a,19a的凸块200加压。加压时的加压压力设为通常使得金属凸块之间压接场合的1/20程度低的加压力。又,加压控制部503控制加热器89,使得第一加压加热炉81,第二加压加热炉84的内部温度成为对于二次接合必要的150~250℃。通过能将加压压力设为以往接合金属凸块之间时的加压力的1/20程度,即使接合薄的半导体芯片12或薄的线路板19时,具有能减少损伤半导体芯片12或线路板19的效果。
如图7的步骤S211所示,加压控制部503监视所定的加压压力以及所定的加热温度的状态是否已保持所定时间。该保持时间根据所使用的金属纳米焊剂种类等而不同,大多采用60分钟程度的保持时间。接着,如图7的步骤S212及图5所示,若经过所定的保持时间,则加压控制部503使得驱动器83,86上升,停止对半导体芯片12和线路板19加压。通过结束上述保持,结束二次接合,各电极通过金属层300接合成导通状态。又,二次接合时,底充剂热硬化,粘接半导体芯片12及线路板19。结束二次接合的线路板19从如图1所示的运出口96由二次接合机构出口导轨94运送到制品库17。若在制品库17码放所定数量的制品,从制品库17运出制品。
二次接合在加压加热炉中保持60分钟程度的加压加热是必要的处理,通过设置二台能成批处理多个电路线路板19的加压加热炉,能缩短每个半导体芯片12的接合处理时间。例如,若从8英寸晶片二片取出的约800个半导体芯片12,使得上述半导体芯片12全部与多个线路板19一次接合,将该经一次接合的约800个半导体芯片12放入一个加压加热炉,为了二次接合,保持60分钟,则每一个半导体芯片12的二次接合必要的时间为大约4.5秒。因此,具有能提高半导体芯片12的接合效率的效果。
本实施形态在一次接合中,能通过以往的金属凸块接合时的加压力的1/100~1/200程度的加压力,使得半导体芯片12和线路板19接合,在二次接合中,能通过以往的金属凸块的接合时的加压力的1/20程度的加压力,使得半导体芯片12和线路板19接合,因此,与以往的金属凸块之间接合比较,能通过非常低的加压力使得半导体芯片12和线路板19的各电极12a,19a接合,因此,具有能减少因焊接引起的半导体芯片12或线路板19的损伤。又,本实施形态分为一次接合及二次接合两个处理工序,在所述一次接合中,能以短时间接合处理使用金属纳米焊剂的各电极12a,19a的接合,在所述二次接合中,必须长时间地保持加压加热,将能短时间处理的一次接合设为连续处理,将成为长时间处理的二次接合设为成批处理,具有能缩短每个半导体芯片12的接合时间、能使用金属纳米焊剂有效地接合半导体芯片12及线路板19的效果。又,本实施形态通过将金属纳米焊剂的微液滴射出在半导体芯片12及线路板19的各电极12a,19a上,形成凸块,因此,能通过喷墨方式等构成凸块形成机构,不需要以往用于形成凸块那样的大装置,具有能使得焊接装置简便的效果。
如上所述,本实施形态的焊接装置10将各电极上没有形成凸块的晶片18、半导体芯片12及电路线路板19作为材料供给,形成凸块200,并进行接合,但也可以将凸块形成机构20作为另外的独立装置,不组装在焊接装置10中。这种场合,可以通过包含晶片库13、线路板库14及凸块形成机构20的另一装置,预先射出金属纳米焊剂的微液滴,形成凸块200,凸块200形成结束的晶片18或半导体芯片12及电路线路板19作为材料,供给不具有凸块形成机构20的焊接装置10,实行一次接合,二次接合,得到制品。这样,通过另一装置形成凸块200,即使在晶片18上需要形成许多凸块200场合,具有缩短每个半导体芯片12的接合时间、能使用金属纳米焊剂有效接合半导体芯片12和电路线路板19的效果。
又,在凸块形成机构20中,也可以设有多个射出头26。这样,通过设有多个射出头,具有能提高凸块200的形成速度、能缩短每个半导体芯片12的接合时间的效果。
在本实施形态中,说明在各电极上形成凸块200进行接合,但也可以如图13所示,仅在欲接合电极之中某一方的电极形成凸块200,将该凸块200推压到另一方电极上,进行一次接合,此后,进行加压加热保持的二次接合。这样,具有凸块200形成数量只需半数、能缩短每个半导体芯片12的接合时间的效果。
又,在本实施形态中,说明在各电极上形成的凸块200都是射出金属纳米焊剂的微液滴形成,但也可以如图14所示,在半导体芯片12或电路线路板19的电极中某一方的电极上射出金属纳米焊剂的微液滴形成凸块200,在另一方的电极上形成焊锡凸块或金凸块那样的金属突起400,接合该金属突起400和凸块200。这种场合,在焊接装置10中,可以组装例如凸块焊接机那样的用于形成金凸块的金属突起形成机构,也可以将金属突起形成机构作为另一装置,将形成有金属突起400的半导体芯片12或电路线路板19作为材料供给,进行一次接合,二次接合。
参照图8说明另一实施形态。与上述说明的实施形态相同部分标以同样符号,说明省略。上述说明的实施形态是在电路线路板19上接合半导体芯片12,本实施形态是使用金属纳米焊剂进行半导体芯片12之间接合,进行三维安装。
如图8(a)所示,各半导体芯片12具有贯通电极12b。如上述图6所说明那样,在各半导体芯片12的贯通电极12b上射出金属纳米焊剂的微液滴,形成凸块200,使得一方的半导体芯片12反转,推压在吸附固定在焊接台55上的半导体芯片12的贯通电极12b上形成的凸块200上,通过超声波振动一边加振一边进行一次接合。
如图8(b)所示,将结束一次接合的半导体芯片12夹入加压加热炉的上部保持板82a,85a以及下部保持板82b,85b之间,加压同时,加热到150~250℃,保持60分钟左右,进行二次接合。通过二次接合,粘接剂的有机物质挥发,分散剂从金属纳米粒子表面脱离,金属纳米粒子之间接合,形成金属层300,接合各贯通电极12b。
如图8(c)所示,将结束二次接合的半导体芯片12再次运送到凸块形成机构20,从射出头26向经二次接合的半导体芯片12的贯通电极12b的上面射出金属纳米焊剂的微液滴100,形成凸块200。接着,如图8(d)所示,将在贯通电极12b上形成凸块200的另一半导体芯片12反转,在结束上述二次接合的半导体芯片12的上面形成的凸块200上,进行一次接合。于是,三片半导体芯片12之中,下部二片半导体芯片12之间,贯通电极12b被二次接合,上部二片半导体芯片12之间,贯通电极12b被一次接合,成为叠合状态。将该状态下的三片半导体芯片12再次运入加压加热炉进行加压、加热。二次接合形成的金属层300的熔融温度与通常金属的熔融温度相同,为1000℃左右的高温。因此,在二次接合时150~250℃的加热温度下,不会熔融,保持该状态。因此,通过加压、加热,在上部二片半导体芯片12之间,仅仅一次接合的凸块200被加压烧结,成为金属层300。这样,利用所形成的金属层300的熔融温度和二次接合的加热温度的温度差,在先通过金属纳米焊剂二次接合的半导体芯片12的贯通电极12b上叠合,使得半导体芯片12二次接合,叠层接合半导体芯片12。
按照本实施形态,除了上述说明的实施形态效果之外,还具有以下效果:不会发生以往技术中通过焊锡凸块叠层接合半导体芯片12的方法中发生的、因后接合加热使得先接合的焊锡熔融引起短路的问题,接合质量高、可靠性高的半导体芯片12的叠层接合,具有能进行三维安装的效果。
参照图9说明另一实施形态。在该实施形态中,如图9(a)所示,具有贯通电极12b的多个半导体芯片12通过一次接合叠层接合之后,将叠层接合的半导体芯片12夹入加压加热炉的上部保持板82a,85a以及下部保持板82b,85b之间,加压同时,加热到150~250℃,将该状态保持60分钟左右,对多段凸块200一下子进行二次接合。通过二次接合,粘接剂的有机物质挥发,分散剂从金属纳米粒子表面脱离,金属纳米粒子之间接合,形成金属层300,各贯通电极12b同时接合、导通。
在本实施形态中,除了上述说明的实施形态效果之外,还具有以下效果:对多段半导体芯片12一下子进行二次接合,与一段段二次接合方法相比,能减少二次接合次数,因此,能进一步缩短平均每片半导体芯片12的接合时间,能有效地进行半导体芯片12的三维安装。
参照图10及图11说明又一实施形态。与上述说明的实施形态相同部分标以同样符号,说明省略。通过二次接合时的加压形成金属层300时,根据加压、加热条件,有时如图10(a)所示,形成各电极12a,19a之间的中央部303的截面大的桶型形状的金属层300。另一方面,半导体装置动作时发热,温度上升。半导体芯片12用硅形成,电路线路板19用玻璃环氧等树脂材料形成,因此,因上述温度上升伸长程度不同,因该伸长差,在接合各电极12a,19a的金属层300产生热应力。当金属层300形成上述那样的桶型场合,在金属层300的与截面积最小的电极19a的接合面301以及与电极12a的接合面302产生最大应力。在该接合面301,302产生的热应力作用在接合面301,302的剪切方向,因此,在金属层300与电极12a,19a的接合面301,302产生裂纹等损伤,或产生导通不良等问题。
另一方面,如图10(b)所示,金属层300的形状在中央具有缩颈304场合,因伸长差产生的热应力施加到中央的缩颈304上,该缩颈304横向变形,能吸收热应力。因此,较好的是,接合各电极12a,19a的金属层300在接合方向中央形成具有缩颈304的形状。但是,二次接合的加压力控制为一定,有时难以可靠地形成缩颈304。
于是,如图10(c)所示,在加压过程途中,使得加压力为负侧,对金属层300施加拉伸力,在金属层300的中央形成缩颈304。更具体地说,如图10(c)所示,通过加压、加热开始金属纳米粒子烧结后,二次接合的所定保持时间结束前的一定时间t1中,减小加压力,使得加压力为负后,结束加压、加热的二次接合。
参照图11及图5说明本实施形态的焊接方法。如图11的步骤S301及图5所示,加压控制部503驱动上述驱动器83,86,使得上部保持板82a,85a前进,使得半导体芯片12压接在电路线路板19上,沿接合方向对各电极12a,19a的凸块200加压。如图11的步骤S302所示,通过没有图示的检测器测定加压力,或由与各电路线路板19接合的半导体芯片12的个数、形状决定的加压载荷等,加压控制部503取得上述测定结果,判断凸块200的加压力是否成为所定的加压力,在成为所定加压力前使得上部保持板82a,85a前进。该所定加压力设为通常使得金属凸块之间压接场合的1/20左右的低的加压力。又,加压控制部503控制加热器89,使得加压加热炉81,84的内部温度成为对于二次接合必要的150~250℃。接着,如图11的步骤S303所示,若加压力成为所定压力,则加压控制部503停止上部保持板82a,85a前进。接着,如图11的步骤S304所示,通过没有图示的检测器测定加压力,或由与各电路线路板19接合的半导体芯片12的个数、形状决定的加压载荷等,加压控制部503取得上述测定结果,判断凸块200的加压力是否成为所定的加压力,没有成为所定加压力场合,在成为所定加压力前,使得上部保持板82a,85a前进,将加压力保持在所定加压力。
如图11的步骤S305所示,若经过所定时间,例如图10(c)所示t1那样,比通常的二次接合保持时间稍稍短的时间,则加压控制部503开始拉伸烧结的金属层300的动作。
如图11的步骤S306及图5所示,加压控制部503使得上部保持板82a,85a及下部保持板82b,85b的各真空吸附孔91a,91b为真空。然后,如图11的步骤S307所示,加压控制部503驱动上述驱动器83,86,使得上部保持板82a,85a朝上方后退,使半导体芯片12脱离电路线路板19。于是,通过真空吸附上部保持板82a,85a吸附的半导体芯片12以及下部保持板82b,85b吸附的电路线路板19沿上下方向被拉伸,拉伸力施加在图10所示的金属层300上。如图11的步骤S308所示,通过没有图示的检测器测定加压力,或由与各电路线路板19接合的半导体芯片12的个数、形状决定的拉伸载荷等,加压控制部503取得上述测定结果,判断施加到烧结的金属层300的拉伸力是否成为所定的拉伸力,在成为所定拉伸力前使得上部保持板82a,85a朝上方后退。接着,如图11的步骤S309所示,若成为所定拉伸力,则加压控制部503停止上部保持板82a,85a朝上方的后退,如图11的步骤S310所示,加压控制部503在所定时间期间使得金属层300保持拉伸状态。
如图11的步骤S311及图5所示,加压控制部503开放上部保持板82a,85a及下部保持板82b,85b的各真空吸附孔91a,91b的真空。由此,施加在金属层300的拉伸力释放。接着,如图11的步骤S312所示,加压控制部503使得上部保持板82a,85a朝上方后退到所定位置,如图11的步骤S313所示,使得电路线路板19和半导体芯片12分离。
本实施形态除了上述说明的实施形态效果之外,还具有以下效果:在加压保持时,使得加压压力为负,对金属层施加拉伸力,能在金属层300的接合方向的中央形成缩颈304。并且,通过该缩颈304,能有效地吸收因半导体芯片12与电路线路板19的伸长差引起的热应力,具有能减少发生导通不良等的效果。
在本实施形态中,说明在金属层300的中央部形成缩颈304,以减少热应力,但只要能减少热应力,金属层300的形状并不局限于缩颈形状,例如,也可以形成高度高的圆筒形等其他形状。在将金属层300形成其他形状的场合,可以适合各形状使得加压力根据时间变化。
参照图12说明又一实施形态。与上述说明的实施形态相同部分标以同样符号,说明省略。本实施形态涉及各电极上形成的凸块前端的形状,更具体地说,将互相接合的一方的凸块的前端形成为凹形状,将另一方凸块前端形成为与该凹形状嵌合的凸形状。
在上述实施形态中,说明各电极上形成的凸块形状为前端变细的锥状,但凸块前端形状并不局限于锥状。如图12(a)所示,在半导体芯片12的电极12a上形成前端成为凹形状的凸块202,而在电路线路板19的电极19a上形成凸块200,该凸块200前端为凸形状,与形成在半导体芯片12上的凹形状的凸块202嵌合。若将这样互相接合的凸块设为凹凸组合进行嵌合,则如图12(b)所示,在将半导体芯片12的凸块202与电路线路板19的凸块200一次接合时,各凸块200,202的侧面等形成的嵌合面203也接触,因此,各凸块200,202互相接触的概率高。因此,具有一次接合时的粘接剂的接合面积增加、能提高一次接合的接合强度、同时能提高一次接合的可靠性的效果。
Claims (18)
1.一种焊接装置,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接装置包括:
凸块形成机构,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
2.一种焊接装置,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接装置包括:
凸块形成机构,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在各电极上形成凸块,使得所述凸块互相压接,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热各凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
3.一种焊接装置,三维安装半导体芯片,其特征在于,该焊接装置包括:
凸块形成机构,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在半导体芯片的电极上形成凸块,将在一半导体芯片的电极上形成的凸块推压到另一半导体芯片的电极上形成的凸块上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,将凸块加热到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
4.根据权利要求1或2或3所述的焊接装置,其特征在于:
加压器包含对向配置、保持半导体芯片或线路板的保持板,驱动至少一方的保持板朝着接合方向进退的保持板驱动部,以及控制保持板驱动部的进退动作的加压控制部;
所述加压控制部设有加压力变更手段,根据时间通过保持板驱动部驱动保持板进退,使得施加到凸块上的加压力变化。
5.根据权利要求4所述的焊接装置,其特征在于:
加压力变更手段包含缩颈形成手段,在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
6.根据权利要求4所述的焊接装置,其特征在于:
二次接合机构是在内部包含将一次接合的凸块朝接合方向加压的加压器的加热炉。
7.根据权利要求4所述的焊接装置,其特征在于:
设有多个二次接合机构。
8.一种焊接装置,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接装置包括:
凸块形成机构,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
金属突起形成机构,将金属突起形成在电极上;
一次接合机构,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,将在某一方的电极上形成的凸块推压到在另一方的电极上形成的金属突起上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合机构,包含将一次接合的凸块朝接合方向加压的加压器,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
9.根据权利要求8所述的焊接装置,其特征在于:
加压器包含对向配置、保持半导体芯片或线路板的保持板,驱动至少一方的保持板朝着接合方向进退的保持板驱动部,以及控制保持板驱动部的进退动作的加压控制部;
所述加压控制部设有加压力变更手段,根据时间通过保持板驱动部驱动保持板进退,使得施加到凸块上的加压力变化。
10.根据权利要求9所述的焊接装置,其特征在于:
加压力变更手段包含缩颈形成手段,在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
11.根据权利要求9所述的焊接装置,其特征在于:
二次接合机构是在内部包含将一次接合的凸块朝接合方向加压的加压器的加热炉。
12.根据权利要求9所述的焊接装置,其特征在于:
设有多个二次接合机构。
13.一种焊接方法,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接方法包括:
凸块形成工序,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
14.一种焊接方法,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接方法包括:
凸块形成工序,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在各电极上形成凸块,使得所述凸块互相压接,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热各凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
15.一种焊接方法,三维安装半导体芯片,其特征在于,该焊接方法包括:
凸块形成工序,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在半导体芯片的电极上形成凸块,将在一半导体芯片的电极上形成的凸块推压到另一半导体芯片的电极上形成的凸块上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,将凸块加热到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
16.根据权利要求13或14或15所述的焊接方法,其特征在于:
二次接合工序在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
17.一种焊接方法,接合半导体芯片的电极及线路板的电极,其特征在于,该焊接方法包括:
凸块形成工序,将金属纳米焊剂的微液滴射出到电极上,在电极上形成凸块;
金属突起形成工序,将金属突起形成在电极上;
一次接合工序,金属纳米粒子表面涂布分散剂,所述金属纳米粒子包含在糊状的粘接剂中,形成金属纳米焊剂,射出该金属纳米焊剂的微液滴,在某一方的电极上形成凸块,将所述凸块推压到另一方电极上形成的金属突起上,加热各凸块,加热到比室温高、比金属纳米焊剂的粘接剂除去温度低的所定温度,以非导通状态一次接合各电极;
二次接合工序,将一次接合的凸块朝接合方向加压,使得加压力根据时间变化,同时,加热凸块到比金属纳米焊剂的粘接剂除去温度及金属纳米焊剂的分散剂除去温度高的温度,除去粘接剂及分散剂,使得凸块的金属纳米粒子加压烧结,各电极导通,进行二次接合。
18.根据权利要求17所述的焊接方法,其特征在于:
二次接合工序在所定时间经过后,将施加到凸块的加压力设为负值,沿接合方向拉伸加压烧结的凸块,在凸块的沿接合方向的中央形成缩颈。
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Also Published As
Publication number | Publication date |
---|---|
KR100979472B1 (ko) | 2010-09-02 |
US7743964B2 (en) | 2010-06-29 |
KR20090106546A (ko) | 2009-10-09 |
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TW201007860A (en) | 2010-02-16 |
CN101681849A (zh) | 2010-03-24 |
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CN101681850A (zh) | 2010-03-24 |
TWI377633B (zh) | 2012-11-21 |
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US20100089980A1 (en) | 2010-04-15 |
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US20100093131A1 (en) | 2010-04-15 |
US7726546B2 (en) | 2010-06-01 |
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