CN101673739B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN101673739B
CN101673739B CN2009102057291A CN200910205729A CN101673739B CN 101673739 B CN101673739 B CN 101673739B CN 2009102057291 A CN2009102057291 A CN 2009102057291A CN 200910205729 A CN200910205729 A CN 200910205729A CN 101673739 B CN101673739 B CN 101673739B
Authority
CN
China
Prior art keywords
layer
insulation film
type
body layer
element separating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009102057291A
Other languages
English (en)
Other versions
CN101673739A (zh
Inventor
米田阳树
笹田一弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101673739A publication Critical patent/CN101673739A/zh
Application granted granted Critical
Publication of CN101673739B publication Critical patent/CN101673739B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供一种半导体装置及其制造方法。从漏极层的下方经由元件分离绝缘膜的下方，形成扩展到源极层的下部的N型主体层的下方的N型外延层中的P型漂移层。该P型漂移层在漏极层的正下方的深度比在元件分离绝缘膜的下方的深度浅，此外，从元件分离绝缘膜的下方起越接近N型主体层越变浅，与N型主体层的底部连接。这样，由于P型漂移层在所述宽范围内扩散，因此形成从N型主体层到漏极层的宽的电流通路，可以提高电流驱动能力，还可以提高漏极耐压。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是，涉及高耐压晶体管的半导体装置及其制造方法。
背景技术
以往，已知一种采用了LOCOS(硅的局部氧化)偏置法的高耐压MOS晶体管。下面，参照图9A～9E说明这种高耐压MOS晶体管的制造方法。
如图9A所示，在N型硅基板21或形成N阱的硅基板21的表面上热氧化形成焊盘氧化膜22，利用减压CVD法在焊盘氧化膜22上形成氮化硅膜23。
然后，如图9B所示，利用蚀刻，经由规定的光刻工序等除去应该在元件分离区域的部分氮化硅膜23以及形成偏置漏极区域的P型漂移层的部分氮化硅膜23。然后，用光刻抗蚀膜(未图示)覆盖应该形成偏置漏极区域的部分以外的部分，将该光刻抗蚀膜和氮化硅膜23作为掩膜，离子注入P型杂质，形成构成偏置漏极区域的比较低浓度的P型层24a。
然后，如图9C所示，将氮化硅膜23作为掩膜，进行热氧化以及热扩散，在硅基板21的表面上形成膜厚为500nm左右的元件分离用的氧化膜25，此外，还形成作为偏置漏极区域的P型漂移层24b。之后，蚀刻除去氮化硅膜23等。
接下来，如图9D所示，将氧化膜25作为掩膜，向硅基板21中离子注入用于阈值电压调整的N型杂质26，之后，在硅基板21的表面上形成栅极氧化膜27。接着，用CVD法堆叠多晶硅膜，经由规定的光刻工序等，形成由多晶硅膜构成的栅电极28。
接着，如图9E所示，将栅电极28、氧化膜25作为掩膜，通过杂质的离子注入，形成高浓度的P型源极层29和P型漏极层30。由此完成了P型漂移层24b和P型源极层29之间构成沟道区31的高耐压MOS晶体管32。
在现有例的高耐压MOS晶体管32中，为了使与沟道区31相接的P型漂移层24b侧端部中的电场强度缓和并提高漏极耐压的高可靠性，必须降低作为偏置漏极区域的P型漂移层24b的杂质浓度并扩展耗尽层。
另一方面，高耐压MOS晶体管的电流驱动能力必须很高，作为偏置漏极区域的P型漂移层24b的杂质浓度必须高，电流通路的电阻必须低。即，现有例的高耐压MOS晶体管32中，高耐压特性和高电流驱动能力性存在平衡关系，要使两特性中任何一个最佳都是很困难的。
发明内容
因此，本发明的目的是对于高性能的高耐压晶体管的市场需求，提供一种漏极耐压高、电流驱动能力高的高耐压晶体管。
本发明的半导体装置包括：第一导电型的半导体层；在所述半导体层的表面上形成的元件分离绝缘膜；与所述元件分离绝缘膜的一端相邻并在所述半导体层的表面上形成的第一导电型主体层；与所述元件分离绝缘膜的另一端相邻并在所述半导体层的表面上形成的第二导电型漏极层；在所述主体层的表面上形成的第二导电型源极层；在所述主体层上形成的栅极绝缘膜；从所述元件分离绝缘膜上经由所述栅极绝缘膜延伸到所述主体层上的栅电极；和从所述漏极层的下方扩展到所述源极层下部的所述主体层下方的所述半导体层中的漂移层。所述漂移层在所述漏极层的正下方的深度比在所述元件分离绝缘膜的下方的深度浅，并且从所述元件分离绝缘膜的下方起越接近所述主体层越变浅，并与所述主体层的底部连接。
此外，本发明的半导体装置的制造方法包括：在第一导电型半导体层的表面选择性地导入第二导电型杂质的工序；通过选择氧化导入了所述杂质的区域，形成元件分离绝缘膜，并且使所述杂质扩散，形成第二导电型漂移层的工序；以所述元件分离绝缘膜为基准，形成与所述元件分离绝缘膜的一端相邻的第一导电型主体层的工序；在所述主体层上形成栅极绝缘膜的工序；形成栅电极的工序，该栅电极从所述元件分离绝缘膜上经由所述栅极绝缘膜延伸到所述主体层上；和在所述主体层的表面上形成第二导电型源极层，并且形成与所述元件分离绝缘膜的另一端相邻的第二导电型漏极层的工序。所述漂移层按照如下方式扩散：从所述漏极层的下方向所述源极层下部的所述主体层的下方的所述半导体层中扩展，并且在所述漏极层的正下方的深度比在所述元件分离绝缘膜的下方的深度浅，另外，从所述元件分离绝缘膜的下方起越接近所述主体层越变浅。
附图说明
图1是表示根据本发明实施方式的半导体装置的平面图。
图2是沿着图1的半导体装置的A-A线截取的剖面图。
图3是表示根据本发明的半导体装置及其制造方法的剖面图。
图4是表示根据本发明的半导体装置及其制造方法的剖面图。
图5是表示根据本发明的半导体装置及其制造方法的剖面图。
图6是表示根据本发明的半导体装置及其制造方法的剖面图。
图7是表示根据本发明的半导体装置及其制造方法的剖面图。
图8是表示根据本发明的半导体装置及其制造方法的剖面图。
图9A～9E是表示现有的半导体装置及其制造方法的剖面图。
具体实施方式
下面参照附图说明本发明的实施方式。尽管为了扩大沟道宽度，这种高耐压MOS晶体管反复形成栅电极13、源极层17、和漏极层18，但是图1中只表示了其一部分。下面，首先说明高耐压MOS晶体管的结构的主要部件，然后详细说明其制造方法。
如图2所示，在P性半导体基板1的表面上形成N+型掩埋层2，在N+型掩埋层2上形成N型外延层3。在N型外延层3的表面上形成通过LOCOS形成的元件分离绝缘膜9，并与该元件分离绝缘膜9的一端相邻，在N型外延层3的表面上形成N型主体层11。此外，与元件分离绝缘膜9的另一端相邻，在N型外延层3的表面上形成P+漏极层18。在N型主体层11的表面上形成P+型源极层17。
在N型主体层11上，形成栅极绝缘膜12，并形成从元件分离绝缘膜9上经由栅极绝缘膜12延伸到N型主体层11上的栅电极13。然后，形成P型漂移层10，该P型漂移层10从漏极层18的下方，经由元件分离绝缘膜9的下方，扩展到源极层17的下部的N型主体层11的下方的N型外延层3中。该P型漂移层10在漏极层18的正下方的深度比在元件分离绝缘膜9的下方的深度浅。
这样，由于P型漂移层10在所述宽范围内扩散，从N型主体层11直到漏极层18形成宽的电流通路，因此可以提高电流驱动能力。在漏极层18的正下方的深度比在元件分离绝缘膜9的下方的深度浅也带来了电流驱动能力的提高。
此外，P型漂移层10在所述宽范围内扩散，并且在漏极层18的正下方的深度比在元件分离绝缘膜9下方的深度浅，因此由P型漂移层10和N型外延层3形成的PN结的结面积变大。其结果，漏极层18的耗尽层很宽地扩展，使漏极层18的电场缓和，可以提高漏极耐压。
此外，在N型主体层11的表面上，形成N型沟道层14，在该N型沟道层14上经栅极绝缘膜12配置栅电极13。即，栅电极13下面的N型主体层11和N型沟道层14构成高耐压晶体管的沟道区域。
N型沟道层14的杂质浓度优选比N型主体层11的杂质浓度高。由此，高耐压晶体管的阈值Vt可以由N型沟道层14的杂质浓度决定。
另一方面，P型漂移层10的端部从元件分离绝缘膜9的下方起越接近N型主体层11越变浅，并延伸到N型主体层11的底部，通过源极层17的下部的P型漂移层10和N型外延层3形成的PN结的结面积增大，可以提高漏极耐压。因此，这部分的漏极耐压由P型漂移层10和N型主体层11的接触部决定。此外，适当地设定N型主体层11的杂质浓度，可以通过补偿P型漏极层的杂质浓度来提高漏极耐压。这种情况下，由于高耐压晶体管的阈值Vt由N型沟道层14的杂质浓度决定，因此即使将N型主体层11的杂质浓度设定为低，也不会影响阈值Vt。即，根据所述结构，可以独立地控制漏极耐压和高耐压晶体管的阈值Vt。
此外，在本实施方式中，反复形成栅电极13、源极层17、漏极层18以便构成图案，如果以源极层17或漏极层18为中心看，形成左右对称的结构。因此，在漏极层18的下方，如果互相相邻的P型漂移层10、10重叠，则该重叠部分的杂质浓度变高。这种结构也有利于提高电流驱动能力。
另一方面，在源极层17的下方，通过使互相相邻的P型漂移层10、10不相接的程度延伸到N型主体层11的底部，增大PN结的结面积，可以提高漏极耐压。
下面，参照图3到图8说明所述高耐压晶体管的制造方法。首先，如图3所示，准备P型半导体基板1(例如P型硅单晶基板)，经过规定的工序在其表面上形成N+型掩埋层2，通过外延法进一步在其表面上形成规定厚度的N型外延层3。
之后，在N型外延层3的表面上形成薄焊盘用热氧化膜4，通过减压CVD法进一步在其表面上能够形成氮化硅膜5。然后，通过规定的光刻工序，在形成有下述的P型漂移层10和元件分离绝缘膜9的区域上形成具有开口部的光刻抗蚀膜(未图示)。然后，利用干蚀刻等蚀刻除去在P型漂移层等的形成预定区域上露出的氮化硅膜5等，之后，通过规定的药液或老化除去光刻抗蚀膜。
接着，使用离子注入法，通过所述蚀刻向已开口的N型外延层3内注入P型杂质，形成P型层8。这种情况下，离子注入之后，在高温下进行推阱(drive-in)而构成的P型层8在N型外延层3的表面上优选形成得比较浅，因此优选形成适当地控制了P型杂质浓度的P型层8。通过该工序，在P型层8之间形成后来形成源极层等的源极单元区域6和后来形成漏极层的漏极单元区域7。
接着，如图4所示，将氮化硅膜5作为耐氧化掩膜，通过在1100℃以上的高温下进行热氧化，形成由热氧化膜构成的元件分离绝缘膜9，并且对P型层8进行推阱，形成作为P型深扩散层的P型漂移层10。P型漂移层10通过如图中所示先较深地扩散到源极单元区域6的内部，再在漏极单元区域7内从漏极单元区域7的两侧扩散2个P型漂移层10，通过互相重叠，可以提高其重叠部分的P型杂质的浓度、减小该部分的P型漂移层10的电阻。
接着，如图5所示，将元件分离绝缘膜9图案作为对准标记的基准，通过规定的光刻工序形成在源极单元区域6中具有开口部的光刻抗蚀膜(未图示)，用该光刻抗蚀膜作为掩膜，通过从该光刻抗蚀膜的开口部向半导体层内离子注入N型杂质，形成N型主体层11。N型主体层11是以元件分离绝缘膜9为基准形成的，因此与元件分离绝缘膜9同时形成的P型漂移层10的位置关系稳定，其再现性高。因此，由N型主体层11的端部的P型漂移层10决定的耐压特性的偏差减少了，可以实现高的再现性。
然后，如图6所示，在包含N型主体层11上的半导体层的表面形成栅极绝缘膜12。之后，在栅极绝缘膜12上用CVD等形成多晶硅膜，通过规定的光刻工序等形成栅电极13。栅电极13在N型主体层11上具有开口部，并从栅极绝缘膜12上延伸到元件分离绝缘膜9上。由于这种情况下的对准标记的基准也成为元件分离绝缘膜9的图案，因此栅电极13和N型主体层11的位置关系没有大的偏离，此外，假设即使多少有点偏离，也不会影响后述的耐压和阈值电压。
接下来，如图7所示，通过规定的光刻工序形成源极单元区域6中具有开口部的光刻抗蚀膜15。之后，相对于露出的N型主体层11，以相对于垂直方向呈30度左右的角度，将栅电极13作为掩膜，向该N型主体层11的表面离子注入N型杂质。这种情况下，多次旋转P型半导体基板1，并进行自对准，从而进行离子注入，在N型主体层11的内侧，形成比N主体层11浓度高的N型沟道层14。通过离子注入后的低温退火，使N型沟道层14进入左右两侧的栅电极13下面的与栅极氧化膜12的界面中。与N型沟道层14的端部的栅极绝缘膜12接触的表面部的位置是旋转P型半导体基板1的相同条件下进行离子注入形成的，因此能形成如图7所示的左右对称的所希望的N型沟道层14。
因此，即使在N型沟道层14的外侧的N型主体层11的表面浓度相当低的情况下，也不需要担心左右哪个的沟道长度变短，在左右任何一个的沟道都不会发生短沟道效应。另外，在本发明的实施方式中，P型半导体基板1以90度连续旋转4次，形成N型沟道层14。此外，即使N型沟道层14的端部、N型主体层11的端部分别与栅极绝缘膜12相接触的部分之间的距离左右不同的情况下，耐压也由与N型主体层11端部相接的P型漂移层10决定，因此不存在阈值Vt由比N型主体层11的杂质浓度高的N型沟道层14决定的大问题。
接着，如图8所示，用CVD法形成覆盖半导体层的整个表面的氧化膜(未图示)，通过规定的RIE(Reactive Ion Etching)进行蚀刻，在栅电极13的侧壁上形成由氧化膜构成的侧壁16。然后，通过规定的光刻工序形成源极单元区域6和漏极层18等中具有开口部的光刻抗蚀膜(未图示)。然后，用栅电极13、侧壁16做掩膜，离子注入高剂量的P型杂质形成P+型源极层17，此外，同时用所述的光刻抗蚀膜(未图示)作为掩膜，离子注入高剂量的P型杂质形成P+型漏极层18。
这种情况下，如果将元件分离绝缘膜9作为掩膜，通过自对准形成漏极层18，可以进一步实现微小的图案。而且，源极层17是用侧壁16做掩膜以自对准方式形成的，因此在与N型沟道层14的位置关系大致固定的N型沟道层14表面上形成的沟道长度也大致固定。
最后，如图2所示，形成覆盖半导体整个表面的层间绝缘膜19，然后，经规定的光刻工序等相对于漏极层18、源极层17、以及未图示的栅电极13形成接触孔20，通过形成由未图示的铝构成的布线电极等，完成了所希望的半导体装置。
从图2中可知，P型漂移层10以元件分离绝缘膜9的形成位置为中心广泛地扩散，一直扩散到N型主体层11下部，由于扩散到元件分离绝缘膜9下部的最深处，因此从N型主体层11直到漏极层18形成宽的电流通路。此外，本发明的实施方式中，漏极层18配置在比源极层17更靠近元件分离绝缘膜9的位置上，因此在漏极层18的下部，P型漂移层10、10从该漏极层的两侧扩散，由于该部分的杂质浓度高，因此该部分的电阻降低。这样，由于作为电流集中的终端部的漏极层18下部的杂质浓度变为高浓度，因此终端部效果也存在，通过降低从源极层17直到漏极层18的电流通路的电阻，从而提高了电流驱动能力。
此外，即使与漏极耐压相关，由于不管哪个都是以元件分离绝缘膜9图案为基准形成的，从而使N型主体层11和P型漂移层10的位置关系稳定，因此通过适当地设定各自的浓度，可以得到所希望的耐压。接着，与在漏极层正下方的深度相比，如上所述的P型漂移层10在元件分离绝缘膜9的下方更深地扩散，从而形成宽的电流通路，但与此同时，结面积变大且很深地扩散的P型漂移层10的曲率半径变大。此外，在源极层17的下方，P型漂移层10在与相邻的P型漂移层10不相接的范围内延伸到N型主体层11的底部。因此，在由P型漂移层10和N型外延层3以及P型漂移层10和N型主体层11形成的PN结内，耗尽层宽度均匀地扩大，有利于提高耐压。此外，用栅电极13作为掩膜以自对准方式形成决定阈值的N型沟道层14，源极层17也是用在栅电极13的侧端部中形成的侧壁16作为掩膜以自对准方式形成的，因此浓度高的N型沟道层14部分的沟道区域的沟道长度固定，晶体管特性也稳定。
另外，尽管本实施方式是包含了也可以形成双极晶体管等的N+型掩埋层2等的半导体基板的结构，但是除了在只由MOS型晶体管构成的没有N+型掩埋层2等的半导体基板上构成的情况之外，即使与本实施方式相反极性的结构，即，将P型变为N型，将N型变为P型的情况，或者单体的MOS型晶体管的情况，只要发明的思想相同，就包含在本发明的范围内。
发明效果
根据本发明，可以提高高耐压晶体管的漏极耐压，并且能提高电流驱动能力。

Claims (9)

1.一种半导体装置，其特征在于，
包括：第一导电型的半导体层；
元件分离绝缘膜，形成在所述半导体层的表面上；
第一导电型主体层，与所述元件分离绝缘膜的一端相邻，并形成在所述半导体层的表面上；
第二导电型漏极层，与所述元件分离绝缘膜的另一端相邻，并形成在所述半导体层的表面上；
第二导电型源极层，形成在所述主体层的表面上；
栅极绝缘膜，形成在所述主体层上；
栅电极，从所述元件分离绝缘膜上经由所述栅极绝缘膜延伸到所述主体层上；和
漂移层，从所述漏极层的下方扩展到所述源极层下部的所述主体层下方的所述半导体层中，
所述漂移层在所述漏极层的正下方的深度比在所述元件分离绝缘膜的下方的深度浅，并且所述漂移层从所述元件分离绝缘膜的下方起越接近所述主体层越变浅，并与所述主体层的底部连接。
2.根据权利要求1所述的半导体装置，其特征在于，
所述主体层的下方的所述漂移层与相邻的其他漂移层不重叠。
3.根据权利要求1所述的半导体装置，其特征在于，
所述漏极层的下方的所述漂移层与相邻的其他漂移层重叠。
4.根据权利要求1所述的半导体装置，其特征在于，
所述主体层包括形成在该主体层的表面上的第一导电型沟道层，
所述沟道层的杂质浓度比所述主体层的杂质浓度高。
5.一种半导体装置的制造方法，其特征在于，
包括：在第一导电型半导体层的表面选择性地导入第二导电型杂质的工序；
通过选择氧化导入了所述杂质的区域，形成元件分离绝缘膜，并且使所述杂质扩散，形成第二导电型漂移层的工序；
以所述元件分离绝缘膜为基准，形成与所述元件分离绝缘膜的一端相邻的第一导电型主体层的工序；
在所述主体层上形成栅极绝缘膜的工序；
形成栅电极的工序，该栅电极从所述元件分离绝缘膜上经由所述栅极绝缘膜延伸到所述主体层上；和
在所述主体层的表面上形成第二导电型源极层，并且形成与所述元件分离绝缘膜的另一端相邻的第二导电型漏极层的工序，
所述漂移层按照如下方式扩散：从所述漏极层的下方向所述源极层下部的所述主体层下方的所述半导体层中扩展，并且所述漂移层在所述漏极层的正下方的深度比在所述元件分离绝缘膜的下方的深度浅，另外，所述漂移层从所述元件分离绝缘膜的下方起越接近所述主体层越变浅。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述漂移层形成为：从所述元件分离绝缘膜的下方起越接近所述主体层越变浅，并与所述主体层的底部连接。
7.根据权利要求6所述的半导体装置的制造方法，其特征在于，
所述主体层下方的所述漂移层按照与相邻的其他漂移层不重叠的状态形成。
8.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述漏极层下方的所述漂移层与相邻的其他漂移层重叠而形成。
9.根据权利要求5所述的半导体装置的制造方法，其特征在于，
还包括：在所述栅电极的下方的所述主体层的表面上，通过注入偏斜离子，形成第一导电型沟道层的工序。
CN2009102057291A 2008-06-27 2009-06-26 半导体装置及其制造方法 Expired - Fee Related CN101673739B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008168185 2008-06-27
JP2008-168185 2008-06-27
JP2008168185A JP2010010408A (ja) 2008-06-27 2008-06-27 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN101673739A CN101673739A (zh) 2010-03-17
CN101673739B true CN101673739B (zh) 2011-02-02

Family

ID=41446351

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009102057291A Expired - Fee Related CN101673739B (zh) 2008-06-27 2009-06-26 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US8410557B2 (zh)
JP (1) JP2010010408A (zh)
CN (1) CN101673739B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2405466B1 (en) * 2010-07-05 2014-04-23 ams AG Symmetric LDMOS transistor and method of production
US8669639B2 (en) * 2012-06-11 2014-03-11 Macronix International Co., Ltd. Semiconductor element, manufacturing method thereof and operating method thereof
US9490322B2 (en) * 2013-01-23 2016-11-08 Freescale Semiconductor, Inc. Semiconductor device with enhanced 3D resurf
JP6284336B2 (ja) * 2013-10-17 2018-02-28 ルネサスエレクトロニクス株式会社 半導体装置
CN109980009B (zh) 2017-12-28 2020-11-03 无锡华润上华科技有限公司 一种半导体器件的制造方法和集成半导体器件
CN109980010B (zh) * 2017-12-28 2020-10-13 无锡华润上华科技有限公司 一种半导体器件的制造方法和集成半导体器件
CN108682691A (zh) * 2018-05-25 2018-10-19 矽力杰半导体技术(杭州)有限公司 横向扩散金属氧化物半导体器件的制造方法及半导体器件

Family Cites Families (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191401A (en) * 1989-03-10 1993-03-02 Kabushiki Kaisha Toshiba MOS transistor with high breakdown voltage
US5306652A (en) * 1991-12-30 1994-04-26 Texas Instruments Incorporated Lateral double diffused insulated gate field effect transistor fabrication process
JP2997377B2 (ja) * 1993-01-06 2000-01-11 シャープ株式会社 半導体装置及びその製造方法
US5874768A (en) * 1994-06-15 1999-02-23 Nippondenso Co., Ltd. Semiconductor device having a high breakdown voltage
JPH08139319A (ja) * 1994-11-11 1996-05-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3547884B2 (ja) * 1995-12-30 2004-07-28 三菱電機株式会社 半導体装置及びその製造方法
JPH09223793A (ja) 1996-02-16 1997-08-26 Sony Corp 半導体装置及びその製造方法
US5854113A (en) * 1996-11-01 1998-12-29 Electronics And Telecommunications Research Institute Method for fabricating power transistor using silicon-on-insulator (SOI) wafer
US6180959B1 (en) * 1997-04-17 2001-01-30 Hitachi, Ltd. Static induction semiconductor device, and driving method and drive circuit thereof
US6160290A (en) * 1997-11-25 2000-12-12 Texas Instruments Incorporated Reduced surface field device having an extended field plate and method for forming the same
KR100253372B1 (ko) * 1997-12-08 2000-04-15 김영환 반도체 소자 및 그 제조방법
US6897525B1 (en) * 1998-11-26 2005-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
JP3443355B2 (ja) * 1999-03-12 2003-09-02 三洋電機株式会社 半導体装置の製造方法
US6365932B1 (en) * 1999-08-20 2002-04-02 Denso Corporation Power MOS transistor
JP4357127B2 (ja) * 2000-03-03 2009-11-04 株式会社東芝 半導体装置
JP2002026328A (ja) * 2000-07-04 2002-01-25 Toshiba Corp 横型半導体装置
JP3831598B2 (ja) * 2000-10-19 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
US6835985B2 (en) * 2000-12-07 2004-12-28 Chartered Semiconductor Manufacturing Ltd. ESD protection structure
JP3831602B2 (ja) * 2000-12-07 2006-10-11 三洋電機株式会社 半導体装置の製造方法
GB2374456A (en) * 2000-12-09 2002-10-16 Esm Ltd High-voltage metal oxide semiconductor device and method of forming the device
US6825543B2 (en) * 2000-12-28 2004-11-30 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and liquid jet apparatus
JP3831615B2 (ja) * 2001-01-16 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
US6617652B2 (en) * 2001-03-22 2003-09-09 Matsushita Electric Industrial Co., Ltd. High breakdown voltage semiconductor device
US20030001216A1 (en) * 2001-06-27 2003-01-02 Motorola, Inc. Semiconductor component and method of manufacturing
US6822292B2 (en) * 2001-11-21 2004-11-23 Intersil Americas Inc. Lateral MOSFET structure of an integrated circuit having separated device regions
JP4677166B2 (ja) * 2002-06-27 2011-04-27 三洋電機株式会社 半導体装置及びその製造方法
KR100442881B1 (ko) * 2002-07-24 2004-08-02 삼성전자주식회사 고전압 종형 디모스 트랜지스터 및 그 제조방법
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7719054B2 (en) * 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US7019377B2 (en) * 2002-12-17 2006-03-28 Micrel, Inc. Integrated circuit including high voltage devices and low voltage devices
US6876035B2 (en) * 2003-05-06 2005-04-05 International Business Machines Corporation High voltage N-LDMOS transistors having shallow trench isolation region
US6924531B2 (en) * 2003-10-01 2005-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. LDMOS device with isolation guard rings
JP4479276B2 (ja) 2004-02-25 2010-06-09 株式会社デンソー 横型ｍｏｓトランジスタの製造方法
US7238986B2 (en) * 2004-05-03 2007-07-03 Texas Instruments Incorporated Robust DEMOS transistors and method for making the same
JP4308096B2 (ja) * 2004-07-01 2009-08-05 パナソニック株式会社 半導体装置及びその製造方法
US7180152B2 (en) * 2004-07-08 2007-02-20 International Rectifier Corporation Process for resurf diffusion for high voltage MOSFET
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
JP2006156779A (ja) * 2004-11-30 2006-06-15 Seiko Epson Corp 半導体装置及びその製造方法
JP4387291B2 (ja) * 2004-12-06 2009-12-16 パナソニック株式会社 横型半導体デバイスおよびその製造方法
US7468537B2 (en) * 2004-12-15 2008-12-23 Texas Instruments Incorporated Drain extended PMOS transistors and methods for making the same
KR100669597B1 (ko) * 2004-12-30 2007-01-15 동부일렉트로닉스 주식회사 균일한 채널 농도 분포를 갖는 수평형 디모스 트랜지스터
JP2006245548A (ja) * 2005-02-01 2006-09-14 Toshiba Corp 半導体装置
US7109562B2 (en) * 2005-02-07 2006-09-19 Leadtrend Technology Corp. High voltage laterally double-diffused metal oxide semiconductor
JP4927340B2 (ja) * 2005-02-24 2012-05-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP2006237224A (ja) * 2005-02-24 2006-09-07 Sanyo Electric Co Ltd 半導体装置
JP4921730B2 (ja) * 2005-06-20 2012-04-25 株式会社東芝 半導体装置
TWI262545B (en) * 2005-08-30 2006-09-21 Powerchip Semiconductor Corp Semiconductor device and fabricating method thereof
US7456451B2 (en) * 2005-09-13 2008-11-25 United Microelectronics Corp. Ultra high voltage MOS transistor device
JP4989085B2 (ja) * 2006-02-24 2012-08-01 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
TW200814320A (en) * 2006-09-15 2008-03-16 Sanyo Electric Co Semiconductor device and method for making same
US20080093700A1 (en) * 2006-10-20 2008-04-24 United Microelectronics Corp. Semiconductor device and method for operating the same
CN101589471B (zh) * 2007-01-04 2012-05-23 飞思卡尔半导体公司 半导体器件及形成半导体器件的方法
KR100840787B1 (ko) * 2007-02-23 2008-06-23 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US7602017B2 (en) * 2007-03-13 2009-10-13 Fairchild Semiconductor Corporation Short channel LV, MV, and HV CMOS devices
US7602037B2 (en) * 2007-03-28 2009-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage semiconductor devices and methods for fabricating the same
US7709908B2 (en) * 2007-08-10 2010-05-04 United Microelectronics Corp. High-voltage MOS transistor device
US20090090983A1 (en) * 2007-10-03 2009-04-09 Adkisson James W Dual work function high voltage devices
JP4700043B2 (ja) * 2007-11-07 2011-06-15 Ｏｋｉセミコンダクタ株式会社 半導体素子の製造方法
US7936010B2 (en) * 2007-12-27 2011-05-03 Infineon Technologies Austria Ag Power semiconductor having a lightly doped drift and buffer layer
JP2009231811A (ja) * 2008-02-27 2009-10-08 Seiko Instruments Inc 半導体装置およびその製造方法
US7910991B2 (en) * 2008-03-31 2011-03-22 Freescale Semiconductor, Inc. Dual gate lateral diffused MOS transistor
JP5437602B2 (ja) * 2008-07-29 2014-03-12 セイコーインスツル株式会社 半導体装置およびその製造方法
JP5296450B2 (ja) * 2008-08-13 2013-09-25 セイコーインスツル株式会社 半導体装置
KR101049876B1 (ko) * 2008-11-19 2011-07-19 주식회사 동부하이텍 횡형 디모스 소자 및 그의 제조 방법
KR20100079548A (ko) * 2008-12-31 2010-07-08 주식회사 동부하이텍 엘디모스 및 그 제조 방법
JP2010278312A (ja) * 2009-05-29 2010-12-09 Sanyo Electric Co Ltd 半導体装置

Also Published As

Publication number Publication date
JP2010010408A (ja) 2010-01-14
US8410557B2 (en) 2013-04-02
CN101673739A (zh) 2010-03-17
US20090321852A1 (en) 2009-12-31

Similar Documents

Publication Publication Date Title
US8247287B2 (en) Method of fabricating a deep trench insulated gate bipolar transistor
US9853146B2 (en) Lateral double diffused MOS transistors
US6825531B1 (en) Lateral DMOS transistor with a self-aligned drain region
CN101673739B (zh) 半导体装置及其制造方法
US20080070369A1 (en) MOS transistor device structure combining Si-trench and field plate structures for high voltage device
KR101228366B1 (ko) Ｌｄｍｏｓ 소자 제조 방법
US9660020B2 (en) Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
TWI421951B (zh) 以不對稱間隔物作為閘極之橫向擴散金屬氧化物半導體（ｌｄｍｏｓ）電晶體
US20100155831A1 (en) Deep trench insulated gate bipolar transistor
US11031466B2 (en) Method of forming oxygen inserted Si-layers in power semiconductor devices
US7268392B2 (en) Trench gate semiconductor device with a reduction in switching loss
KR20010102255A (ko) 자기 정렬된 실리콘 탄화물 ｌｍｏｓｆｅｔ
US8143680B2 (en) Gated diode with non-planar source region
CN102544102A (zh) 一种具有应变结构的vdmos器件及其制备方法
KR20110078621A (ko) 반도체 소자 및 그 제조 방법
KR20170114703A (ko) 게이트 전극 구조물 및 이를 포함하는 고전압 반도체 소자
US8530967B2 (en) Lateral insulated-gate bipolar transistor and manufacturing method thereof
KR100492981B1 (ko) 래터럴 이중확산 모스 트랜지스터 및 그 제조방법
US10727063B2 (en) Methods of fabricating high voltage semiconductor devices
KR102251761B1 (ko) 전력 반도체 소자
CN102420253A (zh) 一种背面嵌入应变介质区的vdmos器件及其制备方法
KR20170111102A (ko) 고전압 반도체 소자
JPH03132077A (ja) 半導体装置とその製造方法
CN111755337A (zh) 横向双扩散晶体管的制造方法
KR20110049245A (ko) 횡방향 탄화규소 전계효과 트랜지스터

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110202

Termination date: 20210626