JP4387291B2 - 横型半導体デバイスおよびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 206
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000012535 impurity Substances 0.000 claims description 74
- 238000009792 diffusion process Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 27
- 238000009826 distribution Methods 0.000 claims description 18
- 230000007423 decrease Effects 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 14
- 229910052787 antimony Inorganic materials 0.000 claims description 10
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 description 25
- 230000003071 parasitic effect Effects 0.000 description 23
- 230000000694 effects Effects 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
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- 230000035515 penetration Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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Description
一方、Pウェル領域の不純物濃度が高い場合、Vthの上昇を招き、オン抵抗の増加、ドレイン飽和電流の低下を招く。これにより、オン時の耐圧は向上するが、電流能力を低下させているので、素子面積が増加してしまう。
請求項3では、P型不純物の濃度分布の頂上は、半導体層表面から深さ0.5μm以内にあるので、不純物が硼素の場合、加速エネルギーを180KeVまで小さくできて、数百〜1MeVの高エネルギーイオン注入を用いる必要がない。従って、イオンの突き抜けを防止するためにレジストマスクを厚くする必要はない。また、比較的高いドーズ量を注入しても、ウェハの処理時間は短くなり生産性を低下させない。
第1の半導体領域15の端部とN+ドレイン領域4との間隔1μmの領域は、Pウェル領域5やP―半導体層14が存在して、逆バイアスが印加された際に端部での電界集中を緩和する効果をもたせている。
2 埋め込み絶縁層
3 N型半導体層
4 ドレイン領域
5 ウェル領域
6 ソース領域
7 コンタクト拡散領域
8 ゲート絶縁膜
9 ゲート電極
10 ソース電極
11 ドレイン電極
12 埋め込み領域
13 フィールド酸化膜
14 半導体層
15 第1の半導体領域
16 第2の半導体領域
17 埋め込み領域
18 ドリフト領域
19 ウェル領域
20 埋め込み領域
21 ソース領域
22 コンタクト拡散領域
23 ドレイン領域
24 ソース電極
25 ドレイン電極
26 マスク層
27 エピタキシャル層
Claims (11)
- 支持基板と、前記支持基板上に形成される埋め込み絶縁膜と、前記埋め込み絶縁膜上に形成されるN型の半導体層と、前記半導体層の表面から前記埋め込み絶縁膜に到達するよう形成されるP型のウェル領域と、前記ウェル領域内の表面に形成されるP型の第1の半導体領域と、前記第1の半導体領域内の表面に形成されるN型のソース領域と、前記半導体層表面に前記ウェル領域から離れて形成されたN型のドレイン領域と、前記半導体層表面の前記ソース領域端から前記ウェル領域に隣接する前記半導体層の間に形成されるゲート絶縁膜と、前記ゲート絶縁膜上に形成されるゲート電極とを備え、
前記第1の半導体領域は、前記ソース領域下方から前記ゲート電極下方の一部まで延在されて、更に、P型不純物の濃度分布は、前記半導体層表面から前記埋め込み絶縁膜に向かって増加して前記ソース領域の下方において減少する頂上を有して、前記第1の半導体領域直下から前記埋め込み絶縁膜までの間の前記ウェル領域は、前記第1の半導体領域の表面濃度よりも低い不純物濃度になっていることを特徴とする横型半導体デバイス。 - 前記第1の半導体領域端と前記第2半導体領域端の間に間隔を設ける請求項1記載の横型半導体デバイス。
- 前記第1の半導体領域において、P型不純物の濃度分布の頂上は、前記半導体層表面から深さ0.5μm以内に位置する請求項1または2記載の横型半導体デバイス。
- 前記第1の半導体領域において、P型不純物の表面濃度は、前記頂上の濃度の5〜20%の範囲である請求項1,2または3記載の横型半導体デバイス。
- 前記第1の半導体領域下の前記半導体層に、前記半導体層よりも高濃度のP型の埋め込み領域が備わっている請求項1,2,3または4記載の横型半導体デバイス。
- 前記第1の半導体領域と前記ゲート電極の重なりの長さが、P型不純物の濃度分布の頂上の前記半導体層表面からの深さと、ほぼ同じである請求項1,2,3,4または5記載の横型半導体デバイス。
- 支持基板と、前記支持基板上に形成される埋め込み絶縁膜と、前記埋め込み絶縁膜上に形成されるP型の半導体層と、前記半導体層内の表面に形成されるN型のウェル領域と、前記半導体層内に前記ウェル領域と隣接もしくは離れて形成されるP型の第2の半導体領域と、前記ウェル領域内の表面に形成されるP型のソース領域と、前記第2の半導体領域内の表面に形成されたP型のドレイン領域と、前記ソース領域端から前記ウェル領域端の間に形成されるゲート絶縁膜と、前記ゲート絶縁膜上に形成されるゲート電極とを備え、
前記ソース領域の下方の半導体層には、N型の埋め込み領域が備えられて、前記埋め込み領域のN型不純物の拡散定数は、前記ウェル領域のN型不純物の拡散定数よりも小さいことを特徴とする横型半導体デバイス。 - 支持基板と、前記支持基板上に形成される埋め込み絶縁膜と、前記埋め込み絶縁膜上に形成されるN型の半導体層と、前記半導体層内の表面に形成されるN型のウェル領域と、前記半導体層内に前記ウェル領域と隣接もしくは離れて形成されるP型の第2の半導体領域と、前記ウェル領域内の表面に形成されるP型のソース領域と、前記第2の半導体領域内の表面に形成されたP型のドレイン領域と、前記ソース領域端から前記第2の半導体領域端の間に形成されるゲート絶縁膜と、前記ゲート絶縁膜上に形成されるゲート電極とを備え、
前記ソース領域の下方の半導体層には、N型の埋め込み領域が備えられて、前記埋め込み領域のN型不純物の拡散定数は、前記ウェル領域のN型不純物の拡散定数よりも小さいことを特徴とする横型半導体デバイス。 - 前記埋め込み領域が、前記ソース領域下方からドレイン側に向かって延在している請求項7または8記載の横型半導体デバイス。
- 前記埋め込み領域のN型不純物がアンチモン又は砒素で、前記ウェル領域のN型不純物が燐である請求項7,8または9記載の横型半導体デバイス。
- 支持基板上に埋め込み絶縁膜を介して形成したP型またはN型の半導体層に、マスク層を形成する工程と、前記マスク層をマスクとしてN型の第1の不純物のイオン注入を用いて前記半導体層に埋め込み領域を形成する工程と、前記マスク層をマスクとして前記第1の不純物よりも拡散定数が大きいN型の第2の不純物のイオン注入を行う工程と、前記マスク層を除去して前記半導体層表面にエピタキシャル成長を行う工程と、熱処理により前記第2の不純物を半導体層表面まで到達してウェル領域を形成する工程とを含む横型半導体デバイスの製造方法。
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TWI487112B (zh) * | 2012-08-20 | 2015-06-01 | Vanguard Int Semiconduct Corp | 半導體裝置及其製造方法 |
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JP2006261639A (ja) * | 2005-02-16 | 2006-09-28 | Renesas Technology Corp | 半導体装置、ドライバ回路及び半導体装置の製造方法 |
KR100761825B1 (ko) * | 2005-10-25 | 2007-09-28 | 삼성전자주식회사 | 횡형 디모스 (ldmos) 트랜지스터 및 그 제조 방법 |
JP2008010628A (ja) * | 2006-06-29 | 2008-01-17 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US7462885B2 (en) * | 2006-11-30 | 2008-12-09 | Taiwan Semiconductor Manufacturing Co. | ESD structure for high voltage ESD protection |
JP5261927B2 (ja) | 2006-12-11 | 2013-08-14 | パナソニック株式会社 | 半導体装置 |
JP5479671B2 (ja) * | 2007-09-10 | 2014-04-23 | ローム株式会社 | 半導体装置 |
JP5410012B2 (ja) * | 2007-09-28 | 2014-02-05 | ローム株式会社 | 半導体装置 |
JP5272410B2 (ja) | 2008-01-11 | 2013-08-28 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP2010010408A (ja) * | 2008-06-27 | 2010-01-14 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2010258210A (ja) * | 2009-04-24 | 2010-11-11 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP5586546B2 (ja) * | 2011-03-23 | 2014-09-10 | 株式会社東芝 | 半導体装置 |
JP5902949B2 (ja) * | 2012-01-05 | 2016-04-13 | 株式会社 日立パワーデバイス | 半導体装置 |
CN103426927B (zh) * | 2012-05-18 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Ldmos晶体管及制造方法 |
US9076837B2 (en) * | 2012-07-06 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage |
JP2014207324A (ja) * | 2013-04-12 | 2014-10-30 | 旭化成エレクトロニクス株式会社 | 半導体装置及びその製造方法 |
CN104681621B (zh) | 2015-02-15 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | 一种源极抬高电压使用的高压ldmos及其制造方法 |
JP7153559B2 (ja) * | 2017-07-14 | 2022-10-14 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
CN112397567A (zh) * | 2019-08-16 | 2021-02-23 | 天津大学 | 一种具有p型横向变掺杂区的高压resurf ldmos器件 |
CN112420804A (zh) * | 2019-08-21 | 2021-02-26 | 天津大学 | 一种具有p型双重补偿结构的高压resurf ldmos器件 |
CN111524975A (zh) * | 2020-04-17 | 2020-08-11 | 华虹半导体(无锡)有限公司 | 横向扩散高压器件及其制作方法 |
US11749718B2 (en) * | 2021-03-05 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
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DE69225552T2 (de) * | 1991-10-15 | 1999-01-07 | Texas Instruments Inc., Dallas, Tex. | Lateraler doppel-diffundierter MOS-Transistor und Verfahren zu seiner Herstellung |
JP3258123B2 (ja) * | 1993-03-15 | 2002-02-18 | 株式会社東芝 | 半導体装置 |
JPH0897163A (ja) * | 1994-07-28 | 1996-04-12 | Hitachi Ltd | 半導体ウエハの製造方法、半導体ウエハ、半導体集積回路装置の製造方法および半導体集積回路装置 |
TW366543B (en) | 1996-12-23 | 1999-08-11 | Nxp Bv | Semiconductor device |
US6107127A (en) * | 1998-09-02 | 2000-08-22 | Kocon; Christopher B. | Method of making shallow well MOSFET structure |
JP3473460B2 (ja) | 1998-11-20 | 2003-12-02 | 富士電機株式会社 | 横型半導体装置 |
JP2000216393A (ja) | 1999-01-26 | 2000-08-04 | Sony Corp | 半導体装置の製造方法及び液晶表示装置 |
JP2001274390A (ja) * | 2000-01-18 | 2001-10-05 | Fuji Electric Co Ltd | 高耐圧デバイスおよびその製造方法、不純物拡散領域の形成方法 |
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TWI487112B (zh) * | 2012-08-20 | 2015-06-01 | Vanguard Int Semiconduct Corp | 半導體裝置及其製造方法 |
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