CN101641770B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101641770B
CN101641770B CN200780052401XA CN200780052401A CN101641770B CN 101641770 B CN101641770 B CN 101641770B CN 200780052401X A CN200780052401X A CN 200780052401XA CN 200780052401 A CN200780052401 A CN 200780052401A CN 101641770 B CN101641770 B CN 101641770B
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semiconductor device
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宫下俊彦
池田圭司
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Fujitsu Semiconductor Ltd
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Abstract

一种半导体器件，具有：半导体基板上的栅极电极(13)；沟道区域(CH)，其设置在上述栅极电极的下方的半导体基板区域；变形生成层(21)，其用于对上述沟道区域赋予应力；对上述沟道区域的源极端(A)施加的变形的绝对值大于对漏极端施加的变形的绝对值。在优选的构成例中，还具有侧壁隔离层(17)，该侧壁隔离层形成在栅极电极的侧壁上，形成在上述栅极电极的源极侧的侧壁宽度(W1)小于形成在上述栅极电极的漏极侧的侧壁宽度(W2)。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，特别涉及在应用变形硅技术的MOS型半导体器件中能够使微细化和晶体管的特性维持并存的非对称侧壁隔离层结构及其制造方法。 
背景技术
使用硅(Si)的CMOS器件技术的发展支撑着今天的电子学产业，目前为了进一步提高性能，仍然以超过迄今为止的速度的速度进行微细化。以工艺学节点表示的Si CMOS器件的时代目前开始65nm节点的大量生产，在开发阶段，将其中心转移至45nm节点。并且，还开始开发作为下一代的32nm节点。这样，随着时代的发展，即，随着微细化的发展，MOSFET的栅极长度缩小为比代表其时代的半间距更小的尺寸，即，缩小为35nm(65nm节点)、25nm(45nm节点)，正在快速接近MOSFET动作的物理限界。 
若如此促进微细化，则仅通过已经变得简单的包含栅极长度的器件尺寸的定标(scaling)，不能提高CMOS器件特性以及电路特性，反而会使其劣化。 
在图1示出伴随着栅极长度定标的电路特性的变化。在未考虑反向电流Ioff的增加的理论上的简单定标中，若栅极长度变得微细化，则会使电流密度Ion增加，使延迟时间减少，即，会提高电路速度。但是，在Ioff恒定的定标中，从图1的曲线图可知，在栅极长度为40nm以下的区域，延迟时间反而会增大。认为其原因在于，寄生电阻相对于MOSFET的全部电阻所占的比例增大，变成与沟道电阻相同的程度。即，意味着，正在进入不能忽视寄生电阻的影响的区域。但是，即使允许这样的特性劣化，根据芯片尺寸的缩小等要求，随着时代的发展继续缩小器件尺寸是必要且不可欠缺的。 
在上述背景下，在进行栅极长度定标时，作为提高与微细化不同的晶体管特性的技术，开始引入了被称为“技术推进器(technology booster)”的技术。在技术推进器中作为最有希望的技术进行开发的技术是变形硅技术。 变形硅技术是这样的技术，即，通过对CMOS晶体管的沟道区域施加变形，提高载流子的移动性，从而提高晶体管特性。作为对沟道区域施加变形的方法，有如下方法，即，在形成晶体管后覆盖应力膜，或者在源级/漏极区域嵌入晶格常数与硅不同的物质，或者利用栅极的堆积膨胀而挤压沟道，上述方法开始实际应用在产品中。 
目前，变形硅技术作为以低成本改善特性的技术，成为必要且不可欠缺的技术。并且，为了进一步改善CMOS晶体管的特性，要求进一步加强沟道变形程度。 
目前，在广泛使用的基于接触蚀刻阻止层(CESL)(contact etching-stoplayer)的工序感应单轴变形技术中，为了进一步加强沟道变形，有效的方法是提高包含侧壁(SW)宽度的栅极的纵横比。为了使纵横比增大，需要使栅极高度变高或者使SW宽度变小。 
图2中的(a)是表示SW宽度恒定时的、从CESL施加的沟道应力的多栅极高度依存性的曲线图；图2中的(b)示出多栅极高度恒定时的SW宽度依存性。在曲线图中，空心圆圈是沟道长度方向(适宜地简单称为“沟道方向”)上的应力，三角形是与其正交的沟道宽度方向上的应力。从图2中的(a)和图2中的(b)可知，多栅极的高度越高，另外，SW宽度越小，特别使沟道方向上的应力上升，有效地对沟道施加变形。换言之，通过使包含SW宽度为止的栅极的纵横比增大，能够有效地对沟道部施加应力。 
根据这样的理由，为了提高栅极的纵横比，开发缩小SW(最终省略)的技术。但是，SW发挥注入深的SD杂质时的掩模的作用，具有抑制短沟道效应的功能。因此，若简单地减小SW宽度，则使短沟道耐性劣化，从而30nm以下的栅极长度下的动作难以进行。还考虑了在注入SD后缩小SW的方法，但是担心使注入层受损。 
此外，作为与变形Si技术无关的晶体管的非对称SW构成的例子，已知如下方法：与所希望的栅极电极相邻地配置虚拟栅极电极，并控制与虚拟栅极电极之间的距离，由此制造SW宽度不对称的晶体管(例如参照专利文献1)。该方法通过减小源极侧的SW宽度，减小源极侧的低浓度杂质扩散区域的宽度，从而防止电流因寄生电阻而降低，另外，减小漏极侧的低浓度杂质扩散区域的电场，从而提高热载流子耐性。 
另外，还公知如下结构，即，仅将栅极电极的漏极侧的SW做成二层结构的偏斜隔离层结构(例如参照专利文献2)，以及通过将栅极电极的沟道方向上的剖面形状做成如船帆那样的不对称的形状，从而较厚地形成漏极侧的SW的非对称SW结构(例如参照专利文献3)。通过这些结构，抑制短沟道效应。 
专利文献1：JP特开2002-190589号公报。 
专利文献2：JP特开2005-268620号公报。 
专利文献3：JP特开平8-153877号公报。 
发明内容
发明要解决的问题 
上述文献均与变形Si技术无关，没有根据与对沟道施加的应力的关系说明非对称性。 
因此，本发明要解决的问题是提供一种器件结构及其制造工艺，在45nm节点以后的时代的变形Si技术中，特别在有效地对沟道施加来自接触蚀刻阻止层(CESL)的变形以进行定标的微细CMOS器件中，也改善晶体管特性。 
用于解决问题的手段 
在进行CMOS器件的定标方面上，应力技术的引入是必须的，但是在栅极长度截止于30nm的区域，冲击输送处于主导地位，其中，上述冲击输送是指，在沟道移动的载流子在从源极到达漏极的期间一次也不散射的输送。在冲击传输中，基于沟道变形来提高移动性的技术对于在沟道中移动的载流子来说不具有意义，而由源极边缘的载流子的热注入速度决定。 
发明人发现了：为了提高微细化的半导体器件的特性，特别是为了提高栅极长度为30nm以下的冲击传输区域的器件特性，重要的是在源极端集中施加沟道变形。 
具体地说，在本发明的第一技术方案中，半导体器件具有：半导体基板上的栅极电极；沟道区域，其设置在上述栅极电极的下方的半导体基板区域；变形生成层，其用于对上述沟道区域赋予应力；对上述沟道区域的源极端施加的变形的绝对值大于对漏极端施加的变形的绝对值。 
在优选的构成例中，还具有侧壁隔离层，该侧壁隔离层形成在上述栅极电极的侧壁；在上述侧壁隔离层中，形成在上述栅极电极的源极侧的侧壁宽度小于形成在上述栅极电极的漏极侧的侧壁宽度。 
例如，上述变形生成层是位于上述栅极电极的上方的接触蚀刻阻止层。或者，上述变形生成层也可以是嵌入在上述半导体基板的源级/漏极区域的化合物半导体层。 
本发明的第二技术方案是一种半导体器件的制造方法。该方法包括如下工序：(a)在半导体基板上形成栅极电极；(b)在上述栅极电极的两侧形成侧壁隔离层；(c)在上述侧壁隔离层中，通过对左右的侧壁注入不同的离子，以使蚀刻速率不同；(d)对上述注入离子后的侧壁隔离层进行蚀刻。 
在优选的制造例中，相对于所述栅极电极以规定的(例如30～50度)倾斜角，从一方向对上述侧壁注入离子。 
另外，优选还包括如下工序：在形成侧壁后，形成对上述栅极电极的正下方的上述半导体基板区域赋予应力的变形生成层。 
发明的效果 
通过上述结构和方法，在栅极长度为30nm以下的高性能逻辑器件中通过沟道变形能够高效率地提高特性，并且抑制短沟道效应，在30nm以下也能够进行切换动作。 
附图说明
图1是表示伴随着栅极长度定标的电路特性的劣化的曲线图。 
图2是表示因增加栅极纵横比而引起的沟道方向上的应力上升的曲线图。 
图3是表示本发明一实施方式的半导体器件的结构的概略剖视图。 
图4是表示PMOSFET沟道区域上的应力分布的模拟结果，其中，上述PMOSFET沟道区域具有赋予压缩应力的CESL。 
图5是用于说明对源极端施加变形的效果的图。 
图6是本发明实施方式的半导体器件的变形例。 
图7是本发明实施方式的半导体器件的另一变形例。 
图8是本发明实施方式的半导体器件的又一变形例。 
图9A是本发明一实施方式的半导体器件的制造工序图。 
图9B是本发明一实施方式的半导体器件的制造工序图。 
图9C是本发明一实施方式的半导体器件的制造工序图。 
图9D是本发明一实施方式的半导体器件的制造工序图。 
图9E是本发明一实施方式的半导体器件的制造工序图。 
图9F是本发明一实施方式的半导体器件的制造工序图。 
图9G是本发明一实施方式的半导体器件的制造工序图。 
图9H是本发明一实施方式的半导体器件的制造工序图。 
图10A是本发明的另一实施方式的半导体器件的制造工序图。 
图10B是本发明的另一实施方式的半导体器件的制造工序图。 
图10C是本发明的另一实施方式的半导体器件的制造工序图。 
图10D是本发明的另一实施方式的半导体器件的制造工序图。 
图10E是本发明的另一实施方式的半导体器件的制造工序图。 
图10F是本发明的另一实施方式的半导体器件的制造工序图。 
图10G是本发明的另一实施方式的半导体器件的制造工序图。 
图10H是本发明的另一实施方式的半导体器件的制造工序图。 
附图标记的说明 
10、10A、10B、10C  半导体器件 
11  半导体基板 
12  栅极绝缘膜 
13  栅极电极 
14  源级/漏极 
17、27  侧壁隔离层 
17S、27S  源极侧侧壁 
17D、27D  漏极侧侧壁 
21  接触蚀刻阻止层(变形生成层) 
24  变形SiGe源极/漏极(变形生成层) 
34  变形SiC源级/漏极(变形生成层) 
CH  沟道区域 
A  沟道区域源极端 
具体实施方式
下面参照附图对本发明的优选实施方式进行说明。图3是表示本发明一实施方式的半导体器件的构成例的概略剖视图。在图3的例子中，在半导体基板11上配置有由NMOSFET和PMOSFET构成的CMOS器件。 
各MOSFET在半导体基板11上具有：隔着栅极绝缘膜12而形成的栅极电极13、在半导体基板11的栅极的正下方的区域延伸的沟道区域(CH)以及向沟道区域的两侧扩展的源级/漏极区域14。在栅极电极13的两侧设置有侧壁隔离层17，源极侧的侧壁(SW)17S的宽度W1比漏极侧的侧壁(SW)17D的宽度W2窄。 
PMOSFET和NMOSFET隔着保护膜29被接触蚀刻阻止层(CESL)21覆盖。CESL21发挥蚀刻阻止膜的功能，同时还发挥变形生成层的功能。NMOSFET上的CESL21t对NMOSFET的沟道区域(CH)施加沟道长度方向上的拉伸变形和深度方向上的压缩变形。在这个意义上，称之为“拉伸CESL”。另一方面，PMOSFET上的CESL21c对PMOSFET的沟道区域施加沟道长度方向上的压缩变形和深度方向上的拉伸变形。在这个意义上，称之为“压缩CESL”。 
如上所述，在图3的CMOSFET中，位于栅极侧壁的侧壁17的宽度在源极侧小于漏极侧。一般，随着栅极长度减小，由于从漏极区域14d起的耗尽层的延伸，尤其是由于来自deep-drain的电场的影响，对栅极的沟道电场的贡献变小、阈值电压下降的短沟道效应成为问题。为了尽量地抑制该短沟道效应，有效的是，使漏极14d侧的深的拡散区域尽可能地离开沟道端，即，使SW宽度W增大。 
但是，另一方面，如图3所示，在使用程序感应的单轴性变形技术的情况下，特别在SW端能够得到大的变形(或者应力)，因此为了通过基于变形的移动性改善来提高特性，优选地，使SW宽度尽量小。 
图4是表示通过二维模拟对PMOSFET的沟道区域的应力分布进行计算 的结果的曲线图，其中，上述PMOSFET的沟道区域被生成压缩应力的CESL21覆盖。如箭头所示，知道如下情形，即，沟道方向(X方向)的应力在SW端增大，随着朝向沟道中央而衰减。 
另一方面，在由于微细化使栅极长度变短，并且进入到从源极注入的载流子在沟道中一次也未散射而到达漏极的冲击(ballistic)载流子输送区域的情况下，超过源极电势的具有全扩散性(diffusive)的载流子注入速度成为载流子输送中的瓶颈，对于器件特性的改善来说，重要的是进一步提高载流子注入速度。 
图5是示意性地表示该情形的图。若增大载流子从源极区域越过电势阻挡层而注入到沟道区域的注入速度V，则可以改善器件特性。这意味着，即，无需对沟道整体均匀地施加变形，而在源极端(在图3中，周缘A的区域)高效率地施加变形即可。 
由此，如图3的椭圆所示，为了抑制从漏极侧的深的扩散层区域14d起的耗尽层的延伸(DIBL)，使漏极侧的侧壁17D的宽度W2增大，另一方面，为了加强源极端A的变形程度，减小源极侧的侧壁17S的宽度W1。这样的变形Si下的非对称SW结构可以说是45nm节点(node)以后的理想的CMOSFET结构。 
图6是表示图3的半导体器件10的变形例的图。半导体器件10A为了进一步改善PMOSFET的特性，采用在源级/漏极(SD)区域嵌入了作为变形生成层的SiGe的embedded-SiGe结构(嵌入SiGe结构)。SiGe-SD层24对P沟道区域施加单轴性的压缩应力，以赋予变形。通过并用SiGe-SD层24和压缩SESL层21c，进一步提高PMOSFET中的载流子的移动性。在这样的情况下，也在NMOSFET和PMOSFET双方中使源极侧侧壁17S的宽度W1小于漏极侧侧壁17D的宽度W2，由此在沟道区域的源极端A更有效地施加变形。 
图7是表示图3的半导体器件10的另一变形例的图。半导体器件10B为了进一步改善NMOSFET的特性，采用在NMOSFET的源级/漏极(SD)区域嵌入了作为变形生成层的SiC的embedded-SiC结构(嵌入SiC结构)。SiC-SD层34对N沟道区域施加拉伸应力。通过并用SiC-SD层34和拉伸CESL21t，能够进一步改善NMOSFET的特性。而且，在NMOSFET和 PMOSFET双方中使源极侧侧壁17S的宽度W1小于漏极侧侧壁17D的宽度W2，由此在沟道区域的源极端A更有效地施加变形。 
图8是表示图3的半导体器件10的另一变形例的图。半导体器件10C为了进一步改善NMOSFET和PMOSFET双方的特性，在NMOSFET的源级/漏极(SD)区域嵌入用于赋予拉伸应力的SiC以作为SiC-SD层34，另一方面，在PMOSFET的源级/漏极(SD)区域嵌入用于赋予压缩应力的SiGe以作为SiGe-SD层24。在NMOSFET和PMOSFET双方中使源极侧侧壁17S的宽度W1小于漏极侧侧壁17D的宽度W2，由此在沟道区域的源极端A有效地施加变形。 
在图9A～9H示出图6的半导体器件10A的制造工序的一例。首先，如图9A所示，在硅基板11的规定位置形成STI等的元件分离区域15，在硅基板11的规定区域形成规定的导电型的阱(未图示)，并导入沟道杂质(未图示)，然后，对表面进行净化处理，并堆积栅极绝缘材料膜和多晶硅膜。例如，通过利用超高解像技术的准分子激光器光刻法和RIE，在栅极绝缘膜12上形成线宽度为18nm～30nm的栅极电极13。将栅极电极13作为掩模，形成各MOSFET的源级/漏极延伸区域(SD extension)16。 
例如，通过As+、2keV、1E15cm-2的离子注入和B+、10keV、1E13cm-2、倾斜角30度、4方向的微小(pocket)杂质注入，形成NMOS的源级/漏极延伸区域16n。例如，通过B+、0.5kev、1E15cm-2的离子注入和As+、40keV、5E12cm-2、倾斜角30度、4方向的微小杂质注入，形成PMOS的源级/漏极延伸区域16p。 
接着，如图9B所示，通过成膜温度为600℃以下的CVD法，堆积10nm左右的SiO2膜17a，接着堆积50nm左右的SiN膜17b，然后，通过RIE，对整个面进行蚀刻，在栅极电极13的两侧留下侧壁17。由于深的SD注入，假设该阶段的侧壁的宽度不影响短沟道效应。 
接着，如图9C所示，对于在电路内统一于一方向的栅极，从源极侧，从一方向注入用于加快氮化硅膜侧壁(SiN SW)17b的湿式蚀刻速率的离子。在该例子中，在3keV、5E14cm-2的条件下，以30～60度的倾斜角注入P+。 
而且，如图9D所示，从漏极侧，从一方向注入用于减慢氮化硅膜侧壁18b的湿式蚀刻速率的离子。在该例子中，在1keV、5E14cm-2的条件下，以 30～60度的倾斜角注入B+。 
针对图9C和图9D的离子注入而言，相对于栅极倾斜30度以上的高角度从一方向进行注入，因此有选择地对一侧的侧壁17注入杂质。另外，将注入能量和注入剂量的条件设定为：不影响MOSFET的短沟道效应，并且使侧壁氮化膜17b的湿式蚀刻速率充分地变化。另外，若有必要，则在注入后例如通过1000℃以下、0sec的尖峰式RTA(spike RTA)进行退火。通过该退火也能够使有选择地注入离子的侧壁的湿式蚀刻速率的差增大。 
接着，如图9E所示，若通过基于磷酸(H3PO4)的湿式蚀刻来应用于晶片的整个面，则源极侧/漏极侧的侧壁17相对于磷酸的蚀刻速率不同，使得源极侧进一步被蚀刻，能够实现左右不对称的侧壁宽度。在此，若将源极侧SW宽度设为W1，将漏极侧SW宽度设为W2，则W1＜W2。 
此外，也可以只进行图9C的离子注入和图9D的离子注入中的任意一种离子注入，其中，上述图9C的离子注入是指，向源极侧注入湿式蚀刻促进用的离子，上述图9D的离子注入是指，向漏极侧注入湿式蚀刻延迟用的离子。这是因为，不管向哪一侧注入离子，都在源极侧和漏极侧出现湿式蚀刻速率差，因此在图9E的湿式工序中能够实现非对称的SW形状。 
接着，如图9F所示，在整个面堆积覆盖氧化膜22，并通过光刻法仅在PMOS区域形成具有开口图形的抗蚀剂掩模23，通过RIE等使PMOS区域的基板表面露出。 
接着，如图9G所示，通过干式蚀刻，在PMOS的源级/漏极区域形成槽25，并去除抗蚀剂掩模23。 
接着，如图9H所示，在PMOS区域的槽25中，例如有选择地外延生长掺杂有B的SiGe，从而形成变形源级/漏极24。然后，去除NMOS区域的覆盖氧化膜(SiO掩模)22，仅覆盖PMOS区域来注入深的SD杂质，然后，进行基于RTA的杂质活性化处理以形成深的源级/漏极区域14s、14d，并去除PMOS区域的掩模(未图示)。然后，虽然未图示，但是对栅极电极13的表面和源级/漏极14以及变形源级/漏极24的表面进行硅化处理，并形成保护膜、CESL，从而得到如图6所示的半导体器件10A。 
图10A～图10H是表示半导体器件的制造工序的变形例的工序图。在变形例中，用单层侧壁代替双层侧壁，而且，在源极侧和漏极侧改变用于使侧 壁的蚀刻速率发生变化的离子种类和腐蚀剂。 
在图10A中，与图9同样地在形成有STI15、阱(未图示)以及沟道(未图示)的硅基板11上的所定位置形成栅极绝缘膜12和栅极电极13，并交互覆盖PMOS区域和NMOS区域而形成源级/漏极延伸区16n、16p。 
在图10B中，例如在600℃以下的成膜温度下，通过CVD法在整个面上堆积形成厚度为60nm左右的氧化硅膜(SiO2)，并进行各向异性蚀刻，从而形成SiO2单层的侧壁27。 
在图10C中，在10keV、5E14cm-2的条件下，以30～60度的倾斜角，从一方向对源极侧的侧壁27注入Ge+。 
接着，如图10D所示，在1keV、5E14cm-2的条件下，以30～60度的倾斜角，从漏极侧从一方向注入B+。由此，相对于源极侧侧壁27，能够加快相对于氟酸(HF)的蚀刻速率。 
此外，仅进行图10C和图10D的工序中的某一工序，也能够使相对于氟酸(HF)的蚀刻速率不同，这与图9的工序相同。另外，在进行蚀刻速率促进和/或延迟用的离子注入后进行退火处理，由此能够使蚀刻速率的差异增大，这也与图9的工序相同。将上述注入能量、注入剂量的条件也设定为有效地使相对于HF的蚀刻速率不同的条件。 
接着，如图10E所示，使用氟酸对整个面进行湿式蚀刻，由此使源极侧侧壁27S的宽度W1小于漏极侧侧壁27D的宽度W2。 
图10F、图10G、图10H的工序与图9F、图9G、图9H同样地在PMOS区域形成变形SiGe源级/漏极区域24s、24d，并在NMOS区域形成深的源级/漏极区域14s、14d，然后，隔着保护膜在PMOS区域形成压缩CESL，在NMOS区域形成拉伸CESL。 
这样，适宜地选择离子种类和腐蚀剂，并在源极侧和漏极侧进行高角度的一方向的离子注入，由此能够形成非对称的侧壁隔离层。 
这样，通过使用变形Si技术和非对称侧壁结构，在栅极长度为30nm以下的高性能逻辑装置中也能够通过沟道变形有效地提高特性，并且，能够抑制短沟道效应以实现恰当地工作的器件。 

Claims (17)

1.一种半导体器件，其特征在于，具有：
半导体基板上的栅极电极；
沟道区域，其设置在上述栅极电极的下方的半导体基板区域；
变形生成层，其用于对上述沟道区域赋予应力；
侧壁隔离层，该侧壁隔离层形成在上述栅极电极的侧壁；
上述侧壁隔离层中，形成在上述栅极电极的源极侧的侧壁宽度小于形成在上述栅极电极的漏极侧的侧壁宽度；
对上述沟道区域的源极端施加的变形的绝对值大于对漏极端施加的变形的绝对值。
2.根据权利要求1所述的半导体器件，其特征在于，上述变形生成层是位于上述栅极电极的上方的接触蚀刻阻止层。
3.根据权利要求1所述的半导体器件，其特征在于，上述变形生成层是嵌入在上述半导体基板的源级/漏极区域中的化合物半导体层。
4.根据权利要求1所述的半导体器件，其特征在于，
上述半导体器件具有NMOS区域和PMOS区域，
上述变形生成层对上述NMOS区域赋予拉伸应力，对上述PMOS区域赋予压缩应力。
5.根据权利要求1所述的半导体器件，其特征在于，对上述源极侧侧壁和漏极侧侧壁中的至少一个侧壁中注入有离子，该离子用于改变相对于规定腐蚀剂的湿式蚀刻速率。
6.根据权利要求1所述的半导体器件，其特征在于，在上述源极侧的侧壁中离子注入有P或Ge。
7.根据权利要求1所述的半导体器件，其特征在于，在上述漏极侧的侧壁中离子注入有B。
8.根据权利要求1所述的半导体器件，其特征在于，上述侧壁具有氧化硅膜和氮化硅膜的二层结构，在源极侧的上述氮化硅膜中注入有用于促进相对于规定腐蚀剂的蚀刻速率的离子，和/或在漏极侧的上述氮化硅膜中注入有用于减慢相对于上述规定腐蚀剂的蚀刻速率的离子。
9.一种半导体器件的制造方法，其特征在于，包括如下工序：
在半导体基板上形成栅极电极；
在上述栅极电极的两侧形成侧壁隔离层；
在上述侧壁隔离层中，通过对左右的侧壁注入不同的离子，以使湿式蚀刻速率不同，
对上述注入离子后的侧壁隔离层进行蚀刻，
在对上述侧壁隔离层进行蚀刻后，形成对上述栅极电极的下方的上述半导体基板区域赋予应力的变形生成层。
10.根据权利要求9所述的半导体器件的制造方法，其特征在于，
以规定的倾斜角，从一方向注入上述离子。
11.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，上述蚀刻是湿式蚀刻。
12.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，
将上述侧壁隔离层做成氧化硅膜和氮化硅膜的二层结构，
对上述左右的侧壁中的一侧的侧壁，从上述一方向注入磷(P)，
使用磷酸对注入上述磷(P)后的侧壁隔离层进行湿式蚀刻。
13.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，
由氧化硅膜形成上述侧壁隔离层，
对上述左右的侧壁中的一侧的侧壁，从上述一方向注入锗(Ge)，使用氟酸对注入上述锗(Ge)后的侧壁隔离层进行湿式蚀刻。
14.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，对上述左右的侧壁中的一侧的侧壁，从上述一方向注入硼(B)，以减慢相对于磷酸或氟酸的湿式蚀刻速率。
15.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，相对于上述栅极电极以30～60度的倾斜角从一方向对上述侧壁进行离子注入。
16.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，还包括如下工序：在上述栅极电极的上方形成接触蚀刻阻止层来作为上述变形生成层。
17.根据权利要求9或10所述的半导体器件的制造方法，其特征在于，还包括如下工序：在上述栅极电极的两侧的源级/漏极区域形成变形源级/漏极层来作为上述变形生成层。
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