CN101483178B - 快闪存储单元及造成分离侧壁氧化的方法 - Google Patents

快闪存储单元及造成分离侧壁氧化的方法 Download PDF

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CN101483178B
CN101483178B CN2009100054848A CN200910005484A CN101483178B CN 101483178 B CN101483178 B CN 101483178B CN 2009100054848 A CN2009100054848 A CN 2009100054848A CN 200910005484 A CN200910005484 A CN 200910005484A CN 101483178 B CN101483178 B CN 101483178B
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D·沈
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Abstract

本发明是一种快闪存储单元及造成分离侧壁氧化的方法。本发明揭露了一种可使集成电路具有紧密的逻辑电路及/或线性电路区域与紧密的存储区域的制程与产品。在一共同的基板上，一双重硬罩幕处理单独形成了逻辑电路及/或线性电路晶体管以及EEPROM存储晶体管的堆栈。藉由使用该处理，该等逻辑电路及/或线性电路晶体管与存储晶体管具有不同的侧壁绝缘层厚度。该等逻辑电路及/或线性电路晶体管具有相对薄的侧壁绝缘层，而其足以提供与邻近装置与导体之间的隔离。该存储晶体管具有较厚的侧壁绝缘层以避免储存于该存储装置中的电荷会对该存储晶体管的操作产生不利的影响。

Description

快闪存储单元及造成分离侧壁氧化的方法
本申请是申请号为03821092.4、申请日为2003年9月3日、题为“快闪存储单元及造成分离侧壁氧化的方法”的中国发明专利申请的分案申请。
技术领域
本案涉及快闪存储单元及造成分离侧壁氧化的方法。
背景技术
一般而言，快闪存储单元是与逻辑电路或线性电路晶体管形成于相同的基板上；为具有一有效率的制造过程，作为该等快闪存储单元控制栅极的晶体管与该等逻辑电路及线性电路晶体管通常会共享相同的多晶硅掩膜，且亦共享相同的侧壁氧化处理与相同的栅极之反应离子蚀刻(RIE)。虽然共享共同的步骤是有效率的，但却同时也出现一种或多种技术问题；由于特征尺寸变小，逻辑电路及/或线性电路晶体管便需要特别浅的源极与漏极之接合形成，以避免短沟道效应(SCE)；为了实现上述之特别浅的源极与漏极之接合形成，便必须将制造该装置之热预算维持的非常低，因此，必须要在一低温条件中执行侧壁氧化处理、或是省略侧壁氧化处理程序。然而，快闪存储单元的栅极边缘需要特别磨圆，以减少因尖锐的栅极边缘所引起的高电场，进而能够将电荷保留在该栅极之堆栈中。栅极之磨圆藉由浮动栅极所捕捉的电荷周围电场之降低而减少了泄漏电流。
发明内容
本发明利用一双重硬掩膜(HM)的方式，藉由逻辑电路与线性电路晶体管与快闪存储单元之侧壁氧化处理与温度的最佳化，来解决习知技术中所存在的问题。该逻辑电路与线性电路晶体管是藉由一硬掩膜而形成，而快闪存储晶体管是藉由另一硬掩膜所形成。一般的硬掩膜是由化学气相沉积(CVD)之TEOS(正硅酸四乙酯)氧化物所形成，虽然附加的硬掩膜对整体制程添加了许多步骤，然而其亦可避免为隔离该快闪存储单元控制栅极与该逻辑电路与线性电路晶体管之多晶硅而使用一额外之深紫外线(DUV)掩膜的花费，后者似乎是仅用以增进已存在的习知技术处理之一替代方式。更具体而言，在蚀刻该快闪存储单元之后添加一第二TEOS硬掩膜，其系于移除第一TEOS硬掩膜与形成快闪侧壁氧化物之后执行。
为了实行本发明，该基板被分为一含有电可擦可编程只读存储器(EEPROM)单元的区域以及含有线性电路或逻辑电路装置的其它区域，一三重阱则形成于该EEPROM区域中；接着形成该EEPROM晶体管之栅极堆栈，而此一步骤包含了形成一穿隧介电层、一穿隧多晶栅极层、一栅极间介电层与一控制栅极层。以一第一硬掩膜覆盖该基板，一般而言该第一硬掩膜是一TEOS层；对该EEPROM区域中的该TEOS层成形(patterned)并形成开口(opened)，以形成该EEPROM晶体管之源极与漏极区域。接着，注入该等源极与漏极区域并移除该TEOS层，且适当氧化该等EEPROM晶体管之侧壁。然后，沉积一第二TEOS硬掩膜于该等线性电路与逻辑电路区域，并单独对此TEOS硬掩膜进行成形以暴露该等线性电路与逻辑电路晶体管之源极与漏极区域；最后注入该等线性电路与逻辑电路晶体管，而该等线性电路与逻辑电路晶体管便以一习知的方式而完成。
本发明让制造者能够最佳化快闪堆栈与逻辑电路及/或线性电路堆栈上的侧壁绝缘层之厚度，其能够制造的装置可在其快闪晶体管与在逻辑电路及/或线性电路晶体管上具有不同侧壁介电质厚度；且此一结构克服了习知结构中快闪晶体管与在逻辑电路及/或线性电路晶体管具有相同侧壁厚度之缺点。藉由本发明，该等逻辑电路及/或线性电路装置具有较薄的侧壁氧化物且因而能够更紧密的排列，以增加该基板中的逻辑电路及/或线性电路电路。此外，该存储装置具有较厚的侧壁绝缘层，以于该存储晶体管操作时保护储存于该栅极间介电层中的电荷。
附图说明
图1至图4.1是沿着该EEPROM区域的字符线而表示在处理中的最初关键步骤；
图4.2至图8是沿着该EEPROM区域的位线而表示在处理中的最终关键步骤。
附图中部件符号的说明
18    基板
20    浅沟槽隔离区域
21    浮动栅极氧化层
22    多晶硅层
23    光致抗蚀剂
24            极间介电层
25            氧化物层
26            多晶硅层
30            TEOS层
31
32            TEOS层
36
41            P型阱
42            N型阱
50            三重阱
51            N型阱
52            P型阱
P-SUB         P型基板
LOGIC/LINEAR  逻辑电路/线性电路
EEPROM        电可擦可编程只读存储器
具体实施方式
请参见图1，对一P型基板18适当成形(patterned)以形成浅沟槽隔离区域20；该浅沟槽隔离区域20围绕各EEPROM晶体管与各对CMOS晶体管。熟习该项技艺之人士都可理解本发明亦可形成于一N型基板上，只要适当使用相反的掺杂物即可。如图2所示，以一浮动栅极氧化层21覆盖该基板，并接着覆盖一多晶硅层22；在沉积该等膜层之前，即先单独成形该基板的一适当部分(例如A部分)，并对其注入以具有一三重阱50，该三重阱50包含了一N型阱51与位于该P型基板18上、围住该N型阱51之一P型阱52。伴随此一叙述的图式说明了在区域B中的一对逻辑电路CMOS晶体管，该等区域可包含除了该对逻辑电路CMOS晶体管以外的晶体管；熟习该项技艺之人士都可理解可在该等区域B中形成具有一传导类型的晶体管，而晶体管的类型可为逻辑电路或线性电路，其包括但不限于功率晶体管(例如LDMOS晶体管)。
接着，以一光致抗蚀剂23对该等氧化物与多晶硅层进行成形以形成一浮动栅极堆栈；请参阅图3，一氮氧化物栅极间介电层24系形成于该基板上，该氮氧化物栅极间介电层24藉由光致抗蚀剂23而进行适当成形，以形成如图4所示之EEPROM堆栈中该ONO介电质三层其中的两层；进行至此，自周边区域B对该氮氧化物栅极间介电层24与多晶硅层11进行细段处理(stripped)，而其适于成形并注入以形成P型阱41与N型阱42。
接着，以一氧化物层25与后续之一第二多晶硅层26覆盖该基板18，该氧化物层25形成了该等逻辑电路与线性电路装置的栅极氧化层，并形成了该ONO介电层24之上氧化层。该多晶硅层26是供该等EEPROM晶体管与该等逻辑电路与线性电路晶体管的控制栅极之用。
一第一TEOS层30系沉积于该第二多晶硅层26之上，接着以光致抗蚀剂23适当成形该第一TEOS层30，以形成该EEPROM之源极与漏极区域开口；对源极与漏极区域适当注入以形成该EEPROM之源极与漏极。然后，藉由一高选择性反应离子蚀刻方式来移除该第一TEOS层30，并终止于多晶硅层26上；接着，该EEPROM栅极堆栈的侧壁系被氧化以提供一适用于快闪堆栈晶体管之侧壁氧化物。在温度为摄氏850至950°、时间为30分钟的炉中进行氧化，以在该栅极堆栈的多晶硅区域上成长厚度为15纳米(nanometers)的侧壁。然后，沉积一第二TEOS层32于该基板18上，以光致抗蚀剂23对该TEOS层32进行适当成形以形成栅极，并对其形成逻辑电路与线性电路晶体管之源极与漏极所需之开口。
对该等逻辑电路及/或线性电路晶体管之源极与漏极加以适当注入，藉由反应离子蚀刻来移除该第二TEOS层32，而外围的晶体管之栅极则会得到一较薄的侧壁氧化物。该侧壁氧化物的厚度约为6纳米，且是藉由一相对较短、较快速的热退火步骤所形成；该快速退火步骤是在温度约700至900℃中约实施10至20秒，其活化了在该逻辑电路及/或线性电路晶体管中的掺杂，但并不会驱使它们远达该基板。这样的结果导致一逻辑电路及/或线性电路区域具有相对较紧密排列的晶体管。
上述的处理使制造者能够制造一具有不同侧壁绝缘厚度之逻辑电路及/或线性电路与存储装置的单一集成电路。在逻辑电路及/或线性电路区域中，该等侧壁能够被最佳化为尽可能的薄，以于该逻辑电路及/或线性电路装置许可的区域中提供更多的晶体管；而在存储区域中，该等存储装置能够被最佳化为具有一足够厚的侧壁氧化物，以避免在该等存储晶体管操作时，储存于该栅极间介电层的电荷受到非预期的影响。

Claims (5)

1.一种具有逻辑电路及/或线性电路晶体管与存储装置的集成电路，所述集成电路包括：
逻辑电路及/或线性电路装置区域，其包括场效晶体管，各包括
自漏极所隔出的源极，
位于所述源极和所述漏极之间的沟道，
控制栅极，所述控制栅极包括位于所述沟道上的绝缘层与位于所述绝缘层上的栅极电极，以控制所述沟道中的电场，以及
逻辑电路及/或线性电路装置侧壁绝缘层，其位于所述栅极电极的侧边，以将所述栅极电极与邻近的晶体管隔离；
存储装置区域，所述存储装置区域包括电子可编程的存储装置，各包括
自漏极所隔出的源极，
位于所述源极和所述漏极之间的沟道，
位于所述沟道上的绝缘层和位于所述绝缘层上的第一电极，以控制所述沟道中的电场，
介电层，位于所述第一电极上，
第二电极，位于所述介电层上，用于将电压供应至存储晶体管以储存或移除电荷，以及
存储装置侧壁绝缘层，其位于所述第一与第二电极的侧边以减少所述电荷于基板中产生的电场，并将邻近的存储装置彼此隔离，其中所述存储装置侧壁绝缘层比所述逻辑电路及/或线性电路装置侧壁绝缘层更厚。
2.根据权利要求1所述的集成电路，其中所述逻辑电路及/或线性电路侧壁绝缘层的厚度少于所述存储装置侧壁绝缘层的厚度的一半。
3.根据权利要求1所述的集成电路，其中所述逻辑电路及/或线性电路侧壁绝缘层约为6纳米厚，而所述存储装置侧壁绝缘层约为15纳米厚。
4.根据权利要求1所述的集成电路，其中所述存储装置是快闪电可擦可编程只读存储器晶体管且形成于所述基板的三重阱区域中。
5.根据权利要求1所述的集成电路，其中所述电极是掺杂多晶硅。
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