五、發明說明（1) 408743- 本發明係有關於一種半導體積體電路製程，特別有關 於一種具有非晶矽頂蓋層（am〇rph〇us silic()n cap layer )之複晶矽金屬閘極（polycide gate)製造方法。 ‘ 在積體電路（ICs)的應用上，導體、半導體及絕緣層 等材料已被廣泛使用’而薄膜沈積（Thin Fiim Deposition)則為主要之半導體技術之一。 其中’在元件尺寸不斷縮小的情況下’為了提高閘極 的導電度’通常會利用複晶矽和金屬矽化物材料來形成半 導體元件之閘極，如第1圖所示，一般M〇s元件結構係在基 底10之主動區形成源/汲極11、且在源/汲極丨丨間之區域表( 面形成複晶石夕金屬閘極G 1和氮化石夕侧壁層（spacer) 1 9，而 複晶矽金屬閘極G1則包括一閘極氧化層12、一嗔hi發 ^ 1J、一矽化鎢層1 6、以及一氮化矽層1 8，此外，在形I 氮化石夕侧壁層1 9之前’一般係另加入一道快速高温氧化（ RTO :rapid thermal oxidation)製程，以在矽基底 1〇、 閘極複晶梦層14及梦化鎢層1 6侧壁形成一薄氧化.層1 7。 由於在形成矽化鎢層16後尚須經歷3道左右之高溫製 程（於稿後描述）’因此容易造成梦化鶴層16向外不正常辦 生（abnormal growth)之缺陷（defects)，尤其當此缺陷突 出於氮化矽侧壁層1 9時，更易導致M0S元件短路。 ， 為改善上述現象，傳統習知技術係在矽化鎢層丨6表面 形成一蓋…屋/，其一方面可以補充矽原子予矽化鎢 層1 6，另一方面則可以隔離氧氣入侵並降低應力，避免不 正常增生（abnormal growth)之缺陷（defects)。然而，在V. Description of the invention (1) 408743- The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly to a polycrystalline silicon metal having an amorphous silicon cap layer (am〇rph〇us silic () n cap layer). Gate (polycide gate) manufacturing method. ‘In the application of integrated circuits (ICs), materials such as conductors, semiconductors, and insulating layers have been widely used’, and thin film deposition (Thin Fiim Deposition) is one of the main semiconductor technologies. Among them, "in the case of ever-decreasing element size", in order to improve the conductivity of the gate electrode, polycrystalline silicon and metal silicide materials are usually used to form the gate of a semiconductor device. As shown in Fig. 1, a general MOS device The structure is a source / drain 11 formed in the active region of the substrate 10 and a region table between the source / drain 丨 (a polycrystalline stone metal gate G 1 and a nitride stone sidewall spacer 1 are formed on the surface 1 9, and the polycrystalline silicon metal gate G1 includes a gate oxide layer 12, a silicon oxide layer 1J, a tungsten silicide layer 16 and a silicon nitride layer 18. In addition, in the shape of a nitride nitride layer I Before the sidewall layer 19, a rapid thermal oxidation (RTO) process is generally added to form a thin layer on the silicon substrate 10, the gate polycrystalline dream layer 14, and the dream tungsten layer 16. Oxidation layer 1 7. As the tungsten silicide layer 16 has to be subjected to about 3 high-temperature processes (described later in the draft) after forming the tungsten silicide layer 16, it is easy to cause the abnormal growth defect of the dreaming crane layer 16 outward. (Defects), especially when the defect protrudes from the silicon nitride sidewall layer 19, it is more likely to cause a MOS device In order to improve the above-mentioned phenomenon, the conventionally known technology is to form a cover on the surface of the tungsten silicide layer 丨 6, which can supplement silicon atoms to the tungsten silicide layer 16 on the one hand, and can isolate the oxygen invasion and Reduce stress and avoid defects of abnormal growth. However, in
第4頁 五、發明說b月⑵ 402743 _____ 矽化鎢層16表面形成一非晶矽頂蓋層之方 成預期之效果，甚至有良率降低之情形發生有時並未能達 有鑑於此，本發明之目的即為了解決上述 【：種具有非晶石夕頂蓋層之複晶石夕合屬閘極製2法” 包括下列步驟，首先提供一基底；其 &方法，係 底表面；形成一複晶矽層於絕緣層表面 ：=層於基 鎢層於複晶矽層表®，其中，矽化鶴 > 成一矽化 成-非晶…層二 子士值決定；以及形成一絕緣遮蔽層= 原 ，隨之定義絕緣遮蔽層、非晶矽頂蓋 :頁蓋層表面 矽層和絕緣層，以構成複晶矽金屬閘* :石化鎢層、複晶 其中，此非晶矽頂蓋層之厚度與 子比值係成正相關；且當矽化鎢芦^ 、之矽/鎢原 至2.8的範圍時，非頂 厚8夕’鎢原子比值在2. 3 。 貝盍層厚度之範圍約在15至50埃. 、下就圖式說明本發明之一種具； 複晶石夕金屬閘極製造方 種具有非日日日發頂盘層之 圖式簡單說明 ~ 第1圖係顯示傳統複晶矽金屬 第2至4圖係顯示傳統複晶金/金閘屬: 流程圖。 7金屬閘極結構之製程步驟 第5圖係顯示傳統具有非晶 極結構剖面圖。 曰夕頂盒層之複晶矽金屬閘Page 4 5. The invention said that the month 402743 _____ The formation of an amorphous silicon cap layer on the surface of the tungsten silicide layer 16 has the expected effect, and even the decrease in the yield rate sometimes fails to achieve this. The purpose of the present invention is to solve the above-mentioned [: a method of polymorphite with an amorphous stone capping layer which is a gate method 2] including the following steps, first providing a substrate; its & method, the bottom surface; Forming a polycrystalline silicon layer on the surface of the insulating layer: = layer on the base tungsten layer on the polycrystalline silicon layer surface, where the silicide crane > forms a silicidation-amorphous ... layer is determined by two values; and an insulating shielding layer is formed = Original, followed by the definition of the insulating shielding layer and the amorphous silicon top cover: the surface silicon layer and the insulating layer of the cover layer to form a polycrystalline silicon metal gate *: a petrochemical tungsten layer and a polycrystalline layer, of which the amorphous silicon top cover layer The thickness and the sub-ratio are positively correlated; and when the tungsten silicide reed ^, the silicon / tungsten source to the range of 2.8, the non-top thickness of the tungsten atom ratio is 2.3. The range of the thickness of the shell layer is about 15 To 50 angstroms, the following diagram illustrates a device of the present invention; polycrystalline stone metal gate A brief description of the model with a non-day-to-day top disc layer ~ Figure 1 shows the traditional polycrystalline silicon metal Figures 2 to 4 show the traditional polycrystalline gold / gold gate genus: flowchart. 7 Metal gate Figure 5 shows the process steps of the pole structure. Figure 5 shows a traditional sectional view of an amorphous pole structure.
五、發明說明（3) 第6圖係顯示梦化鶴層之石夕/鶴原子 時’不同非晶矽頂蓋層厚度下，石夕化η範圍.， 之關係曲線圖。 ’、s *、、力，、製.程溫度 良率第7圖係顯示在不同非晶石夕了頁蓋層厚度下，賴元件之 第8a至8c圖係顯示在不同非晶矽頂蓋 ，:有既定石夕/鶴原子比值之石夕化鶴層 製尤積時間下 關係曲線圖。 /、表柱，獄度之 第9圖係顯示在最佳狀離下非日 化μ @&隹琅住狀L下，非日日矽頂蓋層厚度與矽 化鎢層之矽/鎢原子比值之關係曲線圖。 [符號說明] •基底~10，20 ;源/汲極~；π，21 ;閘極絕緣層〜12，22 :複晶矽層〜14，24 ;矽化鎢層〜16，26 ;薄氧化層〜17， 27 ;氮化矽層〜18，28 ;氮化矽間隙壁〜19，29 ;複晶矽金 屬閘極〜Gl ’ G2 ’ G3 ;不正常増生之缺陷〜30 ;非晶矽頂蓋 層〜4 0 〇 實施例 為方便比較起見，在此先說明第2至4圖之傳統複晶石夕 金屬閘極結構之製程步驟流程圖。 首先請參閱第2圖，該步驟為提供一基底20，基底20 係為一半導體材質，如矽（sili c〇n )，而形成方式則有 蟲晶（expitaxial)或絕緣層上有石夕（silicon on insulator)等，為方便說明，在此以一p型矽基底為例。 接著，先利用一隔離製程如熱氧化製程，來形成一場V. Description of the invention (3) Figure 6 is a graph showing the relationship between Shi Xihua's η range and the thickness of Shi Xihua / He Atomic Time in different layers of amorphous silicon. ', S * ,, force, and manufacturing process temperature yield Figure 7 shows different thicknesses of the amorphous cover sheet, and Figures 8a to 8c of the Lai element show different amorphous silicon top covers. : The relationship curve of Shixi Chemical Crane's layered system with a predetermined Shixi / Crane atomic ratio. /, Table column, the ninth figure of the jail degree shows the non-Japanese and Japanese silicon top-layer thickness and the silicon / tungsten atom of the tungsten silicide layer under the optimal state of the non-daily chemical μ @ & Graph of the relationship between the ratios. [Symbols] • Base ~ 10, 20; Source / Drain ~; π, 21; Gate insulation layer ~ 12, 22: Polycrystalline silicon layer ~ 14, 24; Tungsten silicide layer ~ 16, 26; Thin oxide layer ~ 17, 27; Silicon nitride layer ~ 18, 28; Silicon nitride spacers ~ 19, 29; Polycrystalline silicon metal gate ~ Gl 'G2' G3; Abnormally generated defects ~ 30; Amorphous silicon top cover Layers ~ 4 00 Example For the sake of comparison, the process flow chart of the conventional polycrystalline stone metal gate structure shown in FIGS. 2 to 4 will be described first. First, please refer to FIG. 2. This step is to provide a substrate 20. The substrate 20 is made of a semiconductor material, such as silicon (Silicon), and the formation method is expitaxial or the insulating layer is provided with Shi Xi ( silicon on insulator), etc., for convenience of explanation, a p-type silicon substrate is taken as an example here. Next, an isolation process such as a thermal oxidation process is used to form a field.
第6頁 五、發明說明（4) 絕緣層（field insulator )，並藉該場絕緣層來隔離出 主動區（未顯示），其次，在主動區上另以半導體製程如 薄膜沈積依序形成絕緣層如氧化層2 2、複晶矽層24，石夕化 鎢層26和一遮蔽層28。舉例而言，可先藉熱氧化在基底 2 0表面形成一薄的閘極氧化層2 2，再以化學氣相沈積製程 (CVD)形成一複晶矽層24於閘極氧化層22表面，此外，在 複石夕沈積製程中，亦可在同環境下捧入雜質 以提高其導電度。 接著’在約5 5 0 °C之製程溫度下，以化學氣相沈積製 程形成一矽化鎢層26(WSix ; x為石夕/鎢原子比值），其覆蓋（I、 在複晶碎層24表面。 ^然後，形成一絕緣遮蔽層（insulating mask)28以覆 蓋矽化鎢層26，例如在約80(rc之製程溫度下，以二氯矽 甲烷SiH2C12、氨NH3為主反應物，並藉低壓化學氣相沈積 (LPCVD)製程沈積一氮化矽層28。 其次’對前述基底20實施一快速熱退火製程（RTA)， 例如在約80 〇ec之溫度下進行快速熱退火製程，以釋放矽 化鎢層26之部分應力’並提升其強度。 請$閱第3圖，接著’利用微影製程及蝕刻程序，依 疋義氮化矽層28、矽化鎢層26、複晶矽層24和氧化層22U 以形成由閘極氧化層2 2a、閘極複晶矽層24a、圖案化之 ::匕鎢層26a、和圖案化之氮化石夕層—構成之複晶石夕金屬 請參閱第4圖’該步驟首先為在下之製程溫Page 6 V. Description of the invention (4) Insulation layer (field insulator), and the field insulation layer is used to isolate the active area (not shown). Secondly, the semiconductor is formed on the active area in order to form an insulation layer. The layers are, for example, an oxide layer 2, a polycrystalline silicon layer 24, a tungsten carbide layer 26, and a shielding layer 28. For example, a thin gate oxide layer 22 can be formed on the surface of the substrate 20 by thermal oxidation, and then a polycrystalline silicon layer 24 can be formed on the surface of the gate oxide layer 22 by a chemical vapor deposition process (CVD). In addition, in the process of Fushixi deposition, impurities can be introduced in the same environment to improve its conductivity. Next, at a process temperature of about 5 50 ° C, a tungsten silicide layer 26 is formed by a chemical vapor deposition process (WSix; x is a stone evening / tungsten atomic ratio), which covers (I. ^ Then, an insulating shielding layer 28 is formed to cover the tungsten silicide layer 26, for example, at a process temperature of about 80 (rc), dichlorosilicon methane SiH2C12, ammonia NH3 is the main reactant, and low pressure is used. A chemical vapor deposition (LPCVD) process deposits a silicon nitride layer 28. Next, a rapid thermal annealing process (RTA) is performed on the aforementioned substrate 20, for example, a rapid thermal annealing process is performed at a temperature of about 80 ° C to release silicidation. Partial stress of the tungsten layer 26 'and increase its strength. Please refer to Figure 3, and then use the lithography process and etching process to rely on the silicon nitride layer 28, tungsten silicide layer 26, polycrystalline silicon layer 24 and oxidation. The layer 22U is formed by a gate oxide layer 22a, a gate polycrystalline silicon layer 24a, a patterned :: tungsten tungsten layer 26a, and a patterned nitrided silicon layer-a polycrystalline stone metal. Please refer to Section 4 Figure 'This step is the first process temperature
第7頁 五、發明說明（5) 402743 度下’以一道快速高溫氧化（RT〇 : rapid thermai oxidation)製程’在矽基底2〇及閘極複晶矽層24及矽化鎢 層26a側壁形成一薄氧化層2 7，其次，在複晶矽金屬閘極— G2侧壁’如氮化矽層28a及薄氧化層27侧壁形成一絕緣侧 壁層29 ’例如可以二氯矽甲烷SiH2C12、氨nh3為主反應物 ’並藉低壓化學氣相沈積（LPCVD)製程沈積一氮化矽層， 接著進行回蝕刻步驟，以形成氮化矽侧壁層。 。 依據上述，由於在形成矽化鎢層26後尚須經歷約800 C之說化石夕沈積、約8〇〇艺之熱退火程序、及約1〇5〇0(：之 快速熱氧化程序等3道高溫製程，因此容易造成矽化鎢層 26向外不正常增生（abnormal growth)之缺陷30，尤其當 此缺陷30突出於氮化矽侧壁29時，更易導致M〇s元件短路 〇 睛參閱第5圖’為改善上述現象，習知之複晶矽金屬 閑極G3係在石夕化鎢層表面另形成一非晶矽頂蓋層4〇，例如 在約55〇 °C之製程溫度下，以矽甲烧SiH4為主反應物，並 藉低壓化學氣相沈積（LPCVD)製程產生，其一方面可以補 充發原子予；ε夕化鎢層26a ’另一方面則可以隔離氧氣入侵 並降低應力’避免不正常增生（abnormal growth)之缺陷 (defects) ° 然而’請參閱第6、7圖，其中，第6圖係顯示於矽化 鎢層26之石夕/鎢原子比值χ = 2·8時，其在不同非晶石夕頂蓋層 f度如10埃，30埃，5〇埃，7〇埃下，矽化鎢層應力與製程 溫度之關係曲線圖；而第7圖則係依據第6圖中，不同非晶Page 7 V. Description of the invention (5) 402743 degrees 'with a rapid high temperature oxidation (RT0: rapid thermai oxidation) process' on the silicon substrate 20 and the gate polycrystalline silicon layer 24 and the tungsten silicide layer 26a sidewalls to form a Thin oxide layer 27. Secondly, an insulating sidewall layer 29 is formed on the side wall of the polycrystalline silicon metal gate-G2, such as the silicon nitride layer 28a and the thin oxide layer 27. For example, dichlorosilane methane SiH2C12, ammonia nh3 is the main reactant, and a silicon nitride layer is deposited by a low pressure chemical vapor deposition (LPCVD) process, followed by an etch-back step to form a silicon nitride sidewall layer. . According to the above, after the formation of the tungsten silicide layer 26, it is necessary to undergo three stages of fossil deposition, about 800 ° C thermal annealing process, and about 1050 ° (rapid thermal oxidation process). High temperature process, therefore, it is easy to cause the defect 30 of the tungsten silicide layer 26 to abnormally grow outward, especially when the defect 30 protrudes from the silicon nitride sidewall 29, it is more likely to cause a short circuit of the MOS device. Figure 'To improve the above phenomenon, the conventional polycrystalline silicon metal electrode G3 is formed on the surface of the tungsten tungsten layer with an amorphous silicon cap layer 40, for example, at a process temperature of about 55 ° C, silicon is used. Sintered SiH4 is the main reactant and is produced by the low pressure chemical vapor deposition (LPCVD) process. On the one hand, it can supplement the atomic emission; on the other hand, the tungsten tungsten layer 26a can isolate the oxygen invasion and reduce the stress. Defects of abnormal growth ° However, 'Please refer to Figures 6 and 7, where Figure 6 shows the stone / tungsten atomic ratio χ = 2 · 8 of the tungsten silicide layer 26. F degrees of different capstones such as 10 angstroms, 30 angstroms and 50 angstroms Under 7〇 Å, and the tungsten silicide layer is a graph showing the relationship between stress temperature of the process; and FIG. 7 of the system according to FIG. 6, the different amorphous
第8頁Page 8
玉'發明_⑹ 4Q214S 石夕頂蓋層厚度如10埃，30埃，50诠， 元件良率。 疾50埃，70埃下所測得之MOS.. *前述第6、7圖可知，當石夕化鎢層26之 值χ=2.8，而非晶矽頂蓋層厚度為ίο埃時，由於： :大雜因此良率不細，而當非晶J蓋 ί 著？低’但良率反趨下降，在本實施例之 ^下，，、有在非晶矽頂蓋層厚度為30至5〇埃之間 工=到8。%以上’且非晶石夕頂蓋層厚度為時良 率间於非晶矽頂蓋層厚度為30埃時。 艮 蓋声、分析發化鶴層26之梦/鎢原子比值x與非晶發頂 同^曰石夕了頁，之關係’請參閱第^至^圖，其係顯示在不 定矽/BB鎮屌/層沈積時間了如0秒/15秒/30秒下’具有既 度之關係曲:圖值如^ P2 8由前而述第8&圖可知’當石夕化鶴層26之石夕/嫣原子比值 據特性曲甲燒（SiH4)為主要氣體並進行沈積時，依 穩定.在沈積時間為約30秒時，其應力變化較為 比值X-2 ^則述第8b圖可知，當矽化鎢層26之矽/鎢原子 ，依據特味也而以石夕甲烧（SiH4)為主要氣體並進行沈積時 較為ϊί 線可知，在沈積時間為15秒時’其應力變化白 /鶬原早V同理’由前述第8C圖可知，當石夕化鶴層26之矽 沈積時，仿值ίΓ2.3，而以矽甲烷（SiH4)為主要氣體並進行 應力變化特性曲線可知在沈積時間為15秒左右時，其 為穩定；而在第8a至第8c圖中’若依據未沈積Jade 'invention_⑹ 4Q214S The thickness of the top cover of Shi Xi is 10 Angstroms, 30 Angstroms, 50 Interpreters, and the yield of the components. MOS measured at 50 angstroms and 70 angstroms. * As shown in Figures 6 and 7 above, when the value of the tungsten tungsten layer 26 is χ = 2.8 and the thickness of the amorphous silicon cap layer is ίο, :: Big miscellaneous yield is not fine, and when amorphous J covers? Low ', but the yield decreases in the opposite direction. In this embodiment, the thickness of the amorphous silicon cap layer is between 30 and 50 angstroms. % 'And the amorphous silicon capping layer has a thickness of about 30 angstroms when the amorphous silicon capping layer has a thickness of 30 angstroms. For the sound analysis, the analysis of the dream / tungsten atomic ratio x of the fascinating crane layer 26 is the same as that of the amorphous hair. The relationship is shown in the figures ^ to ^, and it is shown in the indefinite silicon / BB town屌 / layer deposition time such as 0 seconds / 15 seconds / 30 seconds 'has a relationship relationship of the past: the map value is as ^ P2 8 from the previous description 8 & the picture can be seen' Dangshixi Huahe layer 26 of Shixi / Yan atomic ratio according to the characteristics of trimethyl sintering (SiH4) as the main gas and deposition, it is stable. When the deposition time is about 30 seconds, its stress change is more than the ratio X-2 ^ Figure 8b can be seen that when silicified The silicon / tungsten atom of the tungsten layer 26 is based on the special flavor and is mainly deposited with SiX4 (SiH4) as the main gas. It can be seen that when the deposition time is 15 seconds, the stress change is white / Ebara. The same principle of “V” can be seen from the aforementioned FIG. 8C. When the silicon of the Shixi Chemical Crane Layer 26 was deposited, the imitation value was ΓΓ2.3, and the stress variation characteristic curve was taken with silicon methane (SiH4) as the main gas. About 15 seconds, it is stable; while in Figures 8a to 8c,
第9頁 五、發明說明（7) 非晶石夕頂蓋層之特性曲線（0秒），其應力變化最大 請參閱第9圖，其為依據第6至第8圖之關係^在碁‘ <狀態下’非晶石夕頂蓋層厚度與矽化鎢層之梦/鶴原^^ 值之關係曲線圖，其中，非晶石夕頂蓋層 ’、 ^ ^ ^ ,Ε „ M , ,. t /Λ ^ ^ ^ ^ 值在2 化鎢層之矽/鎢原子比 至50埃 的範圍時，非晶Μ蓋層厚度之範圍約在15 鎮原ΐ::頂η::度係依據發化鎢層之梦/ 層向外不正常掩生(ab藉1由本發明之製哼可避免矽化鎢 本發明 者’其能由各種具恰當： 於實施例所引述 本發：；結構空間亦不限於實施置換，且 雖然本發明ρ ,、, k只死•椚W用之尺寸大小。 以限定本發明，任二，佳實施例揭露如上，然其並非用 神和範圍内，當可if各此技藝者’在不脫離本發明之精 護範圍當視後附之申i 13與潤* ’因此本發明之保 甲明專利範圍所界定者為準。 第10頁Page 9 V. Description of the invention (7) The characteristic curve (0 seconds) of the top cover layer of the amorphous stone. For the maximum stress change, please refer to Figure 9, which is based on the relationship between Figures 6 to 8 ^ Zai ' < The graph of the relationship between the thickness of the amorphous cap and the tungsten silicide layer dream / Heyuan ^^ in the state, in which the amorphous cap and cap layer ', ^ ^ ^, Ε M,,. When the value of t / Λ ^ ^ ^ ^ is in the range of the silicon / tungsten atomic ratio of the tungsten carbide layer to 50 Angstroms, the thickness of the amorphous M cap layer is about 15 The dream of the tungsten carbide layer / the layer is not normally hidden outwards (ab borrowed 1 by the system of the present invention to avoid tungsten silicides. The inventor's can be varied from a variety of appropriate: Quoted in the embodiment of the present invention: the structure space is not It is limited to the implementation of the replacement, and although the present invention ρ ,,, and k are only used to determine the size of the invention. To limit the present invention, any two, the preferred embodiment is disclosed as above, but it is not used within the scope and scope. This artist 'will not deviate from the scope of the present invention as the attached application i 13 and Run *'. Therefore, the scope of the invention's Bao Jiaming patent scope shall prevail. Page 10