US20180151585A1 - Method for manufacturing embedded non-volatile memory - Google Patents

Method for manufacturing embedded non-volatile memory Download PDF

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US20180151585A1
US20180151585A1 US15/396,886 US201715396886A US2018151585A1 US 20180151585 A1 US20180151585 A1 US 20180151585A1 US 201715396886 A US201715396886 A US 201715396886A US 2018151585 A1 US2018151585 A1 US 2018151585A1
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forming
device structure
oxide layer
region
gate
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US9997527B1 (en
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Cheng-Bo Shu
Tsung-Yu Yang
Chung-Jen Huang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Definitions

  • IC semiconductor integrated circuit
  • FIG. 1A through FIG. 1O are schematic cross-sectional views of intermediate stages showing a method for manufacturing a semiconductor device in accordance with various embodiments.
  • FIG. 2 is a flow chart of a method for manufacturing a semiconductor device in accordance with various embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • the term “one” or “the” of the single form may also represent the plural form.
  • the terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy.
  • the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • the 1.5 T ESF3 memory is formed with a polysilicon storage by using a logic first process, i.e. a logic well is formed before a non-volatile memory (NVM) process.
  • the logic well is impacted by the subsequent non-volatile memory process, and resulting in a logic device shift.
  • the 1.5 T ESF3 memory is formed by using a logic last process, i.e. a logic well is formed after a non-volatile memory process, such that the shift of the logic device is decreased.
  • an implantation operation of a low voltage well of a low voltage device is performed through a gate oxide layer of a high voltage device, such that an implant profile of the low voltage well is affected, and resulting in the low voltage device shift.
  • the applying of the polysilicon storage induces a triple polysilicon process, and thus increasing complex of the process of manufacturing the 1.5 T ESF3 memory.
  • Embodiments of the present disclosure are directed to providing a method for manufacturing the semiconductor device, in which after a logic well of a logic device and a high voltage well of a high voltage device are formed, dummy structures are formed to cover the logic well and the high voltage well as device structures are formed, such that the logic well and the high voltage well can be prevented by the dummy structures during subsequent high temperature processes, thereby greatly decreasing shift of the logic device and the high voltage device.
  • an oxide/nitride/oxide (ONO) structure is formed as a trap storage structure of each of device structures, the ONO trap storage structure is thinner than a polysilicon floating gate of a conventional memory, and a control gate of the device structure can be directly disposed on the ONO trap storage structure, such that the thickness of the device structure is reduced.
  • ONO trap storage structure a triple polysilicon process can be omitted.
  • each of the device structures has a lower structure topology which is close to that of a logic gate, such that the subsequent patterning processes of the semiconductor device are relatively easy, thereby simplifying a process for manufacturing the semiconductor device and integration of the processes of the semiconductor device and other device, and decreasing process time and reducing process cost.
  • FIG. 1A through FIG. 1O are schematic cross-sectional views of intermediate stages showing a method for manufacturing a semiconductor device in accordance with various embodiments.
  • a substrate 100 is provided.
  • the substrate 100 may be a semiconductor substrate.
  • the substrate 100 may be composed of a single-crystalline semiconductor material or a compound semiconductor material.
  • silicon or germanium may be used as a material forming the substrate 100 .
  • the substrate 100 may be a silicon on insulator substrate.
  • various isolation structures 102 a - 102 d are formed in the substrate 100 .
  • a hard mask (not shown) is formed to cover the substrate 100 , the hard mask is then patterned by a photolithography process and an etch process, and portions of the substrate 100 , which are not covered by the patterned hard mask, are removed to form various trenches in the substrate 100 , an isolation material is formed to fill the trenches and to cover the hard mask layer, and then the hard mask and the isolation material over the hard mask layer are removed to form the isolation structures 102 a - 102 d in the substrate 100 .
  • the isolation structures 102 a - 102 d formed in the substrate 100 at least define a first region 104 a , a second region 104 b , and a third region 104 c , in which the first region 104 a is located between the isolation structures 102 b and 102 c , the second region 104 b is located between the isolation structures 102 a and 102 b , and the third region 104 c is located between the isolation structures 102 c and 102 d .
  • the isolation structures 102 a , 102 b , 102 c , and 102 d may be shallow trench isolation (STI) structures.
  • the isolation material may be formed by using a high density plasma chemical vapor deposition (HDP CVD) method.
  • a pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method.
  • a logic well 108 is formed in the substrate 100 in the second region 104 b by performing an implantation process on the second region 104 b .
  • a high voltage well 110 is formed in the substrate 100 in the third region 104 c by performing an implantation process on the third region 104 c .
  • the logic well 108 and the high voltage well 110 are formed using dopants, such as boron and phosphorous.
  • the portion of the pad oxide layer 106 in the first region 104 a is removed by using a photolithography method and an etching method.
  • the remaining portions of the pad oxide layer 106 cover the second region 104 b and the third region 104 c , as shown in FIG. 1A .
  • an oxide layer 112 , a nitride layer 114 , and an oxide layer 116 are formed to cover the substrate 100 in sequence to form an ONO structure.
  • the oxide layer 112 , the nitride layer 114 , and the oxide layer 116 may be formed by using a deposition method, such as a chemical vapor deposition (CVD) method.
  • the oxide layers 112 and 116 may be formed from silicon oxide, and the nitride layer 114 may be formed from silicon nitride.
  • the oxide layer 112 is formed to have a thickness ranging from about 10 angstrom to about 20 angstrom
  • the nitride layer 114 is formed to have a thickness ranging from about 100 angstrom to about 150 angstrom
  • the oxide layer 116 is formed to have a thickness ranging from about 30 angstrom to about 50 angstrom.
  • a control gate layer 118 is formed to cover the oxide layer 116 by using a deposition method, such as a chemical vapor deposition method.
  • the control gate layer 118 may be formed from polysilicon.
  • the control gate layer 118 is directly deposed on the oxide layer 116 .
  • a nitride layer 120 , an oxide layer 122 , and a nitride layer 124 are formed to cover the control gate layer 118 in sequence to form an NON structure.
  • the nitride layer 120 , the oxide layer 122 , and the nitride layer 124 form a cap structure.
  • the nitride layer 120 , the oxide layer 122 , and the nitride layer 124 may be formed by using a deposition method, such as a chemical vapor deposition method.
  • the nitride layers 120 and 124 may be formed from silicon nitride, and the oxide layer 122 may be formed from silicon oxide.
  • a portion of the nitride layer 124 , a portion of the oxide layer 122 , a portion of the nitride layer 120 , and a portion of the control gate layer 118 are removed by using a photolithography method and an etching method.
  • the remaining portions of the control gate layer 118 disposed on the first region 104 a form control gates 118 a and 118 b respectively, and the remaining portions of the control gate layer 118 disposed on the second region 104 b and the third region 104 c form control gates 118 c and 118 d respectively.
  • the remaining portion 120 a of the nitride layer 120 , the remaining portion 122 a of the oxide layer 122 , and the remaining portion 124 a of the nitride layer 124 are stacked on the control gate 118 a to form a stacked structure 126 a with the control gate 118 a .
  • the remaining portion 120 b of the nitride layer 120 , the remaining portion 122 b of the oxide layer 122 , and the remaining portion 124 b of the nitride layer 124 are stacked on the control gate 118 b to form a stacked structure 126 b with the control gate 118 b .
  • the remaining portion 120 c of the nitride layer 120 , the remaining portion 122 c of the oxide layer 122 , and the remaining portion 124 c of the nitride layer 124 are stacked on the control gate 118 c to form a stacked structure 126 c with the control gate 118 c .
  • the remaining portion 120 d of the nitride layer 120 , the remaining portion 122 d of the oxide layer 122 , and the remaining portion 124 d of the nitride layer 124 are stacked on the control gate 118 d to form a stacked structure 126 d with the control gate 118 d.
  • spacers 128 a - 128 d are respectively formed on sidewalls of the stacked structures 126 a - 126 d to complete device structures 130 a - 130 d , in which the device structures 130 a and 130 b are located on the first region 104 a , the device structure 130 c is located on the second region 104 b and covers the logic well 108 , and the device structure 130 d is located on the second region 104 c and covers the high voltage well 110 .
  • the device structure 130 a - 130 d are separated from each other.
  • each of the spacers 128 a - 128 d is formed to include an oxide layer 132 , a nitride layer 134 , and an oxide layer 136 stacked on the sidewall of the respective stacked structure 126 a , 126 b , 126 c or 126 d in sequence.
  • forming the spacers 128 a - 128 d includes blanketly forming the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 in sequence to cover the stacked structures 126 a - 126 d and the oxide layer 116 , and etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 to remove a portion of the oxide layer 132 , a portion of the nitride layer 134 , and a portion of the oxide layer 136 , so as to form the spacers 128 a - 128 d on the sidewalls of the stacked structure 126 a - 126 d respectively.
  • the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 may be formed by a deposition method, such as a chemical vapor deposition method. Etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 may be performed by using an anisotropic etching method.
  • etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 includes etching the oxide layer 116 and the nitride layer 114 .
  • the portion 112 a of the oxide layer 112 , the remaining portion 114 a of the nitride layer 114 , and the remaining portion 116 a of the oxide layer 116 stacked in sequence form a trap storage structure 138 a .
  • the portion 112 b of the oxide layer 112 , the remaining portion 114 b of the nitride layer 114 , and the remaining portion 116 b of the oxide layer 116 stacked in sequence form a trap storage structure 138 b .
  • the portion 112 c of the oxide layer 112 , the remaining portion 114 c of the nitride layer 114 , and the remaining portion 116 c of the oxide layer 116 stacked in sequence form a trap storage structure 138 c .
  • the portion 112 d of the oxide layer 112 , the remaining portion 114 d of the nitride layer 114 , and the remaining portion 116 d of the oxide layer 116 stacked in sequence form a trap storage structure 138 d .
  • the device structures 130 a - 130 d further respectively include the trap storage structures 138 a - 138 d .
  • each of the device structures 130 c and 130 d further includes the pad oxide layer 106 .
  • the device structures 130 c and 130 d are dummy device structures, and will be removed in the subsequent process.
  • an implantation process 140 may be performed on the substrate 100 through the oxide layer 112 by using the device structures 130 a - 130 d as mask structures, so as to form a word line threshold voltage (Vt) 142 , a source side junction 144 , and a word line Vt 146 in the first region 104 a .
  • the word line Vt 142 and the word line Vt 146 are respectively adjacent to the device structures 130 a and 130 b
  • the source side junction 144 is located between the device structure 130 a and 130 b
  • the source side junction 144 is opposite to the word line Vt 142 and the word line Vt 146 respectively.
  • the implantation process 140 may be performed using dopants, such as boron and phosphorous.
  • gap oxide layers 148 a and 148 b are formed on sidewalls of the spacers 128 a respectively, gap oxide layers 150 a and 150 b are formed on sidewalls of the spacers 128 b respectively, gap oxide layers 152 are formed on sidewalls of the spacers 128 c respectively, and gap oxide layers 154 are formed on sidewalls of the spacers 128 d respectively.
  • the gap oxide layer 148 b and 150 b are disposed on the source side junction 144 .
  • forming the gap oxide layers 148 a , 148 b , 150 a , 150 b , 152 , and 154 includes forming an oxide layer to cover the device structures 130 a - 130 d and the oxide layer 112 on the substrate 100 , and etching the oxide layer to remove a portion of the oxide layer to form the gap oxide layers 148 a , 148 b , 150 a , 150 b , 152 , and 154 .
  • the oxide layer may be formed from silicon oxide, and the oxide layer may be formed by a high temperature oxidation (HTO) method. Etching the oxide layer may be performed by an anisotropic etching method.
  • HTO high temperature oxidation
  • a rapid thermal annealing (RTA) process may be performed on the oxide layer between forming the oxide layer and etching the oxide layer.
  • the device structure 130 d and the gap oxide layers 154 are removed, as shown in FIG. 1G .
  • the gap oxide layers 154 may be firstly removed.
  • the nitride layer 124 d , the oxide layer 122 d , and the nitride layer 120 d are removed by an etching method.
  • the control gate 118 d , the oxide layer 116 , the nitride layer 114 are removed sequentially by an etching method.
  • the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • a first gate oxide layer 156 is formed to cover the substrate 100 .
  • the first gate oxide layer 156 may be formed to further cover the device structures 130 a - 130 c .
  • the first gate oxide layer 156 may be formed to include a rapid thermal oxide (RTO) layer and a high temperature oxide layer on the rapid thermal oxide layer.
  • RTO rapid thermal oxide
  • the gap oxide layers 148 b and 150 b , located on the source side junction 144 , and the gap oxide layers 152 located on the sidewalls of the device structure 130 c are removed.
  • the gap oxide layers 148 b , 150 b and 152 may be removed by using a photolithography method and an etching method.
  • a source line junction 158 is formed in the source side junction 144 by performing an implantation process on the source side junction 144 .
  • the first gate oxide layer 156 on the source line junction 158 is removed by an etching method, as shown in FIG. 1H .
  • a rapid thermal annealing process may be optionally performed on the first gate oxide layer 156 and the source line junction 158 .
  • the device structure 130 c and the first gate oxide layer 156 overlying the device structure 130 c are removed.
  • the first gate oxide layer 156 overlying the device structure 130 c is removed by a dip method.
  • the nitride layer 124 c , the oxide layer 122 c , and the nitride layer 120 c are removed by an etching method, then the control gate 118 c , the oxide layer 116 , the nitride layer 114 are removed sequentially by an etching method, and then the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • a second gate oxide layer 160 may be formed on the substrate 100 and the first gate oxide layer 156 .
  • the second oxide layer 160 may be referred to an IO oxide layer.
  • an operation of forming the second gate oxide layer 160 is performed by a logic dual gate oxide process, and a rapid thermal oxide layer of the second gate oxide layer 160 is firstly formed, and then a high temperature oxide layer of the second gate oxide layer 160 is formed on the rapid thermal oxide layer.
  • a rapid thermal annealing process may be optionally performed on the second gate oxide layer 160 .
  • portions of the second gate oxide layer 160 and portions of the first gate oxide layer 156 on the first region 104 a , the second region 104 b , and a portion of the isolation structure 102 c are removed by, for example, a photolithography method, and an etching method or a dip method. Then, referring to FIG. 1J again, a third gate oxide layer 161 is formed to cover the first region 104 a , the second region 104 b , and the third region 104 c .
  • the third gate oxide layer 161 may be referred to a core oxide layer.
  • the word line Vt 142 , the word line Vt 146 , the device structures 130 a and 130 b , the source line junction 158 , the logic well 108 , the isolation structure 102 b , and the portion of the isolation structure 102 c are exposed.
  • the third gate oxide layer 161 is formed to cover the remaining portions of the second gate oxide layer 160 , the word line Vt 142 , the word line Vt 146 , the device structures 130 a and 130 b , the source line junction 158 , the logic well 108 , the isolation structure 102 b , and the portion of the isolation structure 102 c .
  • the second region 104 b has the second gate oxide layer 160 and the third gate oxide layer 161 sequentially covering thereon.
  • the device including the second gate oxide layer 160 may be referred to a medium voltage (MV) device.
  • MV medium voltage
  • a conductive layer 162 is formed to cover the third gate oxide layer 161 , the device structures 130 a and 130 b , and the gap oxide layers 148 a and 150 a .
  • the conductive layer 162 may be formed from polysilicon, and may be formed by using a deposition method, such as a chemical vapor deposition method.
  • a portion of the conductive layer 162 over the device structures 130 a and 130 b , the spacers 128 a and 128 b , and the gap oxide layers 148 a and 150 a is removed by using a photolithography method and an etching method.
  • portions of the nitride layers 124 a and 124 b , portions of the spacers 128 a and 128 b , and portions of the gate oxide layers 148 a and 150 a are removed.
  • the conductive layer 162 is further etched to form word lines 164 and 166 .
  • the word line 164 is disposed on the third gate oxide layer 161 over the word line Vt 142 and on one of the spacers 128 a of the device structure 130 a , in which the gap oxide layer 148 a is located between the word line 164 and the spacer 128 a ; and the word line 166 is disposed on the third gate oxide layer 161 over the word line Vt 146 and on one of the spacers 128 b of the device structure 130 b , in which the gap oxide layer 150 a is located between the word line 166 and the spacer 128 b .
  • the word lines 164 and 166 are respectively adjacent to the device structures 130 a and 130 b .
  • forming of the word lines 164 and 166 further include forming a gate 168 of the logic device 170 on the logic well 108 and a gate 172 of the high voltage device 174 on the high voltage well 110 .
  • the logic device 170 mainly includes the gate 168 and the third gate oxide layer 161
  • the high voltage device 174 mainly includes the gate 172 , the first gate oxide layer 156 , the second gate oxide layer 160 , and the third gate oxide layer 161 .
  • the device structures 130 c and 130 d can block the logic well 108 and the high voltage well 110 from the implantation process 140 . Furthermore, as shown in FIG. 1F , the logic well 108 and the high voltage well 110 can be prevented by the device structures 130 c and 130 d during the high temperature process (i.e. the rapid thermal annealing process of the gap oxide layers 148 a , 148 b , 150 a , 150 b , 152 , and 154 ). As shown in FIG. 1G , the device structures 130 c can further block the logic well 108 from rapid thermal annealing process of the first gate oxide layer 156 . Therefore, with the device structures 130 c and 130 d , the logic well 108 and the high voltage well 110 are well protected, thereby decreasing shift of the logic device 170 and the high voltage device 174 .
  • the high temperature process i.e. the rapid thermal annealing process of the gap oxide layers 148 a , 148 b , 150 a , 150
  • various lightly doped drains 176 a - 176 g are formed in the substrate 100 by using an implantation method.
  • the lightly doped drains 176 a and 176 b are formed in the logic well 108 at opposite sides of the gate 168 and adjacent to the gate 168
  • the lightly doped drain 176 c is formed in the word line Vt 142 adjacent the word line 164
  • the lightly doped drain 176 d is formed in the word line Vt 146 adjacent the word line 166
  • the lightly doped drains 176 e and 176 f are formed in the high voltage well 110 at opposite sides of the gate 172 and adjacent to the gate 172
  • the lightly doped drain 176 g is formed in the source line junction 158 .
  • various spacers 178 a - 178 h are formed on the third gate oxide layer 161 .
  • the spacers 178 a and 178 b are formed on sidewalls of the gate 168
  • the spacer 178 c is formed on a sidewall of the word line 164
  • the spacer 178 d is formed on a sidewall of the device structure 130 a and over the lightly doped drain 176 g
  • the spacer 178 e is formed on a sidewall of the device structure 130 b and over the lightly doped drain 176 g
  • the spacer 178 f is formed on a sidewall of the word line 166
  • the spacers 178 g and 178 h are formed on sidewalls of the gate 172 .
  • an operation of forming the spacers 178 a - 178 h includes blanketly forming a spacer material layer (not shown) to cover the third gate oxide layer 161 , the gates 168 and 172 , the device structures 130 a and 130 b , and the word lines 164 and 166 , and performing an etching back process on the spacer material layer to remove a portion of the spacer material layer, a portion of the third gate oxide layer 161 , a portion of the second gate oxide layer 160 , and a portion of the first gate oxide layer 156 , so as to form the spacers 178 a - 178 h.
  • a source/drain (S/D) implantation process is performed on the substrate 100 to form S/D regions 180 a - 180 g in the substrate 100 .
  • the S/D regions 180 a - 180 g are respectively formed in the lightly doped drains 176 a - 176 g.
  • a silicide process is performed on the S/D regions 180 a - 180 g and the word lines 164 and 166 , to form various silicide regions 182 a - 182 g , so as to substantially complete a semiconductor device 184 .
  • the silicide regions 182 a - 182 k are respectively formed in the S/D regions 180 a - 180 g , the gate 168 , the word line 164 , the word line 166 , and the gate 172 .
  • the semiconductor device 184 may be a 1.5 T third generation embedded super-flash (ESF3) with an ONO trap storage structure.
  • the trap storage structures 138 a and 138 b are ONO structures, such that each of the trap storage structures 138 a and 138 b is thinner than a conventional polysilicon floating gate, and the control gates 118 a and 118 b can be directly stacked on the trap storage structures 138 a and 138 b .
  • each of the device structures 130 a and 130 b has a lower structure topology which is close to that of other devices, such that the subsequent patterning processes of the semiconductor device 184 are relatively easy, thereby simplifying a process for manufacturing the semiconductor device 184 and integration of the processes of the semiconductor device 184 and the other devices, and decreasing process time and reducing process cost.
  • the semiconductor device 184 can be programmed using a source side injection (SSI) programming method, and can be erased using a Fowler-Nordheim (FN) erase method, thereby decreasing power consumption of the semiconductor device 184 .
  • SSI source side injection
  • FN Fowler-Nordheim
  • the semiconductor device 184 can be programmed by a SSI programming method, the programming operation of the semiconductor device 184 can be performed by a byte mode.
  • FIG. 2 is a flow chart of a method for manufacturing a semiconductor device in accordance with various embodiments.
  • the method begins at operation 200 , where a substrate 100 is provided.
  • the substrate 100 may be a semiconductor substrate, such as a crystalline semiconductor substrate or a compound semiconductor substrate.
  • silicon or germanium may be used as a material forming the substrate 100 .
  • the substrate 100 may be a silicon on insulator substrate.
  • various isolation structures 102 a - 102 d are formed in the substrate 100 to at least define a first region 104 a , a second region 104 b , and a third region 104 c , in which the first region 104 a is located between the isolation structures 102 b and 102 c , the second region 104 b is located between the isolation structures 102 a and 102 b , and the third region 104 c is located between the isolation structures 102 c and 102 d .
  • a hard mask (not shown) is formed to cover the substrate 100 , the hard mask is then patterned by a photolithography process and an etch process, and portions of the substrate 100 , which are not covered by the patterned hard mask, are removed to form various trenches in the substrate 100 , an isolation material is formed to fill the trenches and to cover the hard mask layer, and then the hard mask and the isolation material over the hard mask layer are removed to form the isolation structures 102 a - 102 d in the substrate 100 .
  • the isolation structures 102 a - 102 d may be shallow trench isolation structures.
  • the isolation material may be formed by using a high density plasma chemical vapor deposition method.
  • a pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method.
  • a logic well 108 is formed in the substrate 100 in the second region 104 b by performing an implantation process on the second region 104 b .
  • a high voltage well 110 is formed in the substrate 100 in the third region 104 c by performing an implantation process on the third region 104 c .
  • the logic well 108 and the high voltage well 110 are formed using dopants, such as boron and phosphorous.
  • the portion of the pad oxide layer 106 in the first region 104 a is removed by using a photolithography method and an etching method. The remaining portions of the pad oxide layer 106 cover the second region 104 b and the third region 104 c.
  • device structures 130 a and 130 b are formed on the first region 104 a
  • a device structure 130 c is formed on the second region 104 b and covering the logic well 108
  • a device structure 130 d is formed on the third region 104 c and covering the high voltage well 110 .
  • an oxide layer 112 , a nitride layer 114 , and an oxide layer 116 are formed to cover the substrate 100 in sequence to form an ONO structure.
  • the oxide layer 112 , the nitride layer 114 , and the oxide layer 116 may be formed by using a deposition method.
  • a control gate layer 118 is formed to cover the oxide layer 116 by using a deposition method.
  • the control gate layer 118 is directly deposed on the oxide layer 116 .
  • a nitride layer 120 , an oxide layer 122 , and a nitride layer 124 are formed to cover the control gate layer 118 in sequence to form an NON structure.
  • the nitride layer 120 , the oxide layer 122 , and the nitride layer 124 may be formed by using a deposition method.
  • a portion of the nitride layer 124 , a portion of the oxide layer 122 , a portion of the nitride layer 120 , and a portion of the control gate layer 118 are removed by using a photolithography method and an etching method.
  • the remaining portions of the control gate layer 118 disposed on the first region 104 a form control gates 118 a and 118 b respectively, and the remaining portions of the control gate layer 118 disposed on the second region 104 b and the third region 104 c form control gates 118 c and 118 d respectively.
  • the remaining portion 120 a of the nitride layer 120 , the remaining portion 122 a of the oxide layer 122 , and the remaining portion 124 a of the nitride layer 124 are stacked on the control gate 118 a to form a stacked structure 126 a with the control gate 118 a .
  • the remaining portion 120 b of the nitride layer 120 , the remaining portion 122 b of the oxide layer 122 , and the remaining portion 124 b of the nitride layer 124 are stacked on the control gate 118 b to form a stacked structure 126 b with the control gate 118 b .
  • the remaining portion 120 c of the nitride layer 120 , the remaining portion 122 c of the oxide layer 122 , and the remaining portion 124 c of the nitride layer 124 are stacked on the control gate 118 c to form a stacked structure 126 c with the control gate 118 c .
  • the remaining portion 120 d of the nitride layer 120 , the remaining portion 122 d of the oxide layer 122 , and the remaining portion 124 d of the nitride layer 124 are stacked on the control gate 118 d to form a stacked structure 126 d with the control gate 118 d.
  • spacers 128 a - 128 d are respectively formed on sidewalls of the stacked structures 126 a - 126 d to complete device structures 130 a - 130 d , in which the device structures 130 a - 130 d are separated from each other.
  • each of the spacers 128 a - 128 d is formed to include an oxide layer 132 , a nitride layer 134 , and an oxide layer 136 stacked on the sidewall of the respective stacked structure 126 a , 126 b , 126 c or 126 d in sequence.
  • forming the spacers 128 a - 128 d includes blanketly forming the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 in sequence to cover the stacked structures 126 a - 126 d and the oxide layer 116 , and etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 to remove a portion of the oxide layer 132 , a portion of the nitride layer 134 , and a portion of the oxide layer 136 , so as to form the spacers 128 a - 128 d on the sidewalls of the stacked structure 126 a - 126 d respectively.
  • the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 may be formed by a deposition method. Etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 may be performed by using an anisotropic etching method.
  • etching the oxide layer 132 , the nitride layer 134 , and the oxide layer 136 includes etching the oxide layer 116 and the nitride layer 114 .
  • the portion 112 a of the oxide layer 112 , the remaining portion 114 a of the nitride layer 114 , and the remaining portion 116 a of the oxide layer 116 stacked in sequence form a trap storage structure 138 a .
  • the portion 112 b of the oxide layer 112 , the remaining portion 114 b of the nitride layer 114 , and the remaining portion 116 b of the oxide layer 116 stacked in sequence form a trap storage structure 138 b .
  • the portion 112 c of the oxide layer 112 , the remaining portion 114 c of the nitride layer 114 , and the remaining portion 116 c of the oxide layer 116 stacked in sequence form a trap storage structure 138 c .
  • the portion 112 d of the oxide layer 112 , the remaining portion 114 d of the nitride layer 114 , and the remaining portion 116 d of the oxide layer 116 stacked in sequence form a trap storage structure 138 d .
  • the device structures 130 a - 130 d further respectively include the trap storage structures 138 a - 138 d .
  • each of the device structures 130 c and 130 d further includes the pad oxide layer 106 .
  • an implantation process 140 may be performed on the substrate 100 through the oxide layer 112 by using the device structures 130 a - 130 d as mask structures, so as to form a word line Vt 142 , a source side junction 144 , and a word line Vt 146 in the first region 104 a .
  • the word line Vt 142 and the word line Vt 146 are respectively adjacent to the device structures 130 a and 130 b , and the source side junction 144 is located between the device structure 130 a and 130 b , and the source side junction 144 is opposite to the word line Vt 142 and the word line Vt 146 respectively.
  • gap oxide layers 148 a and 148 b may be formed on sidewalls of the spacers 128 a respectively
  • gap oxide layers 150 a and 150 b may be formed on sidewalls of the spacers 128 b respectively
  • gap oxide layers 152 may be formed on sidewalls of the spacers 128 c respectively
  • gap oxide layers 154 may be formed on sidewalls of the spacers 128 d respectively.
  • the gap oxide layer 148 b and 150 b are disposed on the source side junction 144 .
  • forming the gap oxide layers 148 a , 148 b , 150 a , 150 b , 152 , and 154 includes forming an oxide layer to cover the device structures 130 a - 130 d and the oxide layer 112 on the substrate 100 , and etching the oxide layer to remove a portion of the oxide layer to form the gap oxide layers 148 a , 148 b , 150 a , 150 b , 152 , and 154 .
  • the oxide layer may be formed by a high temperature oxidation method. Etching the oxide layer may be performed by an anisotropic etching method.
  • a rapid thermal annealing process may be performed on the oxide layer between forming the oxide layer and etching the oxide layer.
  • the device structure 130 d and the gap oxide layers 154 are removed.
  • the gap oxide layers 154 may be firstly removed.
  • the nitride layer 124 d , the oxide layer 122 d , and the nitride layer 120 d are removed by an etching method.
  • the control gate 118 d , the oxide layer 116 , the nitride layer 114 are removed sequentially by an etching method.
  • the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • a first gate oxide layer 156 is formed to cover the substrate 100 .
  • the first gate oxide layer 156 may be formed to further cover the device structures 130 a - 130 c.
  • a source line junction 158 is formed in the source side junction 144 .
  • the gap oxide layers 148 b and 150 b located on the source side junction 144 , and the gap oxide layers 152 located on the sidewalls of the device structure 130 c are removed by using a photolithography method and an etching method.
  • the source line junction 158 is formed in the source side junction 144 by performing an implantation process on the source side junction 144 .
  • the first gate oxide layer 156 on the source line junction 158 is removed by an etching method.
  • a rapid thermal annealing process may be optionally performed on the first gate oxide layer 156 and source line junction 158 .
  • the device structure 130 c and the first gate oxide layer 156 overlying the device structure 130 c are removed.
  • the first gate oxide layer 156 overlying the device structure 130 c is removed by a dip method.
  • the nitride layer 124 c , the oxide layer 122 c , and the nitride layer 120 c are removed by an etching method.
  • the control gate 118 c , the oxide layer 116 , the nitride layer 114 are removed sequentially by an etching method.
  • the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • a second gate oxide layer 160 may be formed on the substrate 100 and the first gate oxide layer 156 .
  • an operation of forming the second gate oxide layer 160 is performed by a logic dual gate oxide process, and a rapid thermal oxide layer of the second gate oxide layer 160 is firstly formed, and then a high temperature oxide layer of the second gate oxide layer 160 is formed on the rapid thermal oxide layer.
  • a rapid thermal annealing process may be optionally performed on the second gate oxide layer 160 .
  • portions of the second gate oxide layer 160 and the first gate oxide layer 156 on the first region 104 a , the second region 104 b , and a portion of the isolation structure 102 c are removed by, for example, a photolithography method, and an etching method or a dip method.
  • the word line Vt 142 , the word line Vt 146 , the device structures 130 a and 130 b , the source line junction 158 , the logic well 108 , the isolation structure 102 b , and the portion of the isolation structure 102 c are exposed. Then, referring to FIG.
  • a third gate oxide layer 161 is formed to cover the remaining portions of the second gate oxide layer 160 , the word line Vt 142 , the word line Vt 146 , the device structures 130 a and 130 b , the source line junction 158 , the logic well 108 , the isolation structure 102 b , and the portion of the isolation structure 102 c .
  • the second region 104 b has the second gate oxide layer 160 and the third gate oxide layer 161 sequentially covering thereon.
  • word lines 164 and 166 are formed.
  • a conductive layer 162 is formed to cover the third gate oxide layer 161 , the device structures 130 a and 130 b , and the gap oxide layers 148 a and 150 a , as shown in FIG. 1K .
  • the conductive layer 162 may be formed by using a deposition method. As shown in FIG. 1M
  • a portion of the conductive layer 162 over the device structures 130 a and 130 b , the spacers 128 a and 128 b , and the gap oxide layers 148 a and 150 a is removed by using a photolithography method and an etching method.
  • portions of the nitride layers 124 a and 124 b , portions of the spacers 128 a and 128 b , and portions of the gate oxide layers 148 a and 150 a are removed.
  • the conductive layer 162 is further etched to form the word lines 164 and 166 .
  • the word line 164 is disposed on the third gate oxide layer 161 over the word line Vt 142 and on one of the spacers 128 a of the device structure 130 a , in which the gap oxide layer 148 a is located between the word line 164 and the spacer 128 a .
  • the word line 166 is disposed on the third gate oxide layer 161 over the word line Vt 146 and on one of the spacers 128 b of the device structure 130 b , in which the gap oxide layer 150 a is located between the word line 166 and the spacer 128 b .
  • the word lines 164 and 166 are respectively adjacent to the device structures 130 a and 130 b .
  • forming of the word lines 164 and 166 further include forming a gate 168 of the logic device 170 on the logic well 108 and a gate 172 of the high voltage device 174 on the high voltage well 110 .
  • the logic device 170 mainly includes the gate 168 and the third gate oxide layer 161
  • the high voltage device 174 mainly includes the gate 172 , the first gate oxide layer 156 , the second gate oxide layer 160 , and the third gate oxide layer 161 .
  • lightly doped drains 176 a - 176 g may be optionally formed in the substrate 100 by using an implantation method.
  • the lightly doped drains 176 a and 176 b are formed in the logic well 108 at opposite sides of the gate 168 and adjacent to the gate 168
  • the lightly doped drain 176 c is formed in the word line Vt 142 adjacent the word line 164
  • the lightly doped drain 176 d is formed in the word line Vt 146 adjacent the word line 166
  • the lightly doped drains 176 e and 176 f are formed in the high voltage well 110 at opposite sides of the gate 172 and adjacent to the gate 172
  • the lightly doped drain 176 g is formed in the source line junction 158 .
  • various spacers 178 a - 178 h are formed on the third gate oxide layer 161 .
  • the spacers 178 a and 178 b are formed on sidewalls of the gate 168
  • the spacer 178 c is formed on a sidewall of the word line 164
  • the spacer 178 d is formed on a sidewall of the device structure 130 a and over the lightly doped drain 176 g
  • the spacer 178 e is formed on a sidewall of the device structure 130 b and over the lightly doped drain 176 g
  • the spacer 178 f is formed on a sidewall of the word line 166
  • the spacers 178 g and 178 h are formed on sidewalls of the gate 172 .
  • an operation of forming the spacers 178 a - 178 h includes blanketly forming a spacer material layer to cover the third gate oxide layer 161 , the gates 168 and 172 , the device structures 130 a and 130 b , and the word lines 164 and 166 , and performing an etching back process on the spacer material layer to remove a portion of the spacer material layer, a portion of the third gate oxide layer 161 , a portion of the second gate oxide layer 160 , and a portion of the first gate oxide layer 156 .
  • a S/D implantation process is performed on the substrate 100 to form S/D regions 180 a - 180 g in the substrate 100 .
  • the S/D regions 180 a - 180 g are respectively formed in the lightly doped drains 176 a - 176 g .
  • a silicide process is performed on the S/D regions 180 a - 180 g and the word lines 164 and 166 , to form various silicide regions 182 a - 182 k , so as to substantially complete a semiconductor device 184 .
  • the silicide regions 182 a - 182 k are respectively formed in the S/D regions 180 a - 180 g , the gate 168 , the word line 164 , the word line 166 , and the gate 172 .
  • the present disclosure discloses a method for manufacturing a semiconductor device.
  • various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region.
  • a logic well and a high voltage well are respectively formed in the second region and the third region.
  • a first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well.
  • a first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively.
  • the fourth device structure is removed.
  • a source line junction is formed in the source side junction.
  • the third device structure is removed.
  • a first word line and a second word line are respectively formed on the first word line Vt adjacent to the first device structure and the second word line Vt adjacent to the second device structure.
  • the present disclosure discloses a method for manufacturing a semiconductor device.
  • various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region.
  • a logic well and a high voltage well are respectively formed in the second region and the third region.
  • a first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well.
  • Gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure. The fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed.
  • a first gate oxide layer is formed to cover the substrate.
  • the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed.
  • a source line junction is formed in the substrate between the first device structure and the second device structure.
  • the third device structure is removed.
  • a second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed.
  • a third gate oxide layer is formed to cover the first region, the second region, and the third region.
  • a first word line and a second word line are respectively formed on the gap oxide layer on the first device structure and the gap oxide layer on the second device structure.
  • the present disclosure discloses a method for manufacturing a semiconductor device.
  • various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region.
  • a logic well and a high voltage well are respectively formed in the second region and the third region.
  • a first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well.
  • a trap storage structure is formed on the substrate, a control gate is directly formed on the trap storage structure, a cap structure is formed on the control gate to form a stacked structure, and various spacers are respectively formed on sidewalls of the stacked structure.
  • a first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively.
  • gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure.
  • the fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed.
  • a first gate oxide layer is formed to cover the substrate.
  • the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed.
  • a source line junction is formed in the substrate between the first device structure and the second device structure.
  • the third device structure is removed.
  • a second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed.
  • a third gate oxide layer is formed to cover the first region, the second region, and the third region
  • a first word line is formed on the gap oxide layer on the first device structure
  • a second word line is formed on the gap oxide layer on the second device structure
  • a gate of a high voltage device is formed on the high voltage well
  • a gate of a logic device is formed on the logic well.

Abstract

In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.

Description

    RELATED APPLICATIONS
  • This application claims priority to U.S. Provisional Application Ser. No. 62/426,681, filed Nov. 28, 2016, which is herein incorporated by reference.
    • BACKGROUND
  • The semiconductor integrated circuit (IC) industry has experienced exponential growth over the last few decades. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
  • Super-flash technology has enabled designers to create cost effective and high performance programmable SOC (system on chip) solutions through the use of split-gate flash memory cells. The aggressive scaling of the third generation embedded super-flash (ESF3) memory enables designing flash memories with very high memory array density.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
  • FIG. 1A through FIG. 1O are schematic cross-sectional views of intermediate stages showing a method for manufacturing a semiconductor device in accordance with various embodiments.
  • FIG. 2 is a flow chart of a method for manufacturing a semiconductor device in accordance with various embodiments.
    •  DETAILED DESCRIPTION
  • The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
  • Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • In a typical process for manufacturing a 1.5 T ESF3 memory, the 1.5 T ESF3 memory is formed with a polysilicon storage by using a logic first process, i.e. a logic well is formed before a non-volatile memory (NVM) process. The logic well is impacted by the subsequent non-volatile memory process, and resulting in a logic device shift. In another process for manufacturing a 1.5 T ESF3 memory, the 1.5 T ESF3 memory is formed by using a logic last process, i.e. a logic well is formed after a non-volatile memory process, such that the shift of the logic device is decreased. However, in the logic last process, an implantation operation of a low voltage well of a low voltage device is performed through a gate oxide layer of a high voltage device, such that an implant profile of the low voltage well is affected, and resulting in the low voltage device shift. Moreover, the applying of the polysilicon storage induces a triple polysilicon process, and thus increasing complex of the process of manufacturing the 1.5 T ESF3 memory.
  • Embodiments of the present disclosure are directed to providing a method for manufacturing the semiconductor device, in which after a logic well of a logic device and a high voltage well of a high voltage device are formed, dummy structures are formed to cover the logic well and the high voltage well as device structures are formed, such that the logic well and the high voltage well can be prevented by the dummy structures during subsequent high temperature processes, thereby greatly decreasing shift of the logic device and the high voltage device. Furthermore, an oxide/nitride/oxide (ONO) structure is formed as a trap storage structure of each of device structures, the ONO trap storage structure is thinner than a polysilicon floating gate of a conventional memory, and a control gate of the device structure can be directly disposed on the ONO trap storage structure, such that the thickness of the device structure is reduced. In addition, with the ONO trap storage structure, a triple polysilicon process can be omitted. Thus, compared to the device structure of the conventional memory, each of the device structures has a lower structure topology which is close to that of a logic gate, such that the subsequent patterning processes of the semiconductor device are relatively easy, thereby simplifying a process for manufacturing the semiconductor device and integration of the processes of the semiconductor device and other device, and decreasing process time and reducing process cost.
  • FIG. 1A through FIG. 1O are schematic cross-sectional views of intermediate stages showing a method for manufacturing a semiconductor device in accordance with various embodiments. As shown in FIG. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate. The substrate 100 may be composed of a single-crystalline semiconductor material or a compound semiconductor material. For example, silicon or germanium may be used as a material forming the substrate 100. In certain examples, the substrate 100 may be a silicon on insulator substrate.
  • Referring to FIG. 1A again, various isolation structures 102 a-102 d are formed in the substrate 100. In some examples, in the formation of the isolation structures 102 a-102 d, a hard mask (not shown) is formed to cover the substrate 100, the hard mask is then patterned by a photolithography process and an etch process, and portions of the substrate 100, which are not covered by the patterned hard mask, are removed to form various trenches in the substrate 100, an isolation material is formed to fill the trenches and to cover the hard mask layer, and then the hard mask and the isolation material over the hard mask layer are removed to form the isolation structures 102 a-102 d in the substrate 100. The isolation structures 102 a-102 d formed in the substrate 100 at least define a first region 104 a, a second region 104 b, and a third region 104 c, in which the first region 104 a is located between the isolation structures 102 b and 102 c, the second region 104 b is located between the isolation structures 102 a and 102 b, and the third region 104 c is located between the isolation structures 102 c and 102 d. The isolation structures 102 a, 102 b, 102 c, and 102 d may be shallow trench isolation (STI) structures. The isolation material may be formed by using a high density plasma chemical vapor deposition (HDP CVD) method.
  • After the isolation structures 102 a-102 d are completed, a pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method. In some examples, a logic well 108 is formed in the substrate 100 in the second region 104 b by performing an implantation process on the second region 104 b. Then, a high voltage well 110 is formed in the substrate 100 in the third region 104 c by performing an implantation process on the third region 104 c. The logic well 108 and the high voltage well 110 are formed using dopants, such as boron and phosphorous. After the logic well 108 and the high voltage well 110 are completed, the portion of the pad oxide layer 106 in the first region 104 a is removed by using a photolithography method and an etching method. The remaining portions of the pad oxide layer 106 cover the second region 104 b and the third region 104 c, as shown in FIG. 1A.
  • As shown in FIG. 1B, an oxide layer 112, a nitride layer 114, and an oxide layer 116 are formed to cover the substrate 100 in sequence to form an ONO structure. The oxide layer 112, the nitride layer 114, and the oxide layer 116 may be formed by using a deposition method, such as a chemical vapor deposition (CVD) method. The oxide layers 112 and 116 may be formed from silicon oxide, and the nitride layer 114 may be formed from silicon nitride. In some exemplary examples, the oxide layer 112 is formed to have a thickness ranging from about 10 angstrom to about 20 angstrom, the nitride layer 114 is formed to have a thickness ranging from about 100 angstrom to about 150 angstrom, and the oxide layer 116 is formed to have a thickness ranging from about 30 angstrom to about 50 angstrom. A control gate layer 118 is formed to cover the oxide layer 116 by using a deposition method, such as a chemical vapor deposition method. The control gate layer 118 may be formed from polysilicon. In some exemplary examples, the control gate layer 118 is directly deposed on the oxide layer 116.
  • In some examples, referring to FIG. 1B again, a nitride layer 120, an oxide layer 122, and a nitride layer 124 are formed to cover the control gate layer 118 in sequence to form an NON structure. The nitride layer 120, the oxide layer 122, and the nitride layer 124 form a cap structure. The nitride layer 120, the oxide layer 122, and the nitride layer 124 may be formed by using a deposition method, such as a chemical vapor deposition method. The nitride layers 120 and 124 may be formed from silicon nitride, and the oxide layer 122 may be formed from silicon oxide.
  • As shown in FIG. 1C, a portion of the nitride layer 124, a portion of the oxide layer 122, a portion of the nitride layer 120, and a portion of the control gate layer 118 are removed by using a photolithography method and an etching method. The remaining portions of the control gate layer 118 disposed on the first region 104 a form control gates 118 a and 118 b respectively, and the remaining portions of the control gate layer 118 disposed on the second region 104 b and the third region 104 c form control gates 118 c and 118 d respectively. The remaining portion 120 a of the nitride layer 120, the remaining portion 122 a of the oxide layer 122, and the remaining portion 124 a of the nitride layer 124 are stacked on the control gate 118 a to form a stacked structure 126 a with the control gate 118 a. The remaining portion 120 b of the nitride layer 120, the remaining portion 122 b of the oxide layer 122, and the remaining portion 124 b of the nitride layer 124 are stacked on the control gate 118 b to form a stacked structure 126 b with the control gate 118 b. The remaining portion 120 c of the nitride layer 120, the remaining portion 122 c of the oxide layer 122, and the remaining portion 124 c of the nitride layer 124 are stacked on the control gate 118 c to form a stacked structure 126 c with the control gate 118 c. The remaining portion 120 d of the nitride layer 120, the remaining portion 122 d of the oxide layer 122, and the remaining portion 124 d of the nitride layer 124 are stacked on the control gate 118 d to form a stacked structure 126 d with the control gate 118 d.
  • As shown in FIG. 1D, spacers 128 a-128 d are respectively formed on sidewalls of the stacked structures 126 a-126 d to complete device structures 130 a-130 d, in which the device structures 130 a and 130 b are located on the first region 104 a, the device structure 130 c is located on the second region 104 b and covers the logic well 108, and the device structure 130 d is located on the second region 104 c and covers the high voltage well 110. The device structure 130 a-130 d are separated from each other. In some examples, each of the spacers 128 a-128 d is formed to include an oxide layer 132, a nitride layer 134, and an oxide layer 136 stacked on the sidewall of the respective stacked structure 126 a, 126 b, 126 c or 126 d in sequence. In some exemplary examples, forming the spacers 128 a-128 d includes blanketly forming the oxide layer 132, the nitride layer 134, and the oxide layer 136 in sequence to cover the stacked structures 126 a-126 d and the oxide layer 116, and etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 to remove a portion of the oxide layer 132, a portion of the nitride layer 134, and a portion of the oxide layer 136, so as to form the spacers 128 a-128 d on the sidewalls of the stacked structure 126 a-126 d respectively. The oxide layer 132, the nitride layer 134, and the oxide layer 136 may be formed by a deposition method, such as a chemical vapor deposition method. Etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 may be performed by using an anisotropic etching method.
  • Referring to FIG. 1D again, etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 includes etching the oxide layer 116 and the nitride layer 114. The portion 112 a of the oxide layer 112, the remaining portion 114 a of the nitride layer 114, and the remaining portion 116 a of the oxide layer 116 stacked in sequence form a trap storage structure 138 a. The portion 112 b of the oxide layer 112, the remaining portion 114 b of the nitride layer 114, and the remaining portion 116 b of the oxide layer 116 stacked in sequence form a trap storage structure 138 b. The portion 112 c of the oxide layer 112, the remaining portion 114 c of the nitride layer 114, and the remaining portion 116 c of the oxide layer 116 stacked in sequence form a trap storage structure 138 c. The portion 112 d of the oxide layer 112, the remaining portion 114 d of the nitride layer 114, and the remaining portion 116 d of the oxide layer 116 stacked in sequence form a trap storage structure 138 d. The device structures 130 a-130 d further respectively include the trap storage structures 138 a-138 d. In addition, each of the device structures 130 c and 130 d further includes the pad oxide layer 106. The device structures 130 c and 130 d are dummy device structures, and will be removed in the subsequent process.
  • In some examples, as shown in FIG. 1E, after the device structures 130 a-130 d are completed, an implantation process 140 may be performed on the substrate 100 through the oxide layer 112 by using the device structures 130 a-130 d as mask structures, so as to form a word line threshold voltage (Vt) 142, a source side junction 144, and a word line Vt 146 in the first region 104 a. The word line Vt 142 and the word line Vt 146 are respectively adjacent to the device structures 130 a and 130 b, and the source side junction 144 is located between the device structure 130 a and 130 b, and the source side junction 144 is opposite to the word line Vt 142 and the word line Vt 146 respectively. The implantation process 140 may be performed using dopants, such as boron and phosphorous.
  • In some examples, as shown in FIG. 1F, gap oxide layers 148 a and 148 b are formed on sidewalls of the spacers 128 a respectively, gap oxide layers 150 a and 150 b are formed on sidewalls of the spacers 128 b respectively, gap oxide layers 152 are formed on sidewalls of the spacers 128 c respectively, and gap oxide layers 154 are formed on sidewalls of the spacers 128 d respectively. The gap oxide layer 148 b and 150 b are disposed on the source side junction 144. In some exemplary examples, forming the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154 includes forming an oxide layer to cover the device structures 130 a-130 d and the oxide layer 112 on the substrate 100, and etching the oxide layer to remove a portion of the oxide layer to form the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154. The oxide layer may be formed from silicon oxide, and the oxide layer may be formed by a high temperature oxidation (HTO) method. Etching the oxide layer may be performed by an anisotropic etching method. Optionally, in the formation of the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154, a rapid thermal annealing (RTA) process may be performed on the oxide layer between forming the oxide layer and etching the oxide layer.
  • In some examples, the device structure 130 d and the gap oxide layers 154 are removed, as shown in FIG. 1G. In some exemplary examples, referring to FIG. 1F, the gap oxide layers 154 may be firstly removed. The nitride layer 124 d, the oxide layer 122 d, and the nitride layer 120 d are removed by an etching method. The control gate 118 d, the oxide layer 116, the nitride layer 114 are removed sequentially by an etching method. Then, the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • In some examples, after the device structure 130 d and the gap oxide layers 154 are removed, a first gate oxide layer 156 is formed to cover the substrate 100. The first gate oxide layer 156 may be formed to further cover the device structures 130 a-130 c. In some exemplary examples, the first gate oxide layer 156 may be formed to include a rapid thermal oxide (RTO) layer and a high temperature oxide layer on the rapid thermal oxide layer.
  • In some examples, as shown in FIG. 1H, the gap oxide layers 148 b and 150 b, located on the source side junction 144, and the gap oxide layers 152 located on the sidewalls of the device structure 130 c are removed. The gap oxide layers 148 b, 150 b and 152 may be removed by using a photolithography method and an etching method. A source line junction 158 is formed in the source side junction 144 by performing an implantation process on the source side junction 144. After the source line junction 158 is completed, the first gate oxide layer 156 on the source line junction 158 is removed by an etching method, as shown in FIG. 1H. A rapid thermal annealing process may be optionally performed on the first gate oxide layer 156 and the source line junction 158.
  • As shown in FIG. 1I, the device structure 130 c and the first gate oxide layer 156 overlying the device structure 130 c are removed. In some exemplary examples, referring to FIG. 1H, the first gate oxide layer 156 overlying the device structure 130 c is removed by a dip method. Next, the nitride layer 124 c, the oxide layer 122 c, and the nitride layer 120 c are removed by an etching method, then the control gate 118 c, the oxide layer 116, the nitride layer 114 are removed sequentially by an etching method, and then the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • In some examples, as shown in FIG. 1I, a second gate oxide layer 160 may be formed on the substrate 100 and the first gate oxide layer 156. The second oxide layer 160 may be referred to an IO oxide layer. In some exemplary examples, an operation of forming the second gate oxide layer 160 is performed by a logic dual gate oxide process, and a rapid thermal oxide layer of the second gate oxide layer 160 is firstly formed, and then a high temperature oxide layer of the second gate oxide layer 160 is formed on the rapid thermal oxide layer. A rapid thermal annealing process may be optionally performed on the second gate oxide layer 160.
  • In some examples, as shown in FIG. 1J, portions of the second gate oxide layer 160 and portions of the first gate oxide layer 156 on the first region 104 a, the second region 104 b, and a portion of the isolation structure 102 c are removed by, for example, a photolithography method, and an etching method or a dip method. Then, referring to FIG. 1J again, a third gate oxide layer 161 is formed to cover the first region 104 a, the second region 104 b, and the third region 104 c. The third gate oxide layer 161 may be referred to a core oxide layer. In some exemplary examples, after removing the portions of the second gate oxide layer 160 and the portions of the first gate oxide layer 156, the word line Vt 142, the word line Vt 146, the device structures 130 a and 130 b, the source line junction 158, the logic well 108, the isolation structure 102 b, and the portion of the isolation structure 102 c are exposed. Thus, the third gate oxide layer 161 is formed to cover the remaining portions of the second gate oxide layer 160, the word line Vt 142, the word line Vt 146, the device structures 130 a and 130 b, the source line junction 158, the logic well 108, the isolation structure 102 b, and the portion of the isolation structure 102 c. In certain examples, the second region 104 b has the second gate oxide layer 160 and the third gate oxide layer 161 sequentially covering thereon. The device including the second gate oxide layer 160 may be referred to a medium voltage (MV) device.
  • As shown in FIG. 1K, a conductive layer 162 is formed to cover the third gate oxide layer 161, the device structures 130 a and 130 b, and the gap oxide layers 148 a and 150 a. In some exemplary examples, the conductive layer 162 may be formed from polysilicon, and may be formed by using a deposition method, such as a chemical vapor deposition method.
  • As shown in FIG. 1L, a portion of the conductive layer 162 over the device structures 130 a and 130 b, the spacers 128 a and 128 b, and the gap oxide layers 148 a and 150 a is removed by using a photolithography method and an etching method. In the removing of the portion of the conductive layer 162, portions of the nitride layers 124 a and 124 b, portions of the spacers 128 a and 128 b, and portions of the gate oxide layers 148 a and 150 a are removed.
  • As shown in FIG. 1M, the conductive layer 162 is further etched to form word lines 164 and 166. In some examples, the word line 164 is disposed on the third gate oxide layer 161 over the word line Vt 142 and on one of the spacers 128 a of the device structure 130 a, in which the gap oxide layer 148 a is located between the word line 164 and the spacer 128 a; and the word line 166 is disposed on the third gate oxide layer 161 over the word line Vt 146 and on one of the spacers 128 b of the device structure 130 b, in which the gap oxide layer 150 a is located between the word line 166 and the spacer 128 b. The word lines 164 and 166 are respectively adjacent to the device structures 130 a and 130 b. In some exemplary examples, forming of the word lines 164 and 166 further include forming a gate 168 of the logic device 170 on the logic well 108 and a gate 172 of the high voltage device 174 on the high voltage well 110. The logic device 170 mainly includes the gate 168 and the third gate oxide layer 161, and the high voltage device 174 mainly includes the gate 172, the first gate oxide layer 156, the second gate oxide layer 160, and the third gate oxide layer 161.
  • As shown in FIG. 1E, during the implantation process 140, the device structures 130 c and 130 d can block the logic well 108 and the high voltage well 110 from the implantation process 140. Furthermore, as shown in FIG. 1F, the logic well 108 and the high voltage well 110 can be prevented by the device structures 130 c and 130 d during the high temperature process (i.e. the rapid thermal annealing process of the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154). As shown in FIG. 1G, the device structures 130 c can further block the logic well 108 from rapid thermal annealing process of the first gate oxide layer 156. Therefore, with the device structures 130 c and 130 d, the logic well 108 and the high voltage well 110 are well protected, thereby decreasing shift of the logic device 170 and the high voltage device 174.
  • Referring to FIG. 1M again, in some examples, after the word lines 164 and 166, the gates 168 and 172 are formed, various lightly doped drains 176 a-176 g are formed in the substrate 100 by using an implantation method. The lightly doped drains 176 a and 176 b are formed in the logic well 108 at opposite sides of the gate 168 and adjacent to the gate 168, the lightly doped drain 176 c is formed in the word line Vt 142 adjacent the word line 164, the lightly doped drain 176 d is formed in the word line Vt 146 adjacent the word line 166, the lightly doped drains 176 e and 176 f are formed in the high voltage well 110 at opposite sides of the gate 172 and adjacent to the gate 172, and the lightly doped drain 176 g is formed in the source line junction 158.
  • Referring to FIG. 1N, in some examples, various spacers 178 a-178 h are formed on the third gate oxide layer 161. The spacers 178 a and 178 b are formed on sidewalls of the gate 168, the spacer 178 c is formed on a sidewall of the word line 164, the spacer 178 d is formed on a sidewall of the device structure 130 a and over the lightly doped drain 176 g, the spacer 178 e is formed on a sidewall of the device structure 130 b and over the lightly doped drain 176 g, the spacer 178 f is formed on a sidewall of the word line 166, and the spacers 178 g and 178 h are formed on sidewalls of the gate 172. In some exemplary examples, an operation of forming the spacers 178 a-178 h includes blanketly forming a spacer material layer (not shown) to cover the third gate oxide layer 161, the gates 168 and 172, the device structures 130 a and 130 b, and the word lines 164 and 166, and performing an etching back process on the spacer material layer to remove a portion of the spacer material layer, a portion of the third gate oxide layer 161, a portion of the second gate oxide layer 160, and a portion of the first gate oxide layer 156, so as to form the spacers 178 a-178 h.
  • Referring to FIG. 1N again, after the spacers 178 a-178 h are completed, a source/drain (S/D) implantation process is performed on the substrate 100 to form S/D regions 180 a-180 g in the substrate 100. The S/D regions 180 a-180 g are respectively formed in the lightly doped drains 176 a-176 g.
  • Referring to FIG. 1O, in some examples, a silicide process is performed on the S/D regions 180 a-180 g and the word lines 164 and 166, to form various silicide regions 182 a-182 g, so as to substantially complete a semiconductor device 184. The silicide regions 182 a-182 k are respectively formed in the S/D regions 180 a-180 g, the gate 168, the word line 164, the word line 166, and the gate 172. The semiconductor device 184 may be a 1.5 T third generation embedded super-flash (ESF3) with an ONO trap storage structure.
  • As shown in FIG. 1C and FIG. 1D, the trap storage structures 138 a and 138 b are ONO structures, such that each of the trap storage structures 138 a and 138 b is thinner than a conventional polysilicon floating gate, and the control gates 118 a and 118 b can be directly stacked on the trap storage structures 138 a and 138 b. Thus, each of the device structures 130 a and 130 b has a lower structure topology which is close to that of other devices, such that the subsequent patterning processes of the semiconductor device 184 are relatively easy, thereby simplifying a process for manufacturing the semiconductor device 184 and integration of the processes of the semiconductor device 184 and the other devices, and decreasing process time and reducing process cost.
  • In addition, by using the ONO structure as the trap storage structure 138 a and 138 b, the semiconductor device 184 can be programmed using a source side injection (SSI) programming method, and can be erased using a Fowler-Nordheim (FN) erase method, thereby decreasing power consumption of the semiconductor device 184. Furthermore, because the semiconductor device 184 can be programmed by a SSI programming method, the programming operation of the semiconductor device 184 can be performed by a byte mode.
  • Referring to FIG. 2 with FIG. 1A through FIG. 1O, FIG. 2 is a flow chart of a method for manufacturing a semiconductor device in accordance with various embodiments. The method begins at operation 200, where a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a crystalline semiconductor substrate or a compound semiconductor substrate. For example, silicon or germanium may be used as a material forming the substrate 100. In certain examples, the substrate 100 may be a silicon on insulator substrate.
  • Then, as shown in FIG. 1A, various isolation structures 102 a-102 d are formed in the substrate 100 to at least define a first region 104 a, a second region 104 b, and a third region 104 c, in which the first region 104 a is located between the isolation structures 102 b and 102 c, the second region 104 b is located between the isolation structures 102 a and 102 b, and the third region 104 c is located between the isolation structures 102 c and 102 d. In some examples, in the formation of the isolation structures 102 a-102 d, a hard mask (not shown) is formed to cover the substrate 100, the hard mask is then patterned by a photolithography process and an etch process, and portions of the substrate 100, which are not covered by the patterned hard mask, are removed to form various trenches in the substrate 100, an isolation material is formed to fill the trenches and to cover the hard mask layer, and then the hard mask and the isolation material over the hard mask layer are removed to form the isolation structures 102 a-102 d in the substrate 100. The isolation structures 102 a-102 d may be shallow trench isolation structures. The isolation material may be formed by using a high density plasma chemical vapor deposition method.
  • A pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method. At operation 202, referring to FIG. 1A again, a logic well 108 is formed in the substrate 100 in the second region 104 b by performing an implantation process on the second region 104 b. At operation 204, a high voltage well 110 is formed in the substrate 100 in the third region 104 c by performing an implantation process on the third region 104 c. The logic well 108 and the high voltage well 110 are formed using dopants, such as boron and phosphorous. Then, the portion of the pad oxide layer 106 in the first region 104 a is removed by using a photolithography method and an etching method. The remaining portions of the pad oxide layer 106 cover the second region 104 b and the third region 104 c.
  • At operation 206, as shown in FIG. 1D, device structures 130 a and 130 b are formed on the first region 104 a, a device structure 130 c is formed on the second region 104 b and covering the logic well 108, and a device structure 130 d is formed on the third region 104 c and covering the high voltage well 110. In some examples, as shown in FIG. 1B, in the forming of the device structures 130 a-130 d, an oxide layer 112, a nitride layer 114, and an oxide layer 116 are formed to cover the substrate 100 in sequence to form an ONO structure. The oxide layer 112, the nitride layer 114, and the oxide layer 116 may be formed by using a deposition method. A control gate layer 118 is formed to cover the oxide layer 116 by using a deposition method. In some exemplary examples, the control gate layer 118 is directly deposed on the oxide layer 116. Then, a nitride layer 120, an oxide layer 122, and a nitride layer 124 are formed to cover the control gate layer 118 in sequence to form an NON structure. The nitride layer 120, the oxide layer 122, and the nitride layer 124 may be formed by using a deposition method.
  • As shown in FIG. 1C, a portion of the nitride layer 124, a portion of the oxide layer 122, a portion of the nitride layer 120, and a portion of the control gate layer 118 are removed by using a photolithography method and an etching method. The remaining portions of the control gate layer 118 disposed on the first region 104 a form control gates 118 a and 118 b respectively, and the remaining portions of the control gate layer 118 disposed on the second region 104 b and the third region 104 c form control gates 118 c and 118 d respectively. The remaining portion 120 a of the nitride layer 120, the remaining portion 122 a of the oxide layer 122, and the remaining portion 124 a of the nitride layer 124 are stacked on the control gate 118 a to form a stacked structure 126 a with the control gate 118 a. The remaining portion 120 b of the nitride layer 120, the remaining portion 122 b of the oxide layer 122, and the remaining portion 124 b of the nitride layer 124 are stacked on the control gate 118 b to form a stacked structure 126 b with the control gate 118 b. The remaining portion 120 c of the nitride layer 120, the remaining portion 122 c of the oxide layer 122, and the remaining portion 124 c of the nitride layer 124 are stacked on the control gate 118 c to form a stacked structure 126 c with the control gate 118 c. The remaining portion 120 d of the nitride layer 120, the remaining portion 122 d of the oxide layer 122, and the remaining portion 124 d of the nitride layer 124 are stacked on the control gate 118 d to form a stacked structure 126 d with the control gate 118 d.
  • As shown in FIG. 1D, spacers 128 a-128 d are respectively formed on sidewalls of the stacked structures 126 a-126 d to complete device structures 130 a-130 d, in which the device structures 130 a-130 d are separated from each other. In some examples, each of the spacers 128 a-128 d is formed to include an oxide layer 132, a nitride layer 134, and an oxide layer 136 stacked on the sidewall of the respective stacked structure 126 a, 126 b, 126 c or 126 d in sequence. In some exemplary examples, forming the spacers 128 a-128 d includes blanketly forming the oxide layer 132, the nitride layer 134, and the oxide layer 136 in sequence to cover the stacked structures 126 a-126 d and the oxide layer 116, and etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 to remove a portion of the oxide layer 132, a portion of the nitride layer 134, and a portion of the oxide layer 136, so as to form the spacers 128 a-128 d on the sidewalls of the stacked structure 126 a-126 d respectively. The oxide layer 132, the nitride layer 134, and the oxide layer 136 may be formed by a deposition method. Etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 may be performed by using an anisotropic etching method.
  • Referring to FIG. 1D again, etching the oxide layer 132, the nitride layer 134, and the oxide layer 136 includes etching the oxide layer 116 and the nitride layer 114. The portion 112 a of the oxide layer 112, the remaining portion 114 a of the nitride layer 114, and the remaining portion 116 a of the oxide layer 116 stacked in sequence form a trap storage structure 138 a. The portion 112 b of the oxide layer 112, the remaining portion 114 b of the nitride layer 114, and the remaining portion 116 b of the oxide layer 116 stacked in sequence form a trap storage structure 138 b. The portion 112 c of the oxide layer 112, the remaining portion 114 c of the nitride layer 114, and the remaining portion 116 c of the oxide layer 116 stacked in sequence form a trap storage structure 138 c. The portion 112 d of the oxide layer 112, the remaining portion 114 d of the nitride layer 114, and the remaining portion 116 d of the oxide layer 116 stacked in sequence form a trap storage structure 138 d. The device structures 130 a-130 d further respectively include the trap storage structures 138 a-138 d. In addition, each of the device structures 130 c and 130 d further includes the pad oxide layer 106.
  • At operation 208, as shown in FIG. 1E, an implantation process 140 may be performed on the substrate 100 through the oxide layer 112 by using the device structures 130 a-130 d as mask structures, so as to form a word line Vt 142, a source side junction 144, and a word line Vt 146 in the first region 104 a. The word line Vt 142 and the word line Vt 146 are respectively adjacent to the device structures 130 a and 130 b, and the source side junction 144 is located between the device structure 130 a and 130 b, and the source side junction 144 is opposite to the word line Vt 142 and the word line Vt 146 respectively.
  • Optionally, as shown in FIG. 1F, gap oxide layers 148 a and 148 b may be formed on sidewalls of the spacers 128 a respectively, gap oxide layers 150 a and 150 b may be formed on sidewalls of the spacers 128 b respectively, gap oxide layers 152 may be formed on sidewalls of the spacers 128 c respectively, and gap oxide layers 154 may be formed on sidewalls of the spacers 128 d respectively. The gap oxide layer 148 b and 150 b are disposed on the source side junction 144. In some exemplary examples, forming the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154 includes forming an oxide layer to cover the device structures 130 a-130 d and the oxide layer 112 on the substrate 100, and etching the oxide layer to remove a portion of the oxide layer to form the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154. The oxide layer may be formed by a high temperature oxidation method. Etching the oxide layer may be performed by an anisotropic etching method. Optionally, in the formation of the gap oxide layers 148 a, 148 b, 150 a, 150 b, 152, and 154, a rapid thermal annealing process may be performed on the oxide layer between forming the oxide layer and etching the oxide layer.
  • At operation 210, as shown in FIG. 1G, the device structure 130 d and the gap oxide layers 154 are removed. Referring to FIG. 1F, the gap oxide layers 154 may be firstly removed. The nitride layer 124 d, the oxide layer 122 d, and the nitride layer 120 d are removed by an etching method. Next, the control gate 118 d, the oxide layer 116, the nitride layer 114 are removed sequentially by an etching method. Then, the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method. In some exemplary examples, after the device structure 130 d and the gap oxide layers 154 are removed, a first gate oxide layer 156 is formed to cover the substrate 100. The first gate oxide layer 156 may be formed to further cover the device structures 130 a-130 c.
  • At operation 212, as shown in FIG. 1H, a source line junction 158 is formed in the source side junction 144. In some examples, the gap oxide layers 148 b and 150 b located on the source side junction 144, and the gap oxide layers 152 located on the sidewalls of the device structure 130 c are removed by using a photolithography method and an etching method. Then, the source line junction 158 is formed in the source side junction 144 by performing an implantation process on the source side junction 144. After the source line junction 158 is completed, the first gate oxide layer 156 on the source line junction 158 is removed by an etching method. A rapid thermal annealing process may be optionally performed on the first gate oxide layer 156 and source line junction 158.
  • At operation 214, as shown in FIG. 1I, the device structure 130 c and the first gate oxide layer 156 overlying the device structure 130 c are removed. Referring to FIG. 1H, the first gate oxide layer 156 overlying the device structure 130 c is removed by a dip method. Next, the nitride layer 124 c, the oxide layer 122 c, and the nitride layer 120 c are removed by an etching method. The control gate 118 c, the oxide layer 116, the nitride layer 114 are removed sequentially by an etching method. Then, the oxide layer 112 and the pad oxide layer 106 are removed by a photolithography method, and an etching method or a dip method.
  • In some examples, as shown in FIG. 1I, a second gate oxide layer 160 may be formed on the substrate 100 and the first gate oxide layer 156. In some exemplary examples, an operation of forming the second gate oxide layer 160 is performed by a logic dual gate oxide process, and a rapid thermal oxide layer of the second gate oxide layer 160 is firstly formed, and then a high temperature oxide layer of the second gate oxide layer 160 is formed on the rapid thermal oxide layer. A rapid thermal annealing process may be optionally performed on the second gate oxide layer 160.
  • In some examples, as shown in FIG. 1J, portions of the second gate oxide layer 160 and the first gate oxide layer 156 on the first region 104 a, the second region 104 b, and a portion of the isolation structure 102 c are removed by, for example, a photolithography method, and an etching method or a dip method. After removing the portions of the second gate oxide layer 160 and the portions of the first gate oxide layer 156, the word line Vt 142, the word line Vt 146, the device structures 130 a and 130 b, the source line junction 158, the logic well 108, the isolation structure 102 b, and the portion of the isolation structure 102 c are exposed. Then, referring to FIG. 1J again, a third gate oxide layer 161 is formed to cover the remaining portions of the second gate oxide layer 160, the word line Vt 142, the word line Vt 146, the device structures 130 a and 130 b, the source line junction 158, the logic well 108, the isolation structure 102 b, and the portion of the isolation structure 102 c. In certain examples, the second region 104 b has the second gate oxide layer 160 and the third gate oxide layer 161 sequentially covering thereon.
  • At operation 216, as shown in FIG. 1M, word lines 164 and 166 are formed. In some examples, in the formation of the word lines 164 and 166, a conductive layer 162 is formed to cover the third gate oxide layer 161, the device structures 130 a and 130 b, and the gap oxide layers 148 a and 150 a, as shown in FIG. 1K. The conductive layer 162 may be formed by using a deposition method. As shown in FIG. 1L, a portion of the conductive layer 162 over the device structures 130 a and 130 b, the spacers 128 a and 128 b, and the gap oxide layers 148 a and 150 a is removed by using a photolithography method and an etching method. In the removing of the portion of the conductive layer 162, portions of the nitride layers 124 a and 124 b, portions of the spacers 128 a and 128 b, and portions of the gate oxide layers 148 a and 150 a are removed.
  • Referring to FIG. 1M again, the conductive layer 162 is further etched to form the word lines 164 and 166. In some examples, the word line 164 is disposed on the third gate oxide layer 161 over the word line Vt 142 and on one of the spacers 128 a of the device structure 130 a, in which the gap oxide layer 148 a is located between the word line 164 and the spacer 128 a. The word line 166 is disposed on the third gate oxide layer 161 over the word line Vt 146 and on one of the spacers 128 b of the device structure 130 b, in which the gap oxide layer 150 a is located between the word line 166 and the spacer 128 b. The word lines 164 and 166 are respectively adjacent to the device structures 130 a and 130 b. In some exemplary examples, forming of the word lines 164 and 166 further include forming a gate 168 of the logic device 170 on the logic well 108 and a gate 172 of the high voltage device 174 on the high voltage well 110. The logic device 170 mainly includes the gate 168 and the third gate oxide layer 161, and the high voltage device 174 mainly includes the gate 172, the first gate oxide layer 156, the second gate oxide layer 160, and the third gate oxide layer 161.
  • Various lightly doped drains 176 a-176 g may be optionally formed in the substrate 100 by using an implantation method. The lightly doped drains 176 a and 176 b are formed in the logic well 108 at opposite sides of the gate 168 and adjacent to the gate 168, the lightly doped drain 176 c is formed in the word line Vt 142 adjacent the word line 164, the lightly doped drain 176 d is formed in the word line Vt 146 adjacent the word line 166, the lightly doped drains 176 e and 176 f are formed in the high voltage well 110 at opposite sides of the gate 172 and adjacent to the gate 172, and the lightly doped drain 176 g is formed in the source line junction 158.
  • Referring to FIG. 1N, various spacers 178 a-178 h are formed on the third gate oxide layer 161. The spacers 178 a and 178 b are formed on sidewalls of the gate 168, the spacer 178 c is formed on a sidewall of the word line 164, the spacer 178 d is formed on a sidewall of the device structure 130 a and over the lightly doped drain 176 g, the spacer 178 e is formed on a sidewall of the device structure 130 b and over the lightly doped drain 176 g, the spacer 178 f is formed on a sidewall of the word line 166, and the spacers 178 g and 178 h are formed on sidewalls of the gate 172. In some exemplary examples, an operation of forming the spacers 178 a-178 h includes blanketly forming a spacer material layer to cover the third gate oxide layer 161, the gates 168 and 172, the device structures 130 a and 130 b, and the word lines 164 and 166, and performing an etching back process on the spacer material layer to remove a portion of the spacer material layer, a portion of the third gate oxide layer 161, a portion of the second gate oxide layer 160, and a portion of the first gate oxide layer 156.
  • Referring to FIG. 1N again, after the spacers 178 a-178 h are completed, a S/D implantation process is performed on the substrate 100 to form S/D regions 180 a-180 g in the substrate 100. The S/D regions 180 a-180 g are respectively formed in the lightly doped drains 176 a-176 g. Referring to FIG. 1O, a silicide process is performed on the S/D regions 180 a-180 g and the word lines 164 and 166, to form various silicide regions 182 a-182 k, so as to substantially complete a semiconductor device 184. The silicide regions 182 a-182 k are respectively formed in the S/D regions 180 a-180 g, the gate 168, the word line 164, the word line 166, and the gate 172.
  • In accordance with an embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. A first word line and a second word line are respectively formed on the first word line Vt adjacent to the first device structure and the second word line Vt adjacent to the second device structure.
  • In accordance with another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. Gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure. The fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed. A first gate oxide layer is formed to cover the substrate. The gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed. A source line junction is formed in the substrate between the first device structure and the second device structure. The third device structure is removed. A second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed. A third gate oxide layer is formed to cover the first region, the second region, and the third region. A first word line and a second word line are respectively formed on the gap oxide layer on the first device structure and the gap oxide layer on the second device structure.
  • In accordance with yet another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. In forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure, a trap storage structure is formed on the substrate, a control gate is directly formed on the trap storage structure, a cap structure is formed on the control gate to form a stacked structure, and various spacers are respectively formed on sidewalls of the stacked structure. A first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively. Various gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure. The fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed. A first gate oxide layer is formed to cover the substrate. The gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed. A source line junction is formed in the substrate between the first device structure and the second device structure. The third device structure is removed. A second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed. A third gate oxide layer is formed to cover the first region, the second region, and the third region A first word line is formed on the gap oxide layer on the first device structure, a second word line is formed on the gap oxide layer on the second device structure, a gate of a high voltage device is formed on the high voltage well, and a gate of a logic device is formed on the logic well.
  • The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method for manufacturing a semiconductor device, the method comprising:
forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
forming a logic well and a high voltage well respectively in the second region and the third region;
forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well;
forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively;
removing the fourth device structure;
forming a source line junction in the source side junction;
removing the third device structure; and
forming a first word line and a second word line respectively on the first implanted area adjacent to the first device structure and the second implanted area adjacent to the second device structure.
2. The method of claim 1, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprise:
forming a trap storage structure on the substrate;
forming a control gate directly on the trap storage structure; and
forming a cap structure on the control gate to form a stacked structure.
3. The method of claim 2, wherein forming the trap storage structure further comprises:
forming a first oxide layer on the substrate;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
4. The method of claim 2, wherein forming the cap structure further comprises:
forming a first nitride layer on the control gate;
forming an oxide layer on the first nitride layer; and
forming a second nitride layer on the oxide layer.
5. The method of claim 2, wherein forming each of the first device structure and the second device structure further comprises:
forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure.
6. The method of claim 5, wherein forming each of the spacers further comprises:
forming a first oxide layer;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
7. The method of claim 1,
after forming the first implanted area, the source side junction, and the second implanted area, the method further comprising forming a plurality of gap oxide layers on sidewalls of the first device structure and the second device structure; and
between removing the fourth device structure and forming the source line, the method further comprising removing the gap oxide layers on the source side junction.
8. The method of claim 1,
between removing the fourth device structure and forming the source line junction, the method further comprising forming a first gate oxide layer to cover the substrate; and
between removing the third device structure and forming the first word line and the second word line, the method further comprising:
forming a second gate oxide layer on the substrate and the first gate oxide layer;
removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region to expose the first implanted area, the second implanted area, the first device structure, the second device structure, the source line junction, and the logic well; and
forming a third gate oxide layer on the second gate oxide layer, the first implanted area, the second implanted area, the first device structure, the second device structure, the source line junction, and the logic well.
9. The method of claim 1, wherein forming the first word line and the second word line comprises forming a gate of a high voltage device on the third region and a gate of a logic device on the second region.
10. A method for manufacturing a semiconductor device, the method comprising:
forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
forming a logic well and a high voltage well respectively in the second region and the third region;
forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well;
forming a plurality of gap oxide layers on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure;
removing the fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure;
forming a first gate oxide layer to cover the substrate;
removing the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure;
forming a source line junction in the substrate between the first device structure and the second device structure;
removing the third device structure;
forming a second gate oxide layer on the substrate and the first gate oxide layer;
removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region;
forming a third gate oxide layer to cover the first region, the second region, and the third region; and
forming a first word line and a second word line respectively on the gap oxide layer on the first device structure and the gap oxide layer on the second device structure.
11. The method of claim 10, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprises:
forming a trap storage structure on the substrate;
forming a control gate directly on the trap storage structure; and
forming a cap structure on the control gate to form a stacked structure.
12. The method of claim 11, wherein forming the trap storage structure further comprises:
forming a first oxide layer on the substrate;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
13. The method of claim 11, wherein forming the cap structure further comprises:
forming a first nitride layer on the control gate;
forming an oxide layer on the first nitride layer; and
forming a second nitride layer on the oxide layer.
14. The method of claim 11, wherein forming each of the first device structure and the second device structure further comprises:
forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure.
15. The method of claim 14, wherein forming each of the spacers further comprises:
forming a first oxide layer;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
16. The method of claim 11, between forming the first device structure, the second device structure, the third device structure, and the fourth device structure, and forming the gap oxide layers, the method further comprising:
forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively.
17. A method for manufacturing a semiconductor device, the method comprising:
forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
forming a logic well and a high voltage well respectively in the second region and the third region;
forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprises:
forming a trap storage structure on the substrate;
forming a control gate directly on the trap storage structure;
forming a cap structure on the control gate to form a stacked structure; and
forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure;
forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively;
forming a plurality of gap oxide layers on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure;
removing the fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure;
forming a first gate oxide layer to cover the substrate;
removing the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure;
forming a source line junction in the substrate between the first device structure and the second device structure;
removing the third device structure;
forming a second gate oxide layer on the substrate and the first gate oxide layer;
removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region;
forming a third gate oxide layer to cover the first region, the second region, and the third region; and
forming a first word line on the gap oxide layer on the first device structure, a second word line on the gap oxide layer on the second device structure, a gate of a high voltage device on the high voltage well, and a gate of a logic device on the logic well.
18. The method of claim 17, wherein forming the trap storage structure further comprises:
forming a first oxide layer on the substrate;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
19. The method of claim 17, wherein forming the cap structure further comprises:
forming a first nitride layer on the control gate;
forming an oxide layer on the first nitride layer; and
forming a second nitride on the oxide layer.
20. The method of claim 17, wherein forming each of the spacers further comprises:
forming a first oxide layer;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
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