CN101431058B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN101431058B
CN101431058B CN2008101707993A CN200810170799A CN101431058B CN 101431058 B CN101431058 B CN 101431058B CN 2008101707993 A CN2008101707993 A CN 2008101707993A CN 200810170799 A CN200810170799 A CN 200810170799A CN 101431058 B CN101431058 B CN 101431058B
Authority
CN
China
Prior art keywords
bump electrode
dummy pattern
wiring
film
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008101707993A
Other languages
English (en)
Other versions
CN101431058A (zh
Inventor
铃木进也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN101431058A publication Critical patent/CN101431058A/zh
Application granted granted Critical
Publication of CN101431058B publication Critical patent/CN101431058B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H01L2224/294—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1426—Driver
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种半导体器件及其制造方法。本发明改进了半导体芯片的凸点电极和安装衬底的布线之间耦合的可靠性，更特别地，即使当布线位于凸点电极之下的顶布线层中时本发明仍保证了凸点电极的平坦性，从而改进了凸点电极和形成在玻璃衬底上的布线之间耦合的可靠性。包括电源线或信号线的布线以及虚拟图案形成在凸点电极的非重叠区之下的顶布线层中。虚拟图案定位为填充布线之间的空间以减少由顶布线层中的布线和空间造成的不规则性。通过CMP对形成为覆盖顶布线层的表面保护膜进行平坦化。

Description

半导体器件及其制造方法
相关申请的交叉引用
在此通过参考引入于2007年11月9日提交的日本专利申请No.2007-292079的全部公开内容，包括说明书、附图和摘要。
技术领域
本发明涉及半导体器件及其制造方法，更特别地涉及对于在LCD(液晶显示器)驱动器中使用的半导体器件有用的技术。
背景技术
日本未审专利公开No.2007-103848公开了一种减少半导体芯片尺寸的技术。根据该技术，将焊盘和布线形成在绝缘膜之上。将表面保护膜形成在包括焊盘和布线的绝缘膜之上，并且在表面保护膜中制作开口。该开口形成在焊盘之上以露出焊盘表面。凸点电极形成在包括该开口的表面保护膜之上。焊盘比凸点电极小得多。因此，布线可以在与焊盘的同一层中置于凸点电极之下。换言之，在该技术中，通过减少焊盘尺寸，将布线置于凸点电极之下成为可用的空间中。
发明内容
近年来，使用液晶显示器元件的LCD迅猛发展。通过驱动LCD的驱动器来控制LCD。LCD驱动器包括例如安装在玻璃衬底上的半导体芯片。LCD驱动器的半导体芯片具有在其半导体衬底之上的多个晶体管和多层布线层，在表面之上有凸点电极。形成在表面之上的凸点电极通过各向异性导电膜与玻璃衬底耦合。因此半导体芯片和玻璃衬底通过凸点电极耦合。为了增加粘合强度，增加凸点电极面积以使得半导体芯片和玻璃衬底之间的粘合面积更大已经成为一般惯例。因此，在用于LCD驱动器的半导体芯片中使用的凸点电极比通用半导体芯片大得多。
在LCD驱动器中，用作表面保护膜(钝化膜)的绝缘膜形成在凸点电极之下，并且凸点电极通过在绝缘膜中制作的开口与形成在多层布线层的顶层中的焊盘耦合。通常，开口和焊盘在面积上几乎与凸点电极相同。然而，当焊盘几乎等于凸点电极时，焊盘占据大面积，从而引起没有空间可用于将与焊盘布置在同一层中的电源线和信号线的问题。
为此，通常LCD驱动器使用比凸点电极小的焊盘。因为凸点电极比焊盘大，在平面图上，其具有与焊盘重叠的重叠区和不与焊盘重叠的非重叠区。因此，多层布线层的顶层中在凸点电极的非重叠区之下的空间可用。因此，电源线和信号线可以置于该空间中，允许非重叠区之下空间的有效使用。因此，通过使用比凸点电极小的焊盘，除了焊盘之外，布线可以置于凸点电极之下，有助于半导体芯片(LCD驱动器)的尺寸减少。
然而，凸点电极之下顶布线层中布线的存在引起下面参照附图说明的问题。图36示出构成LCD驱动器的半导体芯片的顶层布线和凸点电极之间的耦合关系。如图36所示，焊盘PD和布线L1和L2形成在层间绝缘膜100的顶层中。即，焊盘PD和布线L1和L2形成在同一层中。形成表面保护膜101以覆盖其中形成焊盘和布线的顶布线层。该表面保护膜101具有不规则表面，其反映焊盘PD和布线L1和L2的位置。因此，形成在表面保护膜101之上的凸点电极BP具有反映表面保护膜101的不规则性的形状。该凸点电极BP通过塞(plug)SIL与焊盘PD电耦合，该塞具有埋在其开口中的导电材料。形成在表面保护膜101之上的凸点电极BP大于焊盘PD，并且在平面图上具有与焊盘PD重叠的重叠区X和不与焊盘PD重叠的非重叠区Y。换言之，顶布线层中在图36所示凸点电极BP的非重叠区Y之下没有焊盘PD形成，并且一些空间是可用的。该空间可有效用于除了焊盘PD之外在顶布线层中布置布线L1和L2，使得半导体芯片(LCD驱动器)可以变小。
然而，如果布线L1和L2置于顶布线层中恰好在凸点电极BP的非重叠区Y之下，则在表面保护膜101上产生反映布线L1和L2的位置的不规则性。因此，形成在表面保护膜101之上的凸点电极BP具有反映表面保护膜101的不规则性的不规则性。如果凸点电极BP具有这种不规则表面，则在安装半导体芯片到玻璃衬底上时将存在一些困难。
图37是示出半导体芯片如何安装到玻璃衬底上的截面图。如图37所示，通过将半导体芯片的凸点电极BP通过各向异性导电膜ACF与玻璃衬底103的布线103a耦合来将半导体芯片安装到玻璃衬底103上。如果凸点电极BP具有不规则表面，则ACF的导电微粒不能适当地接触凸点电极BP。如图37所示，当凸点电极BP的不规则表面的凸出部分接触导电微粒102时，凹入部分不能适当地接触导电微粒102。凸点电极BP的凸出部分受到玻璃衬底103的压力，接触导电微粒102，确保了导电性。另一方面，凸点电极BP的凹入部分几乎不受到玻璃衬底103的压力，使得难以确保凸点电极BP和导电微粒102之间的导电性。
因此，即使增加凸点电极BP的尺寸以确保玻璃衬底103和凸点电极BP之间通过ACF的导电性，凸点电极BP的表面不规则性也使得难以提高凸点电极BP和形成在玻璃衬底103上的布线103a之间的耦合的可靠性。
本发明的目的是提供一种技术，增加半导体芯片的凸点电极和安装衬底的布线之间耦合的可靠性。更具体地，旨在提供一种技术，通过即使当布线位于凸点电极之下的顶布线层中时也确保凸点电极的平坦性，来增加凸点电极和形成在玻璃衬底之上的布线之间耦合的可靠性。
本发明的上述和其他目的和新颖特征将通过该说明书中以下详细描述和附图而充分显现。
这里将公开的本发明的优选实施方式在下面简要概述。
根据本发明的优选实施方式，一种半导体器件包括：(a)半导体衬底，(b)形成在半导体衬底之上的半导体元件，(c)形成在半导体元件之上的多层布线层，以及(d)形成在多层布线层的顶层中的焊盘。其进一步包括：(e)形成在焊盘之上并具有达到焊盘的开口的表面保护膜，以及(f)形成在表面保护膜之上并通过填充开口与焊盘电耦合的凸点电极。凸点电极大于焊盘，从而具有在平面图上与焊盘重叠的重叠区和在平面图上不与焊盘重叠的非重叠区。这里，在多层布线层的顶层中形成：(g)除了焊盘之外的包括电源线或信号线的第一布线，和(h)不同于第一布线的虚拟图案(dummypattern)。与焊盘形成在同一层中的第一布线形成在凸点电极的非重叠区之下的层中。
因为除了电源线或信号线之外有虚拟图案位于多层布线层的顶层中，因此增加了形成在顶层之上的表面保护膜的平坦性。如果仅电源线或信号线形成在多层布线层的顶层中，则由电源线或信号线造成的表面不规则性将变得严重，这是因为顶层不可能密集地填满电源线或信号线。另一方面，通过将该层填满虚拟图案以及电源线或信号线，增加了顶层的平坦性。因此，保证了形成在顶层之上的表面保护膜的平坦性，并且还增加了形成在表面保护膜的表面之上的凸点电极的平坦性。
根据本发明的优选实施方式，制造半导体器件的方法包括以下步骤：(a)在半导体衬底之上形成半导体元件，(b)在半导体元件之上形成多层布线层，以及(c)在多层布线层的顶层中形成导电膜。这些步骤之后的步骤是：(d)通过对导电膜进行构图，形成焊盘、包括电源线或信号线的第一布线以及虚拟图案，以及(e)形成表面保护膜使得覆盖焊盘、第一布线和虚拟图案。该方法进一步包括以下步骤：(f)在表面保护膜中制作达到焊盘的开口，以及(g)在包括开口的表面保护膜之上形成大于焊盘的凸点电极。这里，在步骤(g)中，形成凸点电极，使得具有在平面图上与焊盘重叠的重叠区和在平面图上不与焊盘重叠的非重叠区。与焊盘形成在同一层中的第一布线形成在步骤(g)中形成的凸点电极的非重叠区之下的层中，并且虚拟图案形成在与形成在非重叠区之下的层中的第一布线相邻的给定区域中。
在此公开的本发明的优选实施方式带来的有益效果在下面简要描述。
因为除了电源线或信号线之外有虚拟图案位于多层布线层的顶层中，因此增加了形成在顶布线层之上的表面保护膜的平坦性。如果仅电源线或信号线形成在多层布线层的顶层中，则由电源线或信号线造成的表面不规则性将变得严重，这是因为顶层不可能密集地填满电源线或信号线。通过使顶层形成有虚拟图案以及电源线或信号线，增加了顶层的平坦性。因此，保证了形成在顶层之上的表面保护膜的平坦性，并且还增加了形成在表面保护膜的表面之上的凸点电极的平坦性。因此，增强了半导体芯片的凸点电极和安装衬底的布线之间耦合的可靠性。
附图说明
图1是根据本发明的实施方式的半导体芯片的平面图；
图2是示出图1所示半导体芯片中用于输入信号的凸点电极及其附近的放大图；
图3是示出图2所示虚拟图案的布置的放大图；
图4是示出图1所示半导体芯片中用于输入信号的凸点电极及其附近的放大图；
图5是沿图2中A-A线截取的截面图；
图6是沿图2中B-B线截取的截面图；
图7示出覆盖虚拟图案的氧化硅膜的不规则表面和虚拟图案的尺寸之间的关系；
图8示出覆盖虚拟图案的氧化硅膜的不规则表面和虚拟图案的尺寸之间的关系；
图9是示出图1所示半导体芯片中用于输出信号的凸点电极及其附近的放大图；
图10是图9所示内容的变型；
图11是沿图9中A-A线截取的截面图；
图12示出形成在顶布线层中的布线和虚拟图案占据小于70％的半导体芯片面积；
图13是沿图12中A-A线截取的截面图；
图14示出形成在顶布线层中的布线和虚拟图案占据70％或更多的半导体芯片面积；
图15是沿图14中B-B线截取的截面图；
图16示出其中形成在顶布线层中的布线和虚拟图案占据小于70％的半导体芯片面积的蚀刻的初始阶段；
图17示出其中形成在顶布线层中的布线和虚拟图案占据小于70％的半导体芯片面积的蚀刻的最终阶段；
图18示出其中形成在顶布线层中的布线和虚拟图案占据70％或更多的半导体芯片面积的蚀刻的初始阶段；
图19示出其中形成在顶布线层中的布线和虚拟图案占据70％或更多的半导体芯片面积的蚀刻的最终阶段；
图20是形成在半导体芯片中的MISFET的截面图；
图21是示出制造MISFET的序列的流程图；
图22是示出一种实施方式中制造半导体器件的工艺中步骤的截面图；
图23是示出图22所示步骤之后的半导体器件制造步骤的截面图；
图24是示出图23所示步骤之后的半导体器件制造步骤的截面图；
图25是示出图24所示步骤之后的半导体器件制造步骤的截面图；
图26是示出图25所示步骤之后的半导体器件制造步骤的截面图；
图27是示出图26所示步骤之后的半导体器件制造步骤的截面图；
图28是示出图27所示步骤之后的半导体器件制造步骤的截面图；
图29是示出图28所示步骤之后的半导体器件制造步骤的截面图；
图30是示出图29所示步骤之后的半导体器件制造步骤的截面图；
图31是示出图30所示步骤之后的半导体器件制造步骤的截面图；
图32是示出图31所示步骤之后的半导体器件制造步骤的截面图；
图33是示出一种实施方式中半导体芯片安装到玻璃衬底上的截面图；
图34是示出半导体芯片和玻璃衬底通过各向异性导电膜耦合的放大图；
图35示出液晶显示器件的主要组件；
图36示出基于本发明人的试验在半导体芯片的顶层布线和凸点电极之间的耦合关系；以及
图37是示出基于本发明人的试验半导体芯片如何安装到玻璃衬底上的截面图。
具体实施方式
以下描述的优选实施方式将按照需要分别描述，但是它们并非彼此不相关的，除非另有说明。它们整体或部分地是彼此的变型，并且有时一个描述是另一个的细节或补充形式。
此外，在以下描述的优选实施方式中，即使当用于元件的数字数据(件数、数值、质量、范围等)由特定数字指示时，其也不限于指示的特定数字，除非另有说明或者理论上限于特定数字；其可以大于或小于特定数字。
在以下描述的优选实施方式中，不言而喻，它们的组成元素(包括组成步骤)不一定是必需的，除非另有说明或者理论上认为是必需的。
同样，在以下描述的优选实施方式中，当特定形状或位置关系被指示用于元件时，应该解释为包括实质上等效或类似于特定形状或位置关系的形状或位置关系，除非另有说明或者除非特定形状或位置关系在理论上认为是必要的。如上所述的数值或范围也是如此。
在示出优选实施方式的所有附图中，具有相同功能的元件基本上由相同参考标号指示，并且省略其重复描述。为了易于理解，甚至在平面图中也会使用影线。
图1是示出本发明的实施方式中半导体芯片CHP(半导体器件)的平面图。该实施方式中的半导体芯片CHP是LCD驱动器。参照图1，例如，半导体芯片CHP包括形状为细长矩形的半导体衬底1S，以及驱动LCD器件的LCD驱动器形成在其主表面上。该LCD驱动器具有通过将电压提供到构成LCD的单元阵列中的每个像素来控制液晶分子的定向的功能，并且包括栅驱动电路、源驱动电路、液晶驱动电路、图形RAM(随机存取存储器)和外围电路。这些元件的功能通过形成在半导体衬底1S之上的半导体元件和布线来执行。首先，下面将说明半导体芯片CHP的表面配置。
半导体芯片CHP是具有一对短边和一对长边的矩形，其中凸点电极BP1沿长边之一(如图1所示的下边)按行布置。凸点电极BP1用作外部连接端子，用于与包括形成在半导体芯片CHP内部的半导体元件和布线的集成电路(LCD驱动器)耦合。凸点电极BP1是用于数字输入信号或模拟输入信号的凸点电极。
此外，凸点电极BP2沿另一长边(如图1所示的上边)布置。它们以Z字形图案布置在两行中。该布置图案允许凸点电极BP2密集定位。这些凸点电极BP2也用作外部连接端子，使半导体衬底1S内部的集成电路与外部耦合。凸点电极BP2是用于来自LCD驱动器的输出信号的凸点电极。
这样，凸点电极BP1和凸点电极BP2沿半导体芯片CHP的外围上的一对长边布置。凸点电极BP2的数量大于凸点电极BP1的数量；凸点电极BP1沿一条长边按行布置，同时凸点电极BP2沿另一条长边以Z字形图案布置。这种布置的原因在于，凸点电极BP1是用于进入LCD驱动器的输入信号，而凸点电极BP2是用于来自LCD驱动器的输出信号。因为进入LCD驱动器的输入信号承载串行数据，所以不需要那么多凸点电极BP1作为外部连接端子。另一方面，来自LCD驱动器的输出信号承载并行数据，并且需要许多凸点电极BP2作为外部连接端子。更具体地，用于输出信号的凸点电极BP2的每个被提供用于形成液晶显示器元件(像素)的一个单元，这意味着需要与单元一样多的凸点电极BP2。因此，用于输出信号的凸点电极BP2的数量大于用于输入信号的凸点电极BP1的数量。为此，用于输入信号的凸点电极BP1可以沿长边按行布置，而用于输出信号的凸点电极BP2沿长边以Z字形图案布置。
尽管图1示出用于输入信号的凸点电极BP1和用于输出信号的凸点电极BP2沿半导体芯片CHP的一对长边布置，但可以添加沿一对短边布置的凸点电极。
接下来，将详细描述凸点电极BP1和BP2。凸点电极BP1和BP2每个都具有矩形形状，该矩形具有短边和长边，其中其长边平行于半导体芯片CHP的短边，并且凸点电极BP1和BP2沿半导体芯片CHP的长边布置。形成在半导体芯片CHP之上的凸点电极BP1和BP2在尺寸(面积)上大于通用凸点电极。换言之，凸点电极BP1和BP2的表面积比率较大。如下面将描述的，这旨在确保将半导体芯片CHP(LCD驱动器)通过各向异性导电膜安装到用于液晶显示器件的玻璃衬底上的耦合可靠性。因此，尽管通用半导体芯片在形成半导体元件的有源区中不具有凸点电极，但用于LCD驱动器的半导体芯片CHP在有源区中具有凸点电极BP1和BP2。
凸点电极BP1形成在半导体芯片CHP的表面之上。接下来，将说明凸点电极BP1和它们下面的顶布线层之间的位置关系。图2是示出图1中区域R的放大图。参照图2，凸点电极BP1沿半导体芯片的长边并排放置。图2示出两个相邻凸点电极BP1。这些凸点电极BP1形成在半导体芯片的表面保护膜(钝化膜)之上，并且顶布线层形成在表面保护膜之下。在图2中，省略表面保护膜，以便示出表面保护膜之下的顶布线层和凸点电极BP1之间的位置关系。
如图2所示，凸点电极BP1与形成在顶布线层中的焊盘PD耦合。每个凸点电极BP1大于焊盘PD。除了焊盘之外，布线L1位于凸点电极之下的顶布线层中。即，布线L1在凸点电极BP1之下沿半导体芯片CHP的长边延伸。因为凸点电极BP1大于焊盘PD，在凸点电极BP1之下多层布线层的顶层中有一些空间可用。因此，可以使布线L1位于该空间中，从而有效使用凸点电极BP1之下的空间。因此，小于凸点电极BP1的焊盘PD的使用使得除了焊盘PD之外可以将布线L1放置于凸点电极BP1之下，从而可以使半导体芯片CHP(LCD驱动器)变小。布线L1可以是电源线或信号线。
如前所述，当布线L1形成在凸点电极BP1之下时，表面保护膜具有反映布线和空间之间的水平差的不规则表面；因此凸点电极BP1将形成在表面保护膜的不规则表面之上。结果，凸点电极BP1的表面将不平坦，而是不规则的。如果凸点电极BP1的表面是不规则的，则在将半导体芯片安装到玻璃衬底上时将存在一些困难。因此，凸点电极BP1的表面必须是平坦的。
在该实施方式中，在放置布线L1的顶布线层中形成虚拟图案DP，如图2所示。在图2的示例中，将虚拟图案DP以填充该区域的方式放置在邻近布线L1的区域中。特别地，布线L1之间的空间用虚拟图案DP填满。因此，每个凸点电极BP1之下的空间用虚拟图案DP填满。换言之，多个布线L1以及在形成在布线L1之间的虚拟图案DP位于凸点电极BP1之下的顶布线层中。这减少了凸点电极BP1之下的层(顶布线层)中布线和空间之间的水平差。更具体地，具有几乎与布线L1相同高度的虚拟图案DP形成在凸点电极BP1之下的层(顶布线层)中可用的空间中，从而凸点电极BP1之下的层(顶布线层)中的水平差通过布线L1和虚拟图案而减少。
在顶布线层中，除了在凸点电极BP1之下平行于布线L1布置的虚拟图案DP之外，在不位于凸点电极BP1之下的区域中形成虚拟图案DP。即，在平面图中不与凸点电极重叠的区域中邻近布线L1布置虚拟图案DP。在凸点电极BP1之下的空间中形成虚拟图案DP被认为是消除凸点电极BP1之下的布线L1和该空间之间的水平差所必需的。问题是在平面图中不与凸点电极BP1重叠的区域中邻近布线L1形成虚拟图案DP是否是有益的。然而，即使在不在凸点电极BP1之下的区域中，也将存在布线L1和空间之间的水平差。如果在凸点电极BP1附近存在这种水平差，将影响凸点电极BP1的平坦性。为此，在该实施方式中，虚拟图案DP不仅放置在凸点电极BP1之下的层(顶布线层)中，而且放置在离凸点电极BP1一定距离内的区域中，以保证凸点电极BP1的平坦性。
接下来，将描述虚拟图案DP的布置。图3示出虚拟图案DP的布置。如图3所示，每个虚拟图案DP是具有短边和长边的矩形，并且这种虚拟图案DP如图所示垂直和水平地布置以填充空间。例如，每个虚拟图案具有5.0μm的长边和0.8μm的短边。因为布线L1典型地具有20-30μm的宽度，虚拟图案DP的短边和长边都小于布线L1的宽度。即，每个虚拟图案DP是很小的。这意味着即使当布线L1之间的空间小于布线L1的宽度时，小空间也可以用虚拟图案填满。因此，因为甚至小空间都可以用虚拟图案DP填满，所以顶布线层的平坦性可以足够高。特别地，如图3所示，每个虚拟图案本身是小的，并且虚拟图案DP之间的间隔小到例如为0.6μm。换言之，虚拟图案DP之间的间隔小于虚拟图案DP的短边，使得该空间密集地填满虚拟图案。
图4示出不同于图2所示的虚拟图案DP的布置的示例。如图4所示，凸点电极BP1之下的层(顶布线层)由多条布线L1占据。换言之，布线L1密集地布置，并且凸点电极BP1之下的层(顶布线层)中没有空间可用于虚拟图案DP。因此，在图4的示例中，看起来凸点电极BP1之下的层(顶布线层)中不存在水平差的问题。然而，如图4所示，在形成布线L1使得填充凸点电极BP1之下的区域的同时，在平面图中不与凸点电极BP1重叠的外围区域中没有形成布线L1。具体地，凸点电极BP1的外围区域包括在顶布线层中形成有布线L1的区域和没有布线的区域(空间)两种。因此，在布线L1和空间之间将存在水平差。为了确保凸点电极BP1的平坦性，减少每个凸点电极BP1之下的这种水平差是重要的。因为即使凸点电极BP1的外围区域中的水平差也会影响凸点电极BP1的平坦性，所以在顶布线层中也应该减少外围区域中的该水平差。这是因为，在图4的示例中，虚拟图案DP也形成在邻近布线L1的区域(凸点电极BP1的外围区域)中。因此，凸点电极BP1的外围区域中的水平差在顶布线层中减少，并且保证了形成在顶布线层之上的凸点电极BP1的平坦性。如图2和图4所示，显然，当在凸点电极BP1之下存在布线L1和空间时，形成虚拟图案DP以填充空间是最有效的，并且甚至在顶布线层中离凸点电极BP1一定距离内的外围区域中形成虚拟图案DP也是有效的。上面已说明了凸点电极BP1和形成在凸点电极BP1之下的层(顶布线层)中的虚拟图案DP之间的位置关系。在凸点电极BP2和虚拟图案DP之间的位置关系也是如此。
接下来，将参照截面图说明虚拟图案DP。图5是沿图2中A-A线截取的截面图。图5仅示出包括顶布线层的多层布线层的上部，并且省略了顶布线层之下的部分。
如图5所示，布线42形成在作为层间绝缘膜的氧化硅膜40之上。该布线42通过塞43与其下方的布线耦合。尽管形成在氧化硅膜40中的塞43之下的布线和半导体元件未在图5中示出，但多层布线和如MISFET的半导体元件形成在布线42之下。层间绝缘膜以覆盖布线42的方式形成。层间绝缘膜包括氧化硅膜20和形成在氧化硅膜20之上的TEOS(正硅酸乙酯)的氧化硅膜21。顶布线层形成在层间绝缘膜之上。顶布线层包括焊盘、布线L1和虚拟图案DP。焊盘DP、布线L1和虚拟图案DP通过对导电膜构图来形成，并且它们具有相同厚度。即，布线L1的高度几乎与虚拟图案DP的高度相同。焊盘PD通过穿透氧化硅膜20和氧化硅膜21的塞41与布线42电耦合。换言之，焊盘PD通过布线42和其下方的布线而与半导体元件电耦合。形成氧化硅膜22a使得覆盖顶布线层，以及在氧化硅膜22a之上形成TEOS的氧化硅膜23。此外，在氧化硅膜23之上形成氮化硅膜24。氧化硅膜22a、氧化硅膜23和氮化硅膜24构成表面保护膜(钝化膜)。表面保护膜旨在保护半导体芯片免受机械应力或杂质污染。因此，需要表面保护膜用作对机械强度或污染杂质(诸如移动离子)的屏幕障。例如，如图5所示，它是包括氧化硅膜22a、氧化硅膜23和氮化硅膜24的叠层。
在表面保护膜中制作达到焊盘PD的开口25，并且通过在开口25中埋入导电材料来形成塞SIL。与塞SIL电耦合的凸点电极BP1形成在表面保护膜之上。凸点电极BP1例如包括UBM(凸点下金属)膜26和金膜28。
大于焊盘PD的凸点电极BP1在表面保护膜之上延伸。因此，在平面图中，凸点电极BP1具有与焊盘PD重叠的重叠区X和不与焊盘重叠的非重叠区Y。布线L1位于非重叠区Y之下的层(顶布线层)中。此外，虚拟图案DP位于布线L1之间。因此，如果仅布线L1位于非重叠区Y之下的层(顶布线层)中，则将发生由于布线L1和空间之间的水平差造成的不规则性，并且反映水平差的表面保护膜将不规则。结果，形成在表面保护膜之上的凸点电极BP1的表面将不规则。然而，在该实施方式中，形成具有与布线L1相同高度的虚拟图案DP使得填充布线L1之间的空间，从而非重叠区Y之下的层(顶布线层)中的水平差可以减少。因此，改进了形成在顶布线层之上的表面保护膜的平坦性，并且也改进了形成在表面保护膜之上的凸点电极BP1的平坦性。
总之，该实施方式的一个特征(第一特征)在于，布线L1和虚拟图案DP形成在凸点电极BP1的非重叠区Y之下的层(顶布线层)中，并且虚拟图案具有与布线L1相同的高度并且位于布线L1之间的空间中，从而减少了顶布线层中的水平差。结果，增加了凸点电极BP1的平坦性。因此，在该实施方式中，布线L1(电源线或信号线)可以置于凸点电极BP1的非重叠区Y之下的层(顶布线层)中，使得可以有效使用大凸点电极BP1之下的区域。此外，可能由非重叠区Y之下的层(顶布线层)中的布线L1的存在造成的凸点电极BP1的平坦性的恶化通过用虚拟图案DP填满布线L1之间的空间来减轻。如上所述，根据该实施方式，半导体芯片可以变小，并且凸点电极BP1的平坦性可以增加，从而半导体芯片和衬底之间耦合的可靠性可以增加。
该实施方式的另一特征(第二特征)在于，使表面保护膜平坦化。如上所述，在顶布线层中与布线L1一起形成虚拟图案DP以减少顶布线层中的不规则性。然而，如图5所示，一些不规则性将在形成以覆盖顶布线层的氧化硅膜22a上保留。为了使表面保护膜更平坦，在氧化硅膜22a之上形成TEOS的氧化硅膜23。氧化硅膜23的表面通过化学机械抛光(CMP)平坦化。因此，作为表面保护膜的一部分的氧化硅膜23的表面被平坦化。总之，在顶布线层之上形成氧化硅膜22a之后，在氧化硅膜22a之上形成氧化硅膜23，并且其表面被平坦化以增加表面保护膜的平坦性。因为氮化硅膜24形成在已通过CMP平坦化的氧化硅膜23之上，所以它也是平坦的。因此，稳妥地增加了覆盖顶布线层的表面保护膜的平坦性。结果，凸点电极BP1形成在平坦的表面保护膜之上，并且保证了凸点电极BP1的平坦性。因为表面保护膜的表面是氮化硅膜24，所以可通过CMP抛光氮化硅膜24的表面而不是氧化硅膜23的表面。然而，因为其性质，氮化硅膜24不适于通过传统CMP工艺抛光。为此，通过CMP对氮化硅膜24下面的氧化硅膜23的表面平坦化。换言之，因为氧化硅膜23更易于通过CMP抛光，所以通过平坦化氧化硅膜23来平坦化表面保护膜。
如上所述，在该实施方式中，将用虚拟图案DP填充顶布线层的第一特征和通过CMP对覆盖顶布线层的表面保护膜平坦化的第二特征相结合以确保使形成在表面保护膜之上的凸点电极BP1平坦化。然而，不一定必须结合第一特征和第二特征；可以通过采用第一特征或第二特征来平坦化凸点电极BP1。
图6是沿图2的B-B线截取的截面图。如图6所示，顶布线层中的虚拟图案DP沿凸点电极BP1的阵列按行布置。这些虚拟图案DP在与布线L1相同的方向上延伸(图6未示出)，但它们是虚拟图案的阵列，而不像布线L1每个都是单线。每个虚拟图案DP是小矩形，其短边和长边小于每个布线L1的宽度。顶布线层中的空间用这种小矩形的虚拟图案DP填满。
使用小矩形的虚拟图案提供两个优点，下面将进行说明。第一优点是顶布线层中的空间可以充分地被填充，而不论空间尺寸如何。更具体地，多个布线L1形成在顶布线层中，并且某些相邻布线L1之间的间隔大于其他的间隔。如果虚拟图案尺寸与布线L1的宽度一样大，则布线之间的窄间隔不能用虚拟图案DP来填满。换言之，如果虚拟图案DP的短边和长边都小于布线L1的宽度，则即使较小的间隔(空间)也可以用虚拟图案DP来填满。由于虚拟图案DP较小，所以可用虚拟图案来填满各种形状的空间，而无需改变虚拟图案形式。
小虚拟图案DP的第二优点如下。例如，如果虚拟图案尺寸较大并且虚拟图案DP之间的间隔较宽，如图7所示，则形成为覆盖虚拟图案DP的氧化硅膜22a的表面不规则性的深度S1较大。从顶布线层中虚拟图案DP的目的是为了减少顶布线层中的不规则性的角度而言，这是不期望的。另一方面，如图8所示，如果虚拟图案尺寸较小并且虚拟图案DP之间的间隔较窄，则形成为覆盖虚拟图案DP的氧化硅膜22a的表面不规则性的深度S2较小。从顶布线层中虚拟图案DP的目的是为了减少顶布线层中的不规则性的角度而言，这是期望的。因此，较小的虚拟图案DP和较窄的虚拟图案DP之间的间隔更有利于增加凸点电极平坦性的目的。
在半导体芯片中用于输入信号的凸点电极BP1和顶布线层之间的位置关系已进行了说明。接下来，将说明用于输出信号的凸点电极BP2和顶布线层之间的位置关系。用于输出信号的凸点电极BP2和顶布线层之间的位置关系类似于用于输入信号的凸点电极BP1和顶布线层之间的位置关系。
图9是半导体芯片的一角及其附近的放大图。在图9中，水平方向表示半导体芯片CHP的长边方向，垂直方向表示芯片的短边方向。如图所示，用于输出信号的凸点电极BP2沿半导体芯片CHP的长边方向按行布置。特别地，用于输出信号的凸点电极BP2以Z字形图案布置在两行中。该布置允许许多凸点电极BP2沿芯片CHP的长边方向密集放置。
每个凸点电极BP2的形状为具有短边和长边的矩形，并且焊盘PD置于凸点电极BP2的一部分之下的顶布线层中。焊盘PD和凸点电极BP2通过塞SIL电耦合。在该实施方式中，凸点电极BP2大于焊盘和塞，并且通过小于焊盘PD的塞SIL而与小于凸点电极BP2的焊盘PD耦合。然而，凸点电极BP2的短边短于焊盘PD。这是因为，如果凸点电极BP2的短边长于焊盘PD，则凸点电极BP2的短边附近将具有不规则表面作为顶布线层中焊盘区域和非焊盘区域之间的水平差的反映。因此，为了确保凸点电极BP2的短边附近的平坦性，期望凸点电极BP2的整个短边位于焊盘PD上。
除了焊盘PD之外，在每个凸点电极BP2的长边之下有布线L1和虚拟图案DP。凸点电极BP2的长边远长于焊盘PD，这意味着顶布线层中凸点电极BP2之下存在一些空间。此外，将布线L1置于用于输出信号的凸点电极BP2之下，以便有效使用顶布线层中可用的空间。这些布线L1例如是电源线或信号线。布线L1恰好位于凸点电极BP2之下，并且沿半导体芯片CHP的长边(凸点电极BP2沿着该长边按行布置)延伸。
当以此方式在凸点电极BP2之下形成布线L1时，表面保护膜具有反映布线和空间之间的水平差的不规则表面；因此凸点电极BP2将形成在表面保护膜的不规则表面之上。结果，凸点电极BP2的表面将不是平坦的，而是不规则的。如果凸点电极BP2的表面是不规则的，则在将半导体芯片安装到玻璃衬底上时将存在一些困难。因此，凸点电极BP2的表面必须是平坦的。
因此，在该实施方式中，在放置布线L1的顶布线层中在用于输出信号的凸点电极BP2之下形成虚拟图案DP，如用于输入信号的凸点电极BP1的情况中那样。在图9的示例中，虚拟图案DP以填充该区域的方式放置在邻近布线L1的区域中。特别地，布线L1之间的空间用虚拟图案DP填满。因此，每个凸点电极BP2之下的空间用虚拟图案DP填满。换言之，多个布线L1以及在形成在布线L1之间的虚拟图案DP位于凸点电极BP2之下的顶布线层中。这减少了凸点电极BP2之下的层(顶布线层)中布线和空间之间的水平差。更具体地，具有几乎与布线L1相同高度的虚拟图案DP形成在凸点电极BP2之下的层(顶布线层)中可用的空间中，从而凸点电极BP2之下的层(顶布线层)中的水平差通过布线L1和虚拟图案而减少。
图10示出了不同于图9所示的虚拟图案DP的布置的示例。如图10所示，凸点电极BP2之下的层(顶布线层)由多条布线L1占据。换言之，布线L1密集布置，并且凸点电极BP2之下的层(顶布线层)中没有空间可用于虚拟图案DP。因此，在图10的示例中，看起来凸点电极BP2之下的层(顶布线层)中不存在水平差的问题。然而，如图10所示，在形成布线L1使得填充凸点电极BP2之下的区域的同时，在平面图中不与凸点电极BP2重叠的外围区域中没有形成布线L1。具体地，凸点电极BP2的外围区域包括在顶布线层中形成有布线L1的区域和没有布线的区域(空间)两种。因此，在布线L1和空间之间将存在水平差。为了确保凸点电极BP2的平坦性，减少每个凸点电极BP2之下的这种水平差是重要的。因为即使凸点电极BP2的外围区域中的水平差也会影响凸点电极BP2的平坦性，在顶布线层中也应该减少凸点电极BP2的外围区域中的该水平差。这是因为，在图10的示例中，虚拟图案DP也形成在邻近布线L1的区域(凸点电极BP2的外围区域)中。因此，凸点电极BP2的外围区域中的水平差在顶布线层中减少，并且保证了形成在顶布线层之上的凸点电极BP2的平坦性。
图11是沿图9中A-A线截取的截面图。如图11所示，布线42形成在作为层间绝缘膜的氧化硅膜40之上。该布线42通过塞43与其下方的布线耦合。尽管在形成在氧化硅膜40中的塞43之下的布线和半导体元件未在图11中示出，但多层布线和如MISFET的半导体元件形成在布线42之下。层间绝缘膜以覆盖布线42的方式形成。层间绝缘膜包括氧化硅膜20和形成在氧化硅膜20之上的TEOS(正硅酸乙酯)的氧化硅膜21。顶布线层形成在层间绝缘膜之上。顶布线层包括焊盘PD、布线L1和虚拟图案DP。焊盘PD、布线L1和虚拟图案DP通过对导电膜构图来形成，并且它们具有相同厚度。即，布线L1的高度几乎与虚拟图案DP的高度相同。每个焊盘PD通过穿透氧化硅膜20和氧化硅膜21的塞41而与布线42电耦合。换言之，焊盘PD通过布线42和其下方的布线而与半导体元件电耦合。形成氧化硅膜22a使得覆盖顶布线层，以及在氧化硅膜22a之上形成TEOS的氧化硅膜23。此外，在氧化硅膜23之上形成氮化硅膜24。氧化硅膜22a、氧化硅膜23和氮化硅膜24构成表面保护膜(钝化膜)。
在表面保护膜中制作达到焊盘PD的开口25，并且通过在开口25中埋入导电材料来形成塞SIL。与塞SIL电耦合的凸点电极BP2形成在表面保护膜之上。凸点电极BP2例如包括UBM(凸点下金属)膜26和金膜28。
大于焊盘PD的凸点电极BP2在表面保护膜之上延伸。因此，在平面图中，凸点电极BP2具有与焊盘PD重叠的重叠区X和不与焊盘重叠的非重叠区Y。布线L1位于非重叠区Y之下的层(顶布线层)中。此外，虚拟图案DP位于布线L1之间。因此，如果仅布线L1位于非重叠区Y之下的层(顶布线层)中，则将发生由于布线L1和空间之间的水平差造成的不规则性，并且反映水平差的表面保护膜将不规则。结果，形成在表面保护膜之上的凸点电极BP2的表面将不规则。然而，在该实施方式中，形成具有与布线L1相同高度的虚拟图案DP使得填充布线L1之间的空间，从而非重叠区Y之下的层(顶布线层)中的水平差可以减少。因此，改进了形成在顶布线层之上的表面保护膜的平坦性，并且也改进了形成在表面保护膜之上的凸点电极BP2的平坦性。
此外，该实施方式的一个特征在于，平坦化形成在用于输出信号的凸点电极BP2之下的表面保护膜。例如，通过化学机械抛光(CMP)或类似技术平坦化作为表面保护膜的一部分的氧化硅膜23的表面。因此，氧化硅膜23的表面被平坦化。总之，在顶布线层之上形成氧化硅膜22a之后，在氧化硅膜22a之上形成氧化硅膜23，并且氧化硅膜23的表面被平坦化以增加表面保护膜的平坦性。因为氮化硅膜24形成在已通过CMP平坦化的氧化硅膜23之上，所以氮化硅膜24也是平坦的。因此，稳妥地增加了覆盖顶布线层的表面保护膜的平坦性。结果，凸点电极BP2形成在平坦的表面保护膜之上，并且因此保证了凸点电极BP2的平坦性。
因此，该实施方式具有将用于输出信号的凸点电极BP2之下的顶布线层也用虚拟图案DP填满的第一特征以及通过CMP平坦化覆盖顶布线层的表面保护膜的第二特征。
该实施方式的第一特征是在用于输入信号的凸点电极BP1之下和用于输出信号的凸点电极BP2之下都形成虚拟图案DP。结果，顶布线层中的空间用虚拟图案填满并且覆盖顶布线层的表面保护膜具有较高平坦度，带来形成在表面保护膜之上的凸点电极BP1和BP2的较高平坦度。
因此，从应消除顶布线层中的布线L1和布线L1之间的空间之间的水平差的角度看，将会期望在整个半导体芯片上形成虚拟图案DP。换言之，为了增加覆盖顶布线层的表面保护膜的平坦性和形成在表面保护膜之上的凸点电极BP1的平坦性，将会期望形成虚拟图案以填充顶布线层中的全部空间。
然而，在该实施方式中，虚拟图案DP未遍布顶布线层形成。例如，图1示出半导体芯片CHP的顶布线层包括形成虚拟图案的虚拟图案区DR和未形成虚拟图案的非虚拟图案区NDR。虚拟图案区形成在离凸点电极BP1和BP2给定距离内。这是因为，为了实现凸点电极BP1和BP2的平坦化，将直接影响凸点电极BP1和BP2的平坦化的顶布线层中的水平差通过至少恰好在凸点电极BP1和BP2之下及其外围区域中形成虚拟图案来消除。简言之，为了实现凸点电极BP1和BP2的平坦化，不需要用虚拟图案填满顶布线层中全部空间。换言之，非虚拟图案区NDR不影响凸点电极BP1和BP2的平坦性。
在该实施方式中，出于以下原因，未在整个半导体芯片CHP表面之上提供虚拟图案区DR。第一个原因是为了便于半导体芯片缺陷分析。作为产品装载的LCD驱动器半导体芯片CHP可能包括一些有缺陷的产品。有缺陷的产品从客户处收集并进行缺陷分析。如果虚拟图案形成在顶布线层中全部空间中，则半导体芯片的内部被虚拟图案中使用的金属膜屏蔽。半导体元件和多层布线形成在半导体芯片CHP内部。当将对半导体元件和多层布线进行缺陷分析时，顶布线层中的虚拟图案可能妨碍这种缺陷分析。为此，虚拟图案不在整个顶布线层之上形成。因此，虚拟图案形成在离凸点电极BP1和BP2给定距离内。具体地，虚拟图案区DR在离凸点电极BP1和BP270μm内，并且其余部分是不形成虚拟图案的非虚拟图案区NDR，因此有助于方便缺陷分析。换言之，在该实施方式中，通过仅在影响凸点电极BP1和BP2的区域(顶布线层的一部分)中形成虚拟图案来增加凸点电极BP1和BP2的平坦性，并且通过在其他区域不形成虚拟图案来增强缺陷分析的便利性。
未在整个半导体芯片CHP表面之上提供虚拟图案区DR的第二原因如下。图12示出形成在半导体芯片CHP的顶布线层中的布线L1和虚拟图案DP占据该层的小于70％的情况。即，图12示出顶布线层中虚拟图案DP的比率较低的情况。图13是沿图12中A-A线截取的片断截面图，示出虚拟图案形成过程。如图13所示，从中形成布线L1和虚拟图案DP的导电膜位于作为层间绝缘膜的氧化硅膜21之上，并且构图的抗蚀剂膜RF形成在导电膜之上。进行抗蚀剂膜构图使得抗蚀剂膜留在要形成布线L1和虚拟图案DP的区域中。通过使用构图的抗蚀剂膜RF作为掩膜蚀刻导电膜来形成布线L1和虚拟图案DP。当虚拟图案DP的比率低到小于70％时，通过蚀刻移除的导电膜的比率较高。这意味着要蚀刻的面积较大。当要蚀刻的面积较大时，易于检测何时蚀刻结束。因此，可以准确检测蚀刻结束，这使得易于使布线L1和虚拟图案DP准确成形。
接下来，将说明形成在半导体芯片CHP的顶布线层中的布线L1和虚拟图案DP占据70％或更多的情况。图14示出形成在半导体芯片CHP的顶布线层中的布线L1和虚拟图案DP占据70％或更多的情况。即，图14示出顶布线层中虚拟图案DP的比率较高的情况。图15是沿图14中B-B线截取的片断截面图，示出了虚拟图案形成过程。
如图15所示，从中形成布线L1和虚拟图案DP的导电膜位于作为层间绝缘膜的氧化硅膜21之上，并且构图的抗蚀剂膜RF形成在导电膜之上。进行抗蚀剂膜构图使得抗蚀剂膜留在要形成布线L1和虚拟图案DP的区域中。通过使用构图的抗蚀剂膜RF作为掩膜蚀刻导电膜来形成布线L1和虚拟图案DP。当虚拟图案DP的比率较高或为70％或更多时，通过蚀刻移除的导电膜的比率较低。这意味着要蚀刻的面积较小。如果要蚀刻的面积较小，存在不能准确检测蚀刻结束的问题。该问题可能在普通蚀刻装置中出现。在普通蚀刻装置中，检测蚀刻结束的准确度依赖于要蚀刻的面积的尺寸而变化。
如果要蚀刻的面积较小并且不能准确检测蚀刻结束，则可能由于不足蚀刻或过度蚀刻而产生有缺陷的布线图案L1和有缺陷的虚拟图案DP。对该问题的一个解决方案可以是不基于实际蚀刻条件而是通过控制蚀刻时间来检测蚀刻结束。然而，蚀刻结果中的尺寸波动不可能通过控制蚀刻时间来完全避免。为此，蚀刻结束的检测不应该通过诸如控制蚀刻时间的间接方法而应该基于实际蚀刻条件。因此，为了增加检测蚀刻结束的准确度以改进虚拟图案形成准确度，如图1所示虚拟图案区DR不应该形成在整个半导体芯片CHP表面之上，并且顶布线层中虚拟图案所占据的面积比率应该较低。
如下进一步详述第二个原因。图16示出蚀刻形成在氧化硅膜21之上的导电膜22以形成构成顶布线层的布线和虚拟图案的过程。图16示出虚拟图案所占据的面积比率小于70％或者导电膜22的蚀刻面积较大的情况。为了蚀刻导电膜22，将诸如BCl3或Cl3的氯气用作蚀刻气体。这里，通过氯气和导电膜22的铝膜之间的化学反应来进行蚀刻。在该过程中，随着反应产物蒸发，铝膜逐渐被去除。当足量铝膜存在时，铝膜和蚀刻气体之间的化学反应进行平稳。因此，生成大量反应产物。铝膜蚀刻的进展可以通过检测来自反应产物的光发射(等离子体发射)来估计。更具体地，在蚀刻的初始阶段，足量铝存在，并且铝膜和蚀刻气体之间的化学反应进行平稳，并且生成大量反应产物。因此，在蚀刻的初始阶段，由于大量反应产物的存在，从反应产物发射大量光。
图17示出蚀刻的最终阶段，其中在图16所示阶段之后蚀刻已完成。如图17所示，导电膜22的构图已基本完成，并且导电膜22的铝膜的蚀刻已完成。此时，因为剩下少量铝膜，所以铝膜和蚀刻气体之间的化学反应远小于图16所示初始阶段。因此，来自铝膜和蚀刻气体之间的化学反应的反应产物的量较小，并且从反应产物发射的光量也较小。即，在蚀刻的最终阶段，从反应产物发射的光量较小。因此，蚀刻结束可以通过在蚀刻过程中监控从反应产物发射的光量来检测。当从反应产物发射的光量变得低于指定水平时，可以判定蚀刻已结束。如果蚀刻面积如图16和图17所示较大，则蚀刻的初始阶段和最终阶段之间的光强差较大，并且可以准确检测蚀刻结束。
接下来，图18示出虚拟图案所占据的面积比率是70％或更多或者要蚀刻的导电膜22的面积较小的情况。在这种情况下，如图18所示，因为要蚀刻的面积较小，即使在蚀刻的初始阶段，发射光的强度也较低。更具体地，在蚀刻的初始阶段，剩下足量的导电膜，但不被抗蚀剂膜RF覆盖的要蚀刻的面积非常小；因此，铝膜和蚀刻气体之间的化学反应比虚拟图案所占据的面积比率小于70％的时候要少。为此，即使在蚀刻的初始阶段，反应产物的量也较小，并且从反应产物发射的光强也较低。
接着，蚀刻进行并结束。图19示出蚀刻的最终阶段，其中在图18所示阶段之后蚀刻已完成。如图19所示，要蚀刻的导电膜的几乎所有铝膜被去除，并且铝膜和蚀刻气体之间的化学反应不活跃，并且反应产物的量较小。因此，从反应产物发射的光强较弱。当虚拟图案所占据的面积比率是70％或更多时，如图18和图19所示，要蚀刻的面积较小，并且即使在蚀刻的初始阶段，来自蚀刻的反应产物的量也较小，因此光的量(强度)较小(低)。这意味着当虚拟图案所占据的面积比率是70％或更多时，蚀刻的初始阶段和最终阶段之间存在较小光强差。因此，难以准确检测蚀刻结束。如果不能准确检测蚀刻结束，则产生可能由于不足蚀刻或过度蚀刻而产生有缺陷的布线图案和有缺陷的虚拟图案的问题。为此，期望避免在顶布线层中形成太多虚拟图案。总之，为了增加检测蚀刻结束的准确度以改进虚拟图案形成准确度，如图1所示虚拟图案区DR不应该形成在整个半导体芯片CHP之上，并且顶布线层中虚拟图案所占据的面积比率应该较低。
导电膜22包括铝膜，其被上部钛/氮化钛膜和下部钛/氮化钛膜夹在中间。通常，钛/氮化钛膜的蚀刻不根据反应产物的发射光强而是根据蚀刻时间来控制。因此，如果准确检测铝膜的蚀刻结束，则钛/氮化钛膜可以在指定蚀刻时间内完全去除；另一方面，如果不能准确检测蚀刻结束，则铝膜的不足蚀刻或过度蚀刻将发生，即，当持续指定时间进行蚀刻时，钛/氮化钛膜的不足蚀刻或过度蚀刻可能发生。这表示，为了准确处理导电膜22，准确检测蚀刻结束是重要的。
为此，将顶布线层中虚拟图案区的比率限于平坦化凸点电极所需的值。换言之，避免顶布线层中太多虚拟图案的形成所带来的缺点。
该实施方式的特征简要概述如下。第一特征是在顶布线层中形成虚拟图案，第二特征是通过CMP平坦化覆盖顶布线层的表面保护膜。具体地，仅在凸点电极之下以及其周围中形成虚拟图案，或者到实现第一特征所需的范围，以消除将直接影响凸点电极的平坦性的水平差。
该实施方式的技术思想(第一特征)是在顶布线层中形成虚拟图案。在普通半导体器件中，虚拟图案形成在多层布线层的中间布线层中。这是因为，另一布线层必须制造在多层布线层的中间层之上，并且中间层必须平坦化。然而，现有技术没有在顶布线层中形成虚拟图案的技术思想。因为不需要在顶布线层之上形成布线层，所以不存在必须减少由顶布线层中布线造成的水平差的思想。即，不需要准确地平坦化顶布线层。
另一方面，该实施方式中的半导体器件假设为LCD驱动器。LCD驱动器特征在于通过表面保护膜在顶布线层中形成较大凸点电极。在这种情况下，将布线置于较大凸点电极之下，以便有效使用凸点电极之下的层(顶布线层)。因此，在凸点电极之下的顶布线层中形成布线和空间，并且产生布线和空间之间的水平差。这些水平差反映在覆盖顶布线层的表面保护膜中，导致表面保护膜表面的不规则性。因为形成在表面保护膜之上的凸点电极较大，因此作为表面保护膜的不规则表面的反映，凸点电极的表面也不规则。在该实施方式中，作为对该问题的解决方案，在顶布线层中形成虚拟图案以确保凸点电极的表面平坦性(第一特征)。因此，现有技术的技术思想，即在中间层中形成虚拟图案，在前提和目标方面，不同于该实施方式的思想。现有技术仅暗示在中间层中形成虚拟图案，不包含启发本领域技术人员构思该实施方式的第一特征的思想。
该实施方式的第二特征(技术思想)是通过CMP平坦化覆盖顶布线层的表面保护膜。多层布线层的中间层的表面通过CMP抛光的技术已是普遍使用的，因为需要平坦化层间绝缘膜以在中间层之上形成另一布线层。然而，该现有技术不包含应该对形成为覆盖顶布线层的表面保护膜平坦化的思想。这是因为，不需要在表面保护膜之上形成布线层，因此不需要平坦化表面保护膜。
另一方面，在该实施方式中的半导体器件假设为LCD驱动器。LCD驱动器特征在于通过表面保护膜在顶布线层中形成较大凸点电极。在这种情况下，将布线置于较大凸点电极之下，以有效使用凸点电极之下的层(顶布线层)。因此，在凸点电极之下的顶布线层中形成布线和空间，并且产生布线和空间之间的水平差。这些水平差反映在覆盖顶布线层的表面保护膜中，导致表面保护膜表面的不规则性。因为形成在表面保护膜之上的凸点电极较大，所以作为表面保护膜的不规则表面的反映，凸点电极的表面也不规则。在该实施方式中，作为对该问题的解决方案，将表面保护膜的表面通过CMP平坦化。因此，现有技术的技术思想，即层间绝缘膜表面通过CMP平坦化，在前提和目标方面，不同于该实施方式的思想。现有技术仅暗示通过CMP平坦化中间层，不包含启发本领域技术人员构思该实施方式的第二特征的思想。
以上已描述该实施方式的特征。该实施方式的特征在于半导体芯片的顶布线层以及其位于顶布线层之上的表面保护膜。在半导体芯片的顶布线层之下的层中形成布线，并且在布线之下半导体衬底之上形成半导体元件。该实施方式中的半导体芯片是LCD驱动器。LCD驱动器具有将输入信号(串行数据)转换成输出信号(并行数据)的功能，以及作为电平移动电路的功能，其改变LCD驱动器内部的电压值以将指定水平的电压施加到液晶显示器元件(像素)。这些LCD驱动器功能通过形成在半导体芯片中的CMISFET(互补型金属绝缘体半导体场效应晶体管)来执行。存在两种CMISFET用于LCD驱动器：在较低电压操作的低电压CMISFET和在较高电压操作的高电压CMISFET。接下来，将描述CMISFET及其第一布线层。
图20是在该实施方式中半导体芯片中形成的CMISFET的截面图。如图20所示，元件隔离区2形成在单晶硅半导体衬底1S的表面中。构成半导体元件的有源区被元件隔离区2分隔。在被元件隔离区2分隔的有源区中，将p型阱3a形成在n沟道MISFET形成区中，并且将n型阱3b形成在p沟道MISFET形成区中。
n沟道MISFET形成在p型阱3a之上，并且p沟道MISFET形成在n型阱3b之上。首先，描述n沟道MISFET。n沟道MISFET具有在p型阱3a之上的栅绝缘膜4，并且栅电极6a形成在栅绝缘膜4之上。栅电极6a是包括多晶硅膜5和形成在多晶硅膜5之上的硅化钴膜12的叠层。形成硅化钴膜12以减少栅电极6a的电阻。
侧壁9形成在栅电极6a的两侧上，并且浅低浓度n型杂质扩散区7形成在半导体衬底1S中恰好在每个侧壁9之下。该浅低浓度n型杂质扩散区7是半导体区，其中诸如磷和砷的n型杂质被引入半导体衬底1S，并且其以匹配栅电极6a的方式形成。在半导体衬底1S中，深高浓度n型杂质扩散区10形成在浅低浓度n型杂质扩散区7外部。该深高浓度n型杂质扩散区10也是半导体区，其中诸如磷和砷的n型杂质引入半导体衬底1S，并且其以匹配侧壁9的方式形成。
浅低浓度n型杂质扩散区7和深高浓度n型杂质扩散区10构成用于n沟道MISFET的源区和漏区。当浅低浓度n型杂质扩散区7和深高浓度n型杂质扩散区10以此方式形成用于源区和漏区的每个时，源区和漏区具有轻掺杂漏极(LDD)结构，从而防止栅电极6a端部之下的电场集中。硅化钴膜12形成在深高浓度n型杂质扩散区10的表面之上。形成硅化钴膜12以减少源区和漏区的电阻。
接下来，描述p沟道MISFET。p沟道MISFET具有在n型阱3b之上的栅绝缘膜4，并且栅电极6b形成在栅绝缘膜4之上。栅电极6b是包括多晶硅膜5和形成在多晶硅膜5之上的硅化钴膜12的叠层。形成硅化钴膜12以减少栅电极6b的电阻。
侧壁9形成在栅电极6b的两侧上，并且浅低浓度p型杂质扩散区8形成在半导体衬底1S中恰好在每个侧壁9之下。该浅低浓度p型杂质扩散区8是半导体区，其中诸如硼的p型杂质引入半导体衬底1S，并且其以匹配栅电极6b的方式形成。在半导体衬底1S中，深高浓度p型杂质扩散区11形成在浅低浓度p型杂质扩散区8外部。该深高浓度p型杂质扩散区11也是半导体区，其中诸如硼的p型杂质引入半导体衬底1S，并且其以匹配侧壁9的方式形成。
浅低浓度p型杂质扩散区8和深高浓度p型杂质扩散区11构成用于p沟道MISFET的源区和漏区。当浅低浓度p型杂质扩散区8和深高浓度p型杂质扩散区11以此方式形成用于源区和漏区的每个时，源区和漏区具有轻掺杂漏极(LDD)结构，从而防止栅电极6b端部之下的电场集中。硅化钴膜12形成在深高浓度p型杂质扩散区11的表面之上。形成硅化钴膜12以减少源区和漏区的电阻。
接下来，将描述用于与CMISFET耦合的布线结构。层间绝缘膜13(氧化硅膜)形成在CMISFET之上以覆盖CMISFET。在层间绝缘膜13中制作接触孔14以穿透层间绝缘膜13并且到达其中形成源区和漏区的硅化钴膜12。在接触孔14内部，钛/氮化钛膜15a作为阻挡导电膜形成，并且在接触孔14中埋入钨膜15b。通过以此方式在接触孔14中埋入钛/氮化钛膜15a和钨膜15b产生导电塞16。布线18形成在层间绝缘膜13之上，并且该布线18和塞16电耦合。布线18例如是包括钛/氮化钛膜17a、铝膜17b和钛/氮化钛膜17c的叠层。层间绝缘膜19形成在布线18之上。
此外，多层布线层形成在层间绝缘膜19之上，并且上述顶布线层形成在其顶部。图5和图6示出形成在顶布线层上的内容。该实施方式中的半导体器件(LCD驱动器)如上所述构造。
接下来，将简要说明在该实施方式中如此构造的CMISFET如何操作。取n沟道MISFET作为说明CMISFET的操作的例子。首先，说明n沟道MISFET如何导通。随着阈值以上的指定电压被施加到栅电极6a，作为n型半导体区的沟道形成在半导体衬底1S(p型阱3a)的表面中恰好在栅电极6a之下。这里，因为源区和漏区是n型半导体区，所以源区和漏区通过该沟道电耦合。因此，当源区和漏区之间的电势差给出时，电流在源区和漏区之间流动。这样导通了n沟道MISFET。
接下来，说明n沟道MISFET如何截止。随着阈值以下的指定电压被施加到栅电极6a，形成在半导体衬底1S(p型阱3a)的表面中栅电极6a之下的沟道消失。随着沟道消失，已通过沟道电耦合的源区和漏区彼此电隔离。因此，电流在源区和漏区之间停止流动。这样截止了n沟道MISFET。通过以此方式导通和截止n沟道MISFET，LCD驱动器的集成电路以指定方式操作。
接下来，将参照附图描述根据该实施方式的半导体器件(LCD驱动器)的制造方法。图21是示出制造CMISFET的序列的流程图。首先，将参照图20和图21描述形成CMISFET和第一布线层的过程。
首先，制备掺杂有诸如硼(B)的p型杂质的单晶硅半导体衬底1S。此时，半导体衬底1S是基本盘形的半导体晶片。接着，将元件隔离区2形成在半导体衬底1S的CMISFET形成区中(S101)。元件隔离区2旨在防止元件彼此干扰。可以例如使用LOCOS(硅的局部氧化)或STI(浅沟槽隔离)方法形成元件隔离区2。在使用STI方法的情况下，如下形成元件隔离区2。通过光刻和蚀刻制作元件隔离沟槽。接着，将氧化硅膜形成在半导体衬底1S之上以填充元件隔离沟槽，并且将半导体衬底1S之上不需要的氧化硅膜通过化学机械抛光(CMP)去除。因此，产生具有仅在元件隔离沟槽中埋入的氧化硅膜的元件隔离区2。
接下来，通过在由元件隔离区隔离的有源区中引入杂质来形成阱(S102)。例如，将p型阱3a形成在作为有源区的n沟道MISFET形成区中，并且将n型阱3b形成在作为有源区的p沟道MISFET形成区中。通过离子注入引入诸如硼的p型杂质来形成p型阱3a。类似地，通过离子注入引入诸如磷(P)或砷(As)的n型杂质来形成n型阱3b。
接下来，在p型阱和n型阱的表面之上形成用于沟道的半导体区(未示出)。用于沟道的半导体区旨在控制用于沟道形成的阈值。
接下来，在半导体衬底1S之上形成栅绝缘膜4(S103)。栅绝缘膜4例如是可以通过热氧化或类似技术制造的氧化硅膜。栅绝缘膜4的材料不限于氧化硅，而可以是其他各种材料中的一种，例如氮氧化硅(SiON)。其可以是栅绝缘膜4和半导体衬底1S之间界面中的氮化物沉淀。氮氧化硅膜在减少界面状态密度和减少电子陷阱方面比氧化硅膜更有效。因此，其增加栅绝缘膜4的热载流子可靠性并增强介电强度。此外，氮氧化硅膜比氧化硅膜对杂质而言较不容易穿透。因此，将氮氧化硅膜用于栅绝缘膜4使得由栅电极中杂质扩散到半导体衬底中造成的阈值电压波动最小化。可以例如通过在包括NO、NO2或NH3的氮气环境中热处理半导体衬底1S来形成氮氧化硅膜。可以通过以下方式实现类似效果：在半导体衬底1S的表面之上形成氧化硅的栅绝缘膜4，然后在氮气环境中热处理半导体衬底1S以在栅绝缘膜4和半导体衬底1S之间的界面中引入氮化物沉淀。
可替换地，栅绝缘膜4可以是高介电常数膜，其具有比氧化硅膜高的介电常数。过去，将氧化硅膜用于栅绝缘膜4，原因是其提供高介电强度，并且硅和氧化硅之间的界面是电学和物理上稳定的。然而，随着微观器件的发展趋势，需要很薄的栅绝缘膜4。如果很薄的氧化硅膜用于栅绝缘膜4，则可能产生所谓的隧道电流，其中在MISFET沟道中流动的电子通过由氧化硅膜形成的势垒流到栅电极。
为此，存在使用具有比氧化硅高的介电常数的材料的发展趋势，该材料在提供相同电容的同时可以较厚。因为高介电常数膜即使当其较厚时也可以提供相同电容，所以可以减少泄漏电流。
例如，在该例子中，使用氧化铪(HfO2)膜作为高介电常数膜。代替氧化铪膜，可以使用其他铪膜，例如铝酸铪膜、HfON(氮氧化铪膜)、HfSiO膜(硅酸铪膜)、HfSiON(氮氧化硅铪膜)和HfAlO膜。此外，这些铪绝缘材料可以与其他各种氧化物组合，例如氧化钽、氧化铌、氧化钛、氧化锆、氧化镧和氧化钇，以制备铪绝缘膜。因为这些铪绝缘膜像氧化铪膜一样，提供比氧化硅膜或氮氧化硅膜高的介电常数，所以它们实现与使用氧化铪膜时相同的效果。
接下来，在栅绝缘膜4之上形成多晶硅膜5。多晶硅膜5可以通过CVD或类似技术形成。接着，将诸如磷或砷的n型杂质通过光刻和离子注入引入形成在n沟道MISFET形成区中的多晶硅膜5中。类似地，将诸如硼的p型杂质引入形成在p沟道MISFET形成区中的多晶硅膜5中。
接下来，使用已构图的抗蚀剂膜作为掩模蚀刻多晶硅膜5以在n沟道MISFET形成区中形成栅电极6a以及在p沟道MISFET形成区中形成栅电极6b(S104)。
这里，将n型杂质引入n沟道MISFET形成区中的栅电极6a的多晶硅膜5中。因此，栅电极6a的功函数值可以是硅的导带(4.15eV)附近的值，并且可以减少用于n沟道MISFET的阈值电压。另一方面，将p型杂质引入p沟道MISFET形成区中的栅电极6b的多晶硅膜5中。因此，栅电极6b的功函数值可以是硅的价带(5.15eV)附近的值，并且可以减少用于p沟道MISFET的阈值电压。以此方式，在该实施方式1中，可以减少用于n沟道MISFET和p沟道MISFET二者的阈值电压(双栅结构)。
接下来，通过光刻和离子注入形成浅低浓度n型杂质扩散区7，其匹配n沟道MISFET的栅电极6a。浅低浓度n型杂质扩散区7是半导体区。类似地，在p沟道MISFET形成区中形成浅低浓度p型杂质扩散区8。形成浅低浓度p型杂质扩散区8以匹配p沟道MISFET的栅电极6b。可以通过光刻和离子注入形成浅低浓度p型杂质扩散区8(S105)。
接下来，在半导体衬底1S之上形成氧化硅膜。可以通过CVD或类似技术形成氧化硅膜。通过氧化硅膜的各向异性蚀刻，形成侧壁9作为栅电极6a和6b的侧壁(S106)。尽管使用氧化硅的单层膜形成侧壁9，但侧壁9不限于此，并且也可以将包括氮化硅和氧化硅膜的叠层用于侧壁。
接着，通过光刻和离子注入在n沟道MISFET形成区中形成深高浓度n型杂质扩散区10，其匹配侧壁9(S107)。深高浓度n型杂质扩散区10是半导体区。深高浓度n型杂质扩散区10和浅低浓度n型杂质扩散区7构成源区。类似地，深高浓度n型杂质扩散区10和浅低浓度n型杂质扩散区7构成漏区。当源区和漏区各以此方式包括浅n型杂质扩散区和深n型杂质扩散区时，源区和漏区具有LDD(轻掺杂漏极)结构。
类似地，在p沟道MISFET形成区中形成深高浓度p型杂质扩散区11，其匹配侧壁9。深高浓度p型杂质扩散区11和浅低浓度p型杂质扩散区8构成源区和漏区。因此，在p沟道MISFET中，源区和漏区也具有LDD结构。
在如此形成深高浓度n型杂质扩散区10和深高浓度p型杂质扩散区11之后，在1000℃左右进行热处理以激活引入的杂质。
此后，在半导体衬底之上形成钴膜，方式为其直接接触栅电极6a和6b。同样，钴膜直接接触深高浓度n型杂质扩散区10和深高浓度p型杂质扩散区11。
可以通过溅射或类似技术制作钴膜。通过在形成钴膜之后进行热处理，引起栅电极6a(6b)的多晶硅膜5和钴膜之间的反应以形成硅化钴膜12(S108)。因此，栅电极6a(6b)变成包括多晶硅膜5和硅化钴膜12的叠层。硅化钴膜12旨在减少栅电极的电阻。同样，如上所述热处理引起深高浓度n型杂质扩散区10和深高浓度p型杂质扩散区11的每个的表面中的硅和钴膜之间的反应以形成硅化钴膜12。因此，深高浓度n型杂质扩散区10和深高浓度p型杂质扩散区11中电阻也减少。
未反应的钴被从半导体衬底1S移除。也可以形成硅化镍膜或硅化钛膜来代替该实施方式1中的硅化钴膜12。
接下来，在半导体衬底1S的主表面之上形成用于层间绝缘膜13的氧化硅膜(S109)。该氧化硅膜可以通过CVD(化学气相沉积)形成，使用例如TEOS(正硅酸乙酯)作为其材料。然后，通过CMP或类似技术平坦化氧化硅膜的表面。
接下来，通过光刻和蚀刻在氧化硅膜中制作接触孔14。接着，在接触孔14的氧化硅膜上形成钛/氮化钛膜15a，包括其底部和内壁。钛/氮化钛膜15a是包括钛膜和氮化钛膜的叠层，并且可以通过溅射或类似技术形成。钛/氮化钛膜15a用作防止钨扩散到硅中的阻挡层，钨是用于在下一步骤中要埋入的膜的材料。
接下来，以填充接触孔14的方式，在半导体衬底1S的整个主表面上形成钨膜15b。该钨膜15b可以通过CVD或类似技术形成。通过CMP或类似技术移除氧化硅膜之上不需要的钛/氮化钛膜15a和钨膜15b的部分来形成塞16(S110)。
接下来，在氧化硅膜和塞16之上相继形成钛/氮化钛膜17a、包含铜的铝膜17b以及钛/氮化钛膜17c。可以通过溅射或类似技术形成这些膜。然后，通过光刻和蚀刻对这些膜构图以形成布线18(S111)。此外，在布线之上形成布线以形成多层布线。以此方式将多层布线形成在半导体衬底1S之上。
接下来，将参照附图描述形成多层布线层的顶布线层的过程的步骤。如图22所示，首先，形成层间绝缘膜。层间绝缘膜是包括氧化硅膜20和氧化硅膜21的叠层。可以通过等离子体CVD(化学气相沉积)或类似技术来形成氧化硅膜20。对于氧化硅膜21，使用TEOS作为材料。
接下来，在氧化硅膜21之上形成导电膜22。导电膜例如是铝膜，其可以通过溅射或类似技术形成。实际上，在导电膜22中，铝膜夹在上部钛/氮化钛膜和下部钛/氮化钛膜之间。如图23所示，通过光刻和蚀刻处理导电膜22。通过处理导电膜22，在氧化硅膜21之上形成顶布线层。例如，顶布线层包括焊盘PD、布线L1和虚拟图案DP。虚拟图案DP形成在布线L1之间的空间中。虚拟图案DP与布线L1位于同一层中，减少了布线L1和空间之间的水平差。
接下来，如图24所示，形成覆盖顶布线层的氧化硅膜22a。可以通过等离子体CVD或类似技术形成氧化硅膜22a。虚拟图案DP形成在顶布线层中以填充布线L1之间的空间，减少了反映氧化硅膜22a的不规则表面的不规则性。换言之，因为虚拟图案DP填充布线L1之间的空间，所以减少了氧化硅膜22a的表面不规则性。
然后，如图25所示，在氧化硅膜22a之上形成氧化硅膜23。例如，氧化硅膜23可以使用TEOS作为其材料通过CVD形成。然后，如图26所示，通过CMP(化学机械抛光)或类似技术平坦化氧化硅膜23的表面。CMP是一种抛光技术，其中将半导体衬底表面压在研磨垫上，同时包含硅石微粒的研磨液(浆)在半导体衬底上流动。该技术使用化学机制来用浆氧化要抛光的材料的表面以及机械机制来机械地削去氧化的层。
位于氧化硅膜23之下的氧化硅膜22a由于虚拟图案DP而具有较规则表面。因此，形成在氧化硅膜22a之上的氧化硅膜23也具有较规则表面。(通过CMP)抛光氧化硅膜23以平坦化其表面的过程较容易，因为氧化硅膜23具有较规则表面。即，在顶布线层中形成虚拟图案DP使得易于在后面步骤中平坦化氧化硅膜23。
接下来，如图27所示，在氧化硅膜23之上形成氮化硅膜24。可以通过等离子体CVD或类似技术形成氮化硅膜24。由此在顶布线层之上形成包括氧化硅膜22a、氧化硅膜23和氮化硅膜24的表面保护膜。
接下来，如图28所示，通过光刻和蚀刻在表面保护膜中制作开口25。该开口25形成在焊盘PD之上以露出焊盘PD表面。开口的尺寸小于焊盘PD的尺寸。
接下来，如图29所示，在包括开口25的内部的表面保护膜之上形成UBM(凸点下金属)膜26。UBM膜26可以通过溅射或类似技术形成。UBM膜26是单层膜，或者是包括钛膜、镍膜、钯膜、钛-钨合金膜、氮化钛膜和/或金膜的叠置膜。UBM膜26不仅具有改进凸点电极到焊盘和表面保护膜的粘合的功能，而且具有阻挡功能，用于抑制或防止在后面步骤中形成的金膜的金属元素向布线L1等的移动，或者布线L1等的金属元素向金膜的移动。
接下来，如图30所示，在将抗蚀剂膜27涂覆在UBM膜26上之后，通过曝光和显影在抗蚀剂膜27上进行构图。构图必须使得在凸点电极形成区中不剩下抗蚀剂膜27。然后，如图31所示，通过镀覆形成金膜28。金膜28位于表面保护膜(氮化硅膜24)之上，并且还埋入开口25中。当金膜28埋入开口25中时，完成塞SIL。
然后，如图32所示，通过去除已构图的抗蚀剂膜27和由抗蚀剂膜27覆盖的UBM膜26，形成包括金膜28和UBM膜26的凸点电极BP1。凸点电极BP1大于焊盘PD，并且布线L1位于凸点电极BP1之下的顶布线层中。凸点电极BP1之下布线L1的存在允许有效使用凸点电极之下的空间，导致较小半导体器件。此外，当除了作为电源线或信号线的布线L1之外，虚拟图案DP位于凸点电极BP1之下时，增加了形成在顶布线层之上的表面保护膜的平坦性。换言之，如果仅电源线和信号线(布线L1)形成在多层布线层的顶层中，则由电源线和信号线(布线L1)造成的表面不规则性将很严重，因为顶布线层不可能密集地填满布线。通过在该层中形成虚拟图案DP以及布线，增加了顶布线层的平坦性。此外，因为通过CMP平坦化表面保护膜的表面，保证了形成在顶布线层之上的表面保护膜的平坦性，并且增加了形成在表面保护膜之上的凸点电极的平坦性。此后，通过切割半导体衬底获得单个半导体芯片。
接下来，通过键合(bond)将由上述工艺获得的半导体芯片安装到安装衬底上。图33示出半导体芯片CHP安装到玻璃衬底30上(COG：玻璃上芯片)。如图33所示，将玻璃衬底31安装到玻璃衬底30上，从而形成LCD屏幕。半导体芯片CHP，即LCD驱动器，安装到玻璃衬底30上，靠近LCD屏幕。凸点电极BP1和BP2形成在半导体芯片CHP中，并且凸点电极BP1和BP2通过ACF(各向异性导电膜)与形成在玻璃衬底30之上的端子耦合。玻璃衬底30和柔性印刷电路板32也通过ACF耦合。在安装到玻璃衬底30上的半导体衬底CHP中，用于输出信号的凸点电极BP2与LCD屏幕电耦合，用于输入信号的凸点电极BP1与柔性印刷电路板32电耦合。
图34以放大形式示出安装到玻璃衬底30上的半导体衬底CHP。如图34所示，端子30a形成在玻璃衬底30之上，并且这些端子30a与凸点电极BP1和BP2电耦合。凸点电极BP1和BP2与端子30a彼此不直接接触，而是通过ACF耦合。ACF是通过混合导电精细金属微粒33与热固树脂以及将混合物成形为隔膜来制造的膜。每个金属微粒33是具有3-5μm直径的球形体，包括镍层和金涂层作为其内层以及绝缘层作为其最外层。
当半导体芯片安装到玻璃衬底30上时，在玻璃衬底30的端子30a和半导体芯片CHP的凸点电极BP1和BP2之间放置ACF。当通过加热器等施加热使半导体芯片CHP受压时，压力仅施加到凸点电极BP1和BP2所处的区域。这使得ACF中分散的金属微粒33彼此接触和重叠并且彼此推挤。结果，通过金属微粒33在ACF中产生导电通路。因为压力没有施加到的ACF的金属微粒保持它们的表面绝缘层，所以保持相邻凸点电极BP1之间的绝缘和相邻凸点电极BP2之间的绝缘。这提供了即使当凸点电极BP1或BP2之间的间隔较窄时，半导体芯片CHP安装到玻璃衬底30上也不会造成短路的优点。
在该实施方式1中，在半导体芯片中，虚拟图案形成在顶布线层中，并且通过CMP平坦化覆盖顶布线层的表面保护膜。因此，增加了形成在表面保护膜之上的凸点电极的平坦化。这确保了全部凸点电极完全接触各向异性导电膜中的金属微粒。这改进了半导体芯片的凸点电极和安装衬底的端子(布线)之间耦合的可靠性。
图35示出LCD(液晶显示器件35)的普通结构。如图35所示，LCD屏幕34形成在玻璃衬底上，其中图像出现在该屏幕34上。作为LCD驱动器的半导体芯片CHP安装到玻璃衬底上屏幕34附近。柔性印刷电路板32安装在半导体芯片CHP附近，并且作为驱动器的半导体芯片置于柔性印刷电路板32和LCD屏幕34之间。半导体芯片CHP由此安装到玻璃衬底上。作为LCD驱动器的半导体芯片CHP由此安装到液晶显示器件35上。
至此由本发明人作出的本发明已参照其优选实施方式进行了具体描述。然而，本发明不限于该实施方式，并且显然本发明可以以各种方式修改，而不脱离其精神和范围。
本发明可以广泛用于半导体器件制造工业。

Claims (15)

1.一种半导体器件，包括：
(a)半导体衬底；
(b)半导体元件，形成在所述半导体衬底之上；
(c)多层布线层，形成在所述半导体元件之上；
(d)焊盘，形成在所述多层布线层的顶层中；
(e)表面保护膜，形成在所述焊盘之上，并具有达到所述焊盘的开口；以及
(f)凸点电极，形成在所述表面保护膜之上，并通过填充所述开口而与所述焊盘电耦合，
其中所述凸点电极大于所述焊盘，从而具有在平面图上与所述焊盘重叠的重叠区和在平面图上不与所述焊盘重叠的非重叠区，
其中在与所述焊盘的同一层中，还形成包括电源线或信号线的第一布线以及不同于所述第一布线的虚拟图案，
其中所述第一布线和所述虚拟图案布置在所述凸点电极的非重叠区之下，
其中所述虚拟图案是矩形图案，以及
其中所述虚拟图案的两边的每个宽度小于所述第一布线的宽度。
2.根据权利要求1所述的半导体器件，其中所述虚拟图案包括多个图案。
3.根据权利要求2所述的半导体器件，其中所述多个图案中的每个图案具有短边和长边。
4.根据权利要求1所述的半导体器件，其中所述表面保护膜的表面被平坦化。
5.根据权利要求4所述的半导体器件，其中所述表面保护膜包括通过等离子体CVD形成的第一氧化硅膜、形成在所述第一氧化硅膜之上的TEOS的第二氧化硅膜以及形成在所述第二氧化硅膜之上的氮化硅膜。
6.根据权利要求5所述的半导体器件，其中所述第二氧化硅膜被平坦化。
7.根据权利要求1所述的半导体器件，其中所述半导体器件是用于液晶显示器的LCD驱动器。
8.一种半导体器件，包括在平面图中具有长边和短边的矩形半导体芯片，
所述半导体芯片包括：
(a)半导体衬底，为具有短边和长边的矩形形状；
(b)半导体元件，形成在所述半导体衬底之上；
(c)多层布线层，形成在所述半导体元件之上；
(d)多个焊盘，形成在所述多层布线层的顶层中；
(e)表面保护膜，形成在所述焊盘之上并具有分别达到所述焊盘的多个开口；以及
(f)多个矩形凸点电极，形成在所述表面保护膜之上并通过填充所述开口而与所述焊盘电耦合，
其中在与所述焊盘的同一层中，还形成包括电源线或信号线的第一布线以及不同于所述第一布线的第一虚拟图案；
其中所述凸点电极至少在沿所述半导体芯片的长边方向的第一方向中按行布置，其中所述凸点电极的长边平行于沿所述半导体芯片的短边方向的第二方向；
其中每个所述凸点电极大于每个所述焊盘，从而具有在平面图上与对应焊盘重叠的重叠区和在平面图上不与所述对应焊盘重叠的非重叠区；
其中所述第一布线沿所述第一方向延伸并且布置在所述凸点电极的非重叠区之下；
其中所述第一虚拟图案分别形成于在平面图上与所述凸点电极不重叠、且在平面图上位于所述凸点电极的非重叠区之间的区域中；
其中所述第一虚拟图案是矩形图案；以及
其中所述第一虚拟图案的两边的每个宽度小于所述第一布线的宽度。
9.根据权利要求8所述的半导体器件，
其中在平面图上第二虚拟图案分别布置在所述凸点电极的非重叠区之下；
其中所述第二虚拟图案是矩形图案；以及
其中所述第二虚拟图案的两边的每个宽度小于所述第一布线的宽度。
10.根据权利要求8所述的半导体器件，
其中在平面图中相邻的所述第一虚拟图案之间的间隔小于所述第一虚拟图案的每个短边。
11.一种制造半导体器件的方法，包括以下步骤：
(a)在半导体衬底之上形成半导体元件；
(b)在所述半导体元件之上形成多层布线层；
(c)在所述多层布线层的顶层中形成导电膜；
(d)通过对所述导电膜构图，形成焊盘、包括电源线或信号线的第一布线以及虚拟图案；
(e)形成表面保护膜以覆盖所述焊盘、所述第一布线和所述虚拟图案；
(f)在所述表面保护膜中制作达到所述焊盘的开口；以及
(g)在包括所述开口的所述表面保护膜之上形成大于所述焊盘的凸点电极，
其中形成所述凸点电极，使得具有在平面图上与所述焊盘重叠的重叠区和在平面图上不与所述焊盘重叠的非重叠区，
其中所述第一布线和所述虚拟图案形成在所述凸点电极的非重叠区之下，
其中所述虚拟图案是矩形图案，以及
其中所述虚拟图案的两边的每个宽度小于所述第一布线的宽度。
12.根据权利要求11所述的方法，其中所述虚拟图案在离所述凸点电极给定距离内，并且所述顶层包括其中形成所述虚拟图案的虚拟图案区和其中未形成所述虚拟图案的非虚拟图案区。
13.根据权利要求11所述的方法，进一步包括步骤：
(h)在步骤(e)和(f)之间平坦化所述表面保护膜。
14.根据权利要求13所述的方法，其中步骤(h)是通过化学机械抛光平坦化所述表面保护膜的。
15.根据权利要求11所述的方法，步骤(e)包括以下子步骤：
(e1)通过等离子体CVD形成第一氧化硅膜以覆盖所述焊盘、所述第一布线和所述虚拟图案；
(e2)在所述第一氧化硅膜之上形成TEOS的第二氧化硅膜；
(e3)通过化学机械抛光平坦化所述第二氧化硅膜；以及
(e4)在步骤(e3)之后在所述第二氧化硅膜之上形成氮化硅膜。
CN2008101707993A 2007-11-09 2008-10-29 半导体器件及其制造方法 Active CN101431058B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007292079A JP5291917B2 (ja) 2007-11-09 2007-11-09 半導体装置およびその製造方法
JP2007-292079 2007-11-09
JP2007292079 2007-11-09

Publications (2)

Publication Number Publication Date
CN101431058A CN101431058A (zh) 2009-05-13
CN101431058B true CN101431058B (zh) 2012-12-26

Family

ID=40622952

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101707993A Active CN101431058B (zh) 2007-11-09 2008-10-29 半导体器件及其制造方法

Country Status (4)

Country Link
US (12) US8552552B2 (zh)
JP (1) JP5291917B2 (zh)
CN (1) CN101431058B (zh)
TW (2) TWI552239B (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5291917B2 (ja) * 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5415710B2 (ja) * 2008-04-10 2014-02-12 ルネサスエレクトロニクス株式会社 半導体装置
JP5395407B2 (ja) * 2008-11-12 2014-01-22 ルネサスエレクトロニクス株式会社 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法
KR20100055193A (ko) * 2008-11-17 2010-05-26 삼성전자주식회사 반도체 집적 회로 장치 및 그를 포함하는 액정 표시 장치
JP5503208B2 (ja) * 2009-07-24 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP5315186B2 (ja) 2009-09-18 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2013033775A (ja) * 2009-12-03 2013-02-14 Panasonic Corp 半導体集積回路及びそれを備えた半導体装置、並びに電子機器
WO2012002236A1 (en) * 2010-06-29 2012-01-05 Semiconductor Energy Laboratory Co., Ltd. Wiring board, semiconductor device, and manufacturing methods thereof
KR101300034B1 (ko) * 2010-10-18 2013-08-29 엘지디스플레이 주식회사 액정표시장치용 기판 및 이를 이용한 액정표시장치
US8434041B2 (en) * 2011-01-10 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Increasing dielectric strength by optimizing dummy metal distribution
US8778737B2 (en) * 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
TWI467719B (zh) * 2012-05-07 2015-01-01 Novatek Microelectronics Corp 薄膜覆晶裝置
JP5995518B2 (ja) 2012-05-11 2016-09-21 ローム株式会社 半導体装置および半導体装置の製造方法
CN103632957A (zh) * 2012-08-23 2014-03-12 上海华虹宏力半导体制造有限公司 半导体芯片第一层金属阻挡层的制造方法
JP6180801B2 (ja) * 2013-06-07 2017-08-16 ルネサスエレクトロニクス株式会社 半導体装置
JP6334851B2 (ja) * 2013-06-07 2018-05-30 シナプティクス・ジャパン合同会社 半導体装置、表示デバイスモジュール、及び、表示デバイスモジュールの製造方法
JP2015032661A (ja) * 2013-08-01 2015-02-16 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法および半導体装置の実装方法
KR20150038842A (ko) * 2013-10-01 2015-04-09 삼성디스플레이 주식회사 구동 칩, 이를 구비한 표시 장치 및 구동 칩 제조 방법
JP2015079848A (ja) * 2013-10-17 2015-04-23 シナプティクス・ディスプレイ・デバイス株式会社 表示装置駆動用半導体集積回路装置
KR20150080825A (ko) * 2014-01-02 2015-07-10 삼성디스플레이 주식회사 표시 패널, 이를 포함하는 표시 장치 및 이의 제조 방법
US9275967B2 (en) 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
JP2016131245A (ja) * 2015-01-13 2016-07-21 デクセリアルズ株式会社 多層基板
US10943879B2 (en) * 2015-01-13 2021-03-09 Dexerials Corporation Bump-forming film, semiconductor device and manufacturing method thereof, and connection structure
KR102410525B1 (ko) * 2015-04-14 2022-06-20 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이를 구비한 디스플레이 장치, 박막 트랜지스터 기판 제조방법 및 디스플레이 장치 제조방법
JP6503286B2 (ja) * 2015-12-24 2019-04-17 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体ウェハ
JP2017116798A (ja) * 2015-12-25 2017-06-29 株式会社ジャパンディスプレイ 表示装置、表示装置の製造方法、及びドライバｉｃ
CN105514075B (zh) * 2015-12-31 2019-05-17 昆山国显光电有限公司 显示装置绑定结构
KR102487061B1 (ko) 2016-06-30 2023-01-12 삼성디스플레이 주식회사 표시 장치
JP6106794B1 (ja) * 2016-08-05 2017-04-05 サーパス工業株式会社 流体機器
TWI587043B (zh) * 2017-01-25 2017-06-11 友達光電股份有限公司 畫素結構及其顯示面板
CN107807479B (zh) 2017-11-15 2021-01-22 京东方（河北）移动显示技术有限公司 阵列基板和显示面板
US11705624B2 (en) 2017-11-29 2023-07-18 Dai Nippon Printing Co., Ltd. Wiring board and method for manufacturing wiring board
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法
KR102481468B1 (ko) * 2018-01-04 2022-12-26 삼성디스플레이 주식회사 표시 장치
CN110557887B (zh) * 2018-05-31 2021-10-12 京东方科技集团股份有限公司 电路对位组件及显示装置
CN108919571B (zh) * 2018-07-11 2021-07-27 业成科技（成都）有限公司 显示面板
JP6705479B2 (ja) * 2018-09-12 2020-06-03 日亜化学工業株式会社 光源装置の製造方法
US11259406B2 (en) * 2018-11-21 2022-02-22 Synaptics Incorporated Flexible connector for a display device
KR20210018700A (ko) * 2019-08-09 2021-02-18 삼성디스플레이 주식회사 접착 부재 및 이를 포함한 표시장치
KR20210036437A (ko) * 2019-09-25 2021-04-05 삼성디스플레이 주식회사 표시장치 및 이의 제조 방법
CN110579917B (zh) * 2019-10-15 2022-03-01 上海中航光电子有限公司 显示模组及显示装置
CN113496891B (zh) * 2020-04-03 2023-03-14 重庆超硅半导体有限公司 一种集成电路硅片表面氧化膜自适应均匀腐蚀方法
CN114442353A (zh) * 2020-10-30 2022-05-06 京东方科技集团股份有限公司 驱动背板及其制备方法和显示面板
CN112710928B (zh) * 2020-12-10 2023-02-21 国网宁夏电力有限公司电力科学研究院 基于自相关性分析的直流局部放电波形去干扰方法及系统
US20230021655A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1945817A (zh) * 2005-10-07 2007-04-11 株式会社瑞萨科技 半导体器件及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100212009B1 (ko) * 1995-12-29 1999-08-02 김영환 반도체 소자의 금속배선 보호막 형성방법
US6049132A (en) * 1996-07-12 2000-04-11 Kawasaki Steel Corporation Multiple metallization structure for a reflection type liquid crystal display
JP4222525B2 (ja) * 1996-07-12 2009-02-12 川崎マイクロエレクトロニクス株式会社 半導体装置、その製造方法及び反射型液晶表示装置
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP2002198374A (ja) * 2000-10-16 2002-07-12 Sharp Corp 半導体装置およびその製造方法
JP4445189B2 (ja) * 2002-08-29 2010-04-07 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
JP4228948B2 (ja) * 2004-03-16 2009-02-25 日本電気株式会社 表示装置
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7241636B2 (en) * 2005-01-11 2007-07-10 Freescale Semiconductor, Inc. Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
JP4829879B2 (ja) * 2005-03-11 2011-12-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP2007115980A (ja) * 2005-10-21 2007-05-10 Toshiba Corp 半導体装置及びその製造方法
JP2007123407A (ja) * 2005-10-26 2007-05-17 Renesas Technology Corp 半導体装置の製造方法
US7659178B2 (en) * 2006-04-21 2010-02-09 International Business Machines Corporation Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate
JP2007294783A (ja) * 2006-04-27 2007-11-08 Renesas Technology Corp 半導体装置の製造方法および半導体装置の設計支援システム
JP5123510B2 (ja) * 2006-09-28 2013-01-23 ルネサスエレクトロニクス株式会社 半導体装置
JP5291917B2 (ja) * 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1945817A (zh) * 2005-10-07 2007-04-11 株式会社瑞萨科技 半导体器件及其制造方法

Also Published As

Publication number Publication date
US20200335467A1 (en) 2020-10-22
US8552552B2 (en) 2013-10-08
US20160126264A1 (en) 2016-05-05
US20160086911A1 (en) 2016-03-24
US9508630B2 (en) 2016-11-29
US20090121349A1 (en) 2009-05-14
TW201445655A (zh) 2014-12-01
US20130344693A1 (en) 2013-12-26
TWI552239B (zh) 2016-10-01
CN101431058A (zh) 2009-05-13
TW200924091A (en) 2009-06-01
US20170005055A1 (en) 2017-01-05
US20160126203A1 (en) 2016-05-05
US20190172808A1 (en) 2019-06-06
US20170338197A1 (en) 2017-11-23
US9484286B2 (en) 2016-11-01
US10204878B2 (en) 2019-02-12
US20140312493A1 (en) 2014-10-23
US20130020701A1 (en) 2013-01-24
US8785318B2 (en) 2014-07-22
US10741517B2 (en) 2020-08-11
US20160079202A1 (en) 2016-03-17
TWI453842B (zh) 2014-09-21
JP2009117761A (ja) 2009-05-28
JP5291917B2 (ja) 2013-09-18
US9484287B2 (en) 2016-11-01
US8552555B2 (en) 2013-10-08
US9748191B2 (en) 2017-08-29
US11239191B2 (en) 2022-02-01

Similar Documents

Publication Publication Date Title
CN101431058B (zh) 半导体器件及其制造方法
JP5259211B2 (ja) 半導体装置
JP2007123407A (ja) 半導体装置の製造方法
JP5805818B2 (ja) 半導体装置
JP5759029B2 (ja) 半導体装置
JP5466280B2 (ja) 半導体装置
JP6030200B2 (ja) 半導体装置
JP2016154252A (ja) 半導体装置およびその製造方法
JP5918421B2 (ja) 半導体装置
JP5918422B2 (ja) 半導体装置
US20240339475A1 (en) Signal shielding for integrated circuits
JP5514927B2 (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP.

Effective date: 20100925

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20100925

Address after: Kanagawa

Applicant after: Renesas Electronics Corporation

Address before: Tokyo, Japan, Japan

Applicant before: Renesas Technology Corp.

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP02 Change in the address of a patent holder
CP02 Change in the address of a patent holder

Address after: Tokyo, Japan, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa

Patentee before: Renesas Electronics Corporation