CN101416315A - 用于功率器件的电荷平衡技术 - Google Patents
用于功率器件的电荷平衡技术 Download PDFInfo
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Abstract
一种电荷平衡半导体功率器件,包括:活性区域,包括被偏置于导电状态中时能够传导电流的多个单元;环绕活性区域的非活性周界区,其中,当多个单元被偏置于导电状态中时没有电流流过非活性周界区;交替布置的p柱的条带和n柱的条带,沿着容纳半导体功率器件的模片的长度延伸穿过活性区域和非活性周界区。
Description
相关申请交叉参考
本申请涉及2004年12月29日提交的第11/026,276号普通转让美国申请,其全部内容结合于此作为参考。
技术领域
本发明涉及半导体功率器件技术,更具体地涉及用于半导体功率器件的电荷平衡技术。
背景技术
垂直半导体功率器件具有电极布置在两个相对平面上的结构。当接通垂直功率器件时,漂移电流在该器件中垂直地流动。当断开垂直功率器件时,由于施加在该器件上的反向偏压,在器件中形成沿水平方向和垂直方向延伸的耗尽区。为了获得高击穿电压,设置在电极之间的漂移层由具有高电阻率的材料形成,并且增大漂移层的厚度。然而,这会导致器件中的接通电阻Rdson增大,这随之降低了导电率和器件的转换速度,因而降低器件的性能。
为了解决这个问题,已经提出了具有这样的漂移层的电荷平衡功率器件,该漂移层包括以交替方式布置的垂直延伸的n区(n柱)和p区(p柱)。图1A是这种器件100的布局图。器件100包括被非活性周界区环绕的活性区域110,该非活性周界区包括p环120和外端接区130。周界p环120为具有圆角的矩形。依据设计,端接区130可以包括类似形状的交替的p环和n环。活性区域110包括交替布置的p柱110P和n柱110N,这些p柱和n柱以条带的形式垂直地延伸并且沿着顶部和底部在周界环120处端接。图1B中可以更清楚地看到活性区域中交替的p柱和n柱的物理结构,图1B示出了沿图1A中的线A-A′的阵列区110的横截面视图。
图1B中描绘的功率器件是具有漂移层16的传统平面门电路垂直MOSFET,该漂移层包括交替的p柱110P和n柱110N。源极金属28电接触沿着顶侧的源极区20和阱区18,而漏极金属14电接触沿着器件的底侧的漏极区12。当接通器件时,电流路径就通过交替导电型漂移层16形成。n柱和p柱掺杂浓度和物理尺寸被设计成在相邻的柱之间获得电荷平衡,从而保证当器件处于断开状态时漂移层16完全耗尽。
回到图1A,为了实现高击穿电压,n柱中n电荷的数量和p柱中p电荷的数量在活性区域110中以及在活性区域与非活性周界区之间的界面处都必须是平衡的。然而,因为各种区的几何形状的变化,在所有的界面区处实现电荷平衡,尤其是沿着p柱和n柱端接于周界环120中的顶部界面区和底部界面区实现电荷平衡,以及在n柱和p柱具有变化的长度的转角区中实现电荷平衡是困难的。这在图1C中更清楚地示出,图1C示出了图1A中的功率器件100的左上角的放大视图。
在图1C中,活性区域110中的单元被标记为S1。活性p柱111(其被划分成左半部111-1和右半部111-2)和活性p柱113(其被划分成左半部113-1和右半部113-2)通过n柱112分隔开。在单元S1中,活性p柱111的右半部111-2中的p电荷数量Qp1和活性p柱113的左半部113-2中的p电荷数量Qp2的总和(Qp1+Qp2)等于活性n柱112中的n电荷数量Qn1。因此,在活性区域110的维持了这种电荷平衡的所有部分中实现了最佳击穿电压。
如所示的,非活性周界区的转角部分包括周界p环120和端接区130,该端接区具有以交替方式布置的n环131和p环132。周界p环120(其被划分成下半部121和上半部122)和端接区p环132(其被划分成下半部132-1和上半部132-2)通过n环131分隔开。在单元S2中,p环132的下半部132-1中的p电荷数量Qpt1和环120的上半部122中的p电荷数量Qpe的总和(Qpt1+Qpe)等于n环131中的n电荷数量Qnt。因此,在非活性周界区的维持了这种电荷平衡的所有部分中实现了最佳击穿电压。
然而,因为几何形状的限制,活性区域与非活性周界区之间的界面处的p电荷数量和n电荷数量在很多位置是不平衡的。这些区中缺少电荷平衡导致器件的击穿电压特性恶化。因此,需要消除了现有技术中活性区域到非活性周界区界面处的电荷不平衡问题的电荷平衡技术,因而导致更高的击穿电压额定值(rating)。
发明内容
根据本发明的实施例,电荷平衡半导体功率器件包括这样的活性区域:该活性区域包括当被偏置于导电状态中时能够传导电流的多个单元。非活性周界区环绕活性区域。当多个单元被偏置于导电状态中时,没有电流流过非活性周界区。交替布置的第一导电型柱的条带和第二导电型柱的条带沿着容纳半导体功率器件的模片(die)的长度延伸穿过活性区域和非活性周界区。
在一个实施例中,每个第一导电型柱的条带均包括形成第二导电型区的条带的一部分的间断(discontinuity)。第二导电型区的条带垂直于模片的长度在非活性周界区中延伸。
在另一个实施例中,每个第一导电型柱的条带包括形成多个第二导电型区的条带的一部分的多个间断。该多个第二导电型区的条带垂直于模片的长度在非活性周界区中延伸。
根据本发明的另一实施例,电荷平衡半导体功率器件包括这样的活性区:该活性区包括被偏置于导电状态中时能够传导电流的多个单元。非活性周界区环绕活性区域。当多个单元被偏压于导电状态中时,没有电流通过非活性周界区。P柱的条带和n柱的条带以交替方式布置。P柱的条带和n柱的条带沿着容纳半导体功率器件的模片的长度延伸穿过活性区域和非活性周界区。每个p柱的条带均包括形成多个n区的条带的一部分的多个间断。该多个n区的条带垂直于模片的长度在非活性周界区中延伸。
可以参照本说明书的剩余部分以及附图实现对在此所公开的本发明的特征和优点的进一步理解。
附图说明
图1A示出了传统电荷平衡功率器件的简化布局图;
图1B示出了沿图1C中的功率器件中的线A-A′的横截面视图;
图1C示出了图1A中的功率器件的左上角的放大视图;
图2示出了根据本发明示例性实施例的电荷平衡功率器件的简化布局图;
图3示出了根据本发明另一示例性实施例的电荷平衡功率器件的简化布局图;
图4示出了根据本发明又一示例性实施例的电荷平衡功率器件的简化布局图;以及
图5和图6示出了非活性周界区的简化横截面视图,其中场板(field plate)与根据本发明的两个示例性实施例的电荷平衡结构结合。
具体实施方式
图2-图4示出了模片的简化布局图,其中根据本发明的三个示例性实施例实现了改进的电荷平衡技术。这些技术有利地消除了为了在现有技术的电荷平衡器件中的活性区域与其环绕的非活性周界区之间的过渡区处实现电荷平衡的复杂设计需求。
在图2中,容纳电荷平衡功率器件的模片200包括其中形成有多个活性单元的活性区域202和环绕活性区域的非活性周界区。非活性周界区由从活性区域202的水平边缘到模片的对应边缘的距离(在图2中以字母X标记出)限定,并且由从活性区域202的垂直边缘到模片的对应边缘的距离(在图2中以字母Y标记出)限定。通常,术语“活性区域”在此用来指明器件的其中形成有能够传导电流的活性单元的区域,而术语“非活性周界区”用来指明器件的其中形成有非导电结构的区域。
为了更清楚地示出这些图中的电荷平衡技术,图2-图4中的距离X和Y被显著地放大(实际上,距离X和Y远小于图2-4中所示的距离)。容纳在模片200中的功率器件是MOSFET(例如,与图1B中的类似),在图2中由参考标号202标记的活性区域的边界与其中形成有MOSFET单元的阱区的边界对应。
如图2中所示,垂直延伸的p柱210P和n柱210N以交替的方式布置,从而形成电荷平衡结构。在一个实施例中,活性p柱210P通过在硅中形成沟槽(trench)并使用诸如选择性外延生长(SEG)的已知技术用p型硅填充这些沟槽来形成。通常,使这些n柱和p柱的物理尺寸和掺杂浓度最优化,从而在相邻的柱之间获得电荷平衡,这与以上结合图1C中的单元S1的描述类似。
与其中活性区域中的p柱和n柱在活性区域的边界处端接的传统电荷平衡器件不同,在图2中,如所示的那样,活性p柱和n柱延伸穿过活性区域和非活性周界区。这消除了活性区域的边缘和转角处的电荷平衡问题,因此在显著地简化了器件的设计的同时实现了最佳的电荷平衡和击穿特性。
在一个实施例中,距离X和Y被选择成确保活性区域外的完全耗尽。在一个实施例中,其中p柱通过在硅中形成沟槽来形成,距离X和Y中的每一个均等于或大于p柱沟槽的深度。尽管图2中所示的活性区域202的垂直边缘落入n柱中,然而可以扩展或收缩活性区域,以使得活性区域的垂直边缘落入p柱中。像这样,对于活性区域202的边缘与柱就不存在误对准问题。在一个实施例中,起始晶片可以包括如图2中所示的p柱和n柱,而包括其活性区域和其他区的功率器件利用已知的加工技术形成。
图3示出了与图2中的实施例类似的另一个实施例,除了在上非活性周界区和下非活性周界区中每一个的垂直延伸的p柱中形成有间断之外。这些间断形成水平延伸的n条带320N,如下非活性周界区中所示的那样,该n条带将每个p柱分割成两个部分310P-1和310P-2。p柱中的这些间断扰乱了非活性周界区中的场,从而减小了沿着该区中的硅表面的场。这有助于提高非活性周界区中的击穿电压。
在一个实施例中,从活性区域302的边缘到n条带320N的间隔B基于功率器件的击穿电压额定值、光掩膜限制、以及其他性能和设计目标来确定。在一个实施例中,使用较小的间隔B来实现更精细的场分布调节。非活性周界区中的尺寸(X、Y、B)又都被放大了,以更容易地示出本发明的各种特征。
图4示出了图3实施例的变体,其中在上非活性周界区和下非活性周界区中每一个的每个p柱中均形成有多个间断,因此在这些区中形成多个n条带420N、430N。多个间断使得能够实现更高的电压额定值。如所示的,外部条带430N比内部条带420N宽。对选择N条带的宽度以及它们之间的间隔的考虑与针对传统端接防护环的考虑相似。在一个实施例中,图3和4中的n条带以如下方式形成。在形成p柱的过程中,使用掩膜来防止p柱在沿着p柱的间隙位置处形成。
如果需要,图2-图4中的技术可以与其他的边缘端接技术结合。具体地,端接场板技术可以有利地与图2-图4中的实施例结合,以进一步减少非活性周界区中的硅表面处的场。图5和6中示出了这种结合的两个实例。
图5示出了沿着活性区域的边缘处的模片区的横截面视图。在图5中,活性区域延伸至p阱502的左侧,而非活性周界区延伸至p阱502的右侧。如图2-图4中实施例,p柱510P和n柱510N延伸穿过活性区域和非活性周界区两者。如所示的,p柱510P在N外延层512中的一深度处端接,而N外延层512的在p柱510P之间延伸的那些部分形成电荷平衡结构的n柱510N。浮动p型扩散环504A-504C形成在非活性周界区中并在活性区周围延伸。如所看到的那样,相邻环之间的间隔沿远离活性区的方向逐渐增加。介电层506使环504A-504C与叠加结构(未示出)绝缘。P阱502可以是活性区域的最后的p阱或者形成端接结构的一部分。在任一种情况中,p阱502会电连接至活性p阱。
与图5类似,图6示出了活性区域的边缘处的模片区的横截面视图,其中活性区域延伸至p阱602的左侧,而端接区延伸至p阱602的右侧。P柱610P和n柱610N延伸穿过活性区域和非活性区两者。如图5中的实施例,p柱610P在N外延层612中的一深度处端接,而N外延层612的在p柱610P之间延伸的那些部分形成电荷平衡结构的n柱610N。然而,在这个实施例中,在非活性周界区上方形成有平面场板结构。该平面场板结构包括在非活性周界区上方延伸的多晶硅层608,以及将多晶硅层608电连接至p阱602的金属接触层614。介电层606使非活性周界区中的电荷平衡结构与层叠的多晶硅层608和其他未示出的结构绝缘。如图5中所示的实施例,p阱602可以是活性区域的最后的p阱或者形成端接结构的一部分。在任一种情况中,p阱602会电连接至活性p阱。
尽管图5和6示出了两种不同的边缘端接技术,然而这两种技术可以以多种方式结合。例如,在图6实施例的可替换实施方式中,多个浮动p型扩散环以类似于图5中的方式包含在非活性周界区中,除了p型扩散环被设置在场板608的左侧。作为另一实例,在图5实例的可替换实施方式中,一单独的平面场板连接至每个浮动p型扩散环504A-504C。
在此公开的各种电荷平衡技术可以与图1B中所示的垂直平面门电路MOSFET单元结构、及其他的电荷平衡MOSFET变体(诸如沟槽门电路或屏蔽门电路结构)、以及其他电荷平衡功率器件(诸如IGBT、双极晶体管、二极管和肖特基器件)相结合。例如,本发明的各种实施例可以与例如上面所参照的2004年12月29日提交的第11/026,276,号美国专利申请的图14、图21-图24、图28A-图28D、图29A-图29C、图61A、图62A、图62B、图63A中示出的任何器件相结合,其全部内容结合于此作为参考。
尽管上面提供了对本发明的各种实施例的详细描述,然而,可以有多种替换、修改、和等同物。并且,应理解,在此提供以描述各种实施例的所有数字实例和材料类型仅是为了示例说明的目的,而不是旨在限制本发明。例如,上述实施例中的各种区的极性可以颠倒以获得相反类型的器件。因此,由于这个以及其他原因,以上描述不应被理解成限制本发明的范围,本发明的范围由权利要求来限定。
Claims (25)
1.一种电荷平衡半导体功率器件,包括:
活性区域,包括被偏置于导电状态中时能够传导电流的多个单元;
环绕所述活性区域的非活性周界区,其中,当所述多个单元被偏置于所述导电状态中时没有电流流过所述非活性周界区;以及
形成在第二导电型的硅区中的交替布置的第一导电型柱的条带和第二导电型柱的条带,所述交替布置的第一导电型的条带和第二导电型的条带沿第一尺寸延伸穿过所述活性区域和所述非活性周界区。
2.根据权利要求1所述的电荷平衡半导体功率器件,其中,每个第一导电型柱的条带均包括形成第二导电型区的条带的一部分的间断,所述第二导电型区的条带垂直于所述第一尺寸在所述非活性周界区中延伸。
3.根据权利要求1所述的电荷平衡半导体功率器件,其中,每个第一导电型柱的条带均包括形成多个第二导电型区的条带的一部分的多个间断,所述多个第二导电型区的条带垂直于所述第一尺寸在所述非活性周界区中延伸。
4.根据权利要求1所述的电荷平衡半导体功率器件,其中,所述电荷平衡半导体功率器件是垂直导电的功率器件。
5.根据权利要求1所述的电荷平衡半导体功率器件,其中,所述第一导电型是p型,而所述第二导电型是n型。
6.根据权利要求1所述的电荷平衡半导体功率器件,还包括处于所述非活性端接区中的场板。
7.根据权利要求1所述的电荷平衡半导体功率器件,其中,所述非活性周界区包括在所述活性区域周围延伸的多个第二导电型的环。
8.根据权利要求1所述的电荷平衡半导体功率器件,还包括延伸到所述非活性周界区中的场板导体,其中,所述场板导体的一部分通过介电层与下面的第一导电型柱的条带和第二导电型柱的条带绝缘。
9.一种垂直导电的电荷平衡半导体功率器件,包括:
活性区域,包括被偏置于导电状态中时能够传导电流的多个单元;
环绕所述活性区域的非活性周界区,其中,当所述多个单元被偏置于所述导电状态中时没有电流流过所述非活性周界区;以及
沿第一尺寸延伸穿过所述活性区域和所述非活性周界区的交替布置的第一导电型柱的条带和第二导电型柱的条带,每个第一导电型柱的条带均包括形成第二导电型区的条带的一部分的间断,所述第二导电型区的条带垂直于所述第一尺寸在所述非活性周界区中延伸。
10.根据权利要求9所述的电荷平衡半导体功率器件,其中,所述第一导电型是p型,而所述第二导电型是n型。
11.根据权利要求9所述的电荷平衡半导体功率器件,还包括处于所述非活性端接区中的场板。
12.根据权利要求9所述的电荷平衡半导体功率器件,其中,所述非活性周界区包括在所述活性区域周围延伸的多个第二导电型的环。
13.根据权利要求9所述的电荷平衡半导体功率器件,还包括延伸到所述非活性周界区中的场板导体,其中,所述场板导体的一部分通过介电层与下面的第一导电型柱的条带和第二导电型柱的条带绝缘。
14.一种电荷平衡半导体功率器件,包括:
活性区域,包括被偏置于导电状态中时能够传导电流的多个单元;
环绕所述活性区域的非活性周界区,其中,当所述多个单元被偏置于所述导电状态中时没有电流流过所述非活性周界区;以及
以交替方式布置的p柱的条带和n柱的条带,所述p柱的条带和n柱的条带沿着容纳所述半导体功率器件的模片的长度延伸穿过所述活性区域和所述非活性周界区,每个p柱的条带均包括形成多个n区的条带的一部分的多个间断,所述多个n区的条带垂直于所述模片的长度在所述非活性周界区中延伸。
15.根据权利要求14所述的电荷平衡半导体功率器件,其中,所述电荷平衡半导体功率器件是垂直导电的功率器件。
16.根据权利要求14所述的电荷平衡半导体功率器件,还包括处于所述非活性端接区中的场板。
17.根据权利要求14所述的电荷平衡半导体功率器件,其中,所述非活性周界区包括在所述活性区域周围延伸的多个第二导电型的环。
18.根据权利要求14所述的电荷平衡半导体功率器件,还包括延伸到所述非活性周界区中的场板导体,其中,所述场板导体的一部分通过介电层与下面的第一导电型柱的条带和第二导电型柱的条带绝缘。
19.一种硅晶片,包括:
第一导电型的硅区;以及
在所述硅区中从沿着硅晶片周界的位置到沿着硅晶片周界的相对位置而平行延伸的多个第二导电型柱的条带,所述多个第二导电型柱的条带延伸至所述硅区中的预定深度。
20.根据权利要求19所述的硅晶片,其中,所述第一导电型是n型,而所述第二导电型是p型。
21.一种硅模片,包括:
第一导电型的硅区;以及
在所述硅区中从所述硅模片的一个边缘到所述硅模片的相对边缘而平行延伸的多个第二导电型柱的条带,所述多个第二导电柱的条带延伸至所述硅区中的预定深度。
22.根据权利要求21所述的硅模片,其中,所述第一导电型是n型,而所述第二导电型是P型。
23.一种在具有第一导电型的硅区的半导体模片中形成电荷平衡结构的方法,所述方法包括:
形成在所述硅区中从所述硅模片的一个边缘到所述硅模片的相对边缘而平行延伸的多个第二导电型柱的条带,所述多个第二导电型柱的条带延伸至所述硅区中的预定深度。
24.根据权利要求23所述的方法,其中,所述形成步骤包括:
形成延伸至所述硅区中的预定深度的多个沟槽,所述沟槽从所述硅模片的一个边缘延伸至所述硅模片的相对边缘;以及
用第二导电型的硅材料填充所述多个沟槽。
25.根据权利要求23所述的方法,其中,所述第一导电型是n型,而所述第二导电型是p型。
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JP3899231B2 (ja) * | 2000-12-18 | 2007-03-28 | 株式会社豊田中央研究所 | 半導体装置 |
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
DE10205345B9 (de) * | 2001-02-09 | 2007-12-20 | Fuji Electric Co., Ltd., Kawasaki | Halbleiterbauelement |
JP4839519B2 (ja) * | 2001-03-15 | 2011-12-21 | 富士電機株式会社 | 半導体装置 |
US6683363B2 (en) * | 2001-07-03 | 2004-01-27 | Fairchild Semiconductor Corporation | Trench structure for semiconductor devices |
JP3973395B2 (ja) * | 2001-10-16 | 2007-09-12 | 株式会社豊田中央研究所 | 半導体装置とその製造方法 |
JP4126915B2 (ja) * | 2002-01-30 | 2008-07-30 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP3908572B2 (ja) * | 2002-03-18 | 2007-04-25 | 株式会社東芝 | 半導体素子 |
US6768180B2 (en) * | 2002-04-04 | 2004-07-27 | C. Andre T. Salama | Superjunction LDMOST using an insulator substrate for power integrated circuits |
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JP4253558B2 (ja) * | 2003-10-10 | 2009-04-15 | 株式会社豊田中央研究所 | 半導体装置 |
US8084815B2 (en) * | 2005-06-29 | 2011-12-27 | Fairchild Korea Semiconductor Ltd. | Superjunction semiconductor device |
KR20070015309A (ko) * | 2005-07-30 | 2007-02-02 | 페어차일드코리아반도체 주식회사 | 고전압 반도체소자 |
US7595542B2 (en) * | 2006-03-13 | 2009-09-29 | Fairchild Semiconductor Corporation | Periphery design for charge balance power devices |
US7592668B2 (en) * | 2006-03-30 | 2009-09-22 | Fairchild Semiconductor Corporation | Charge balance techniques for power devices |
-
2006
- 2006-03-30 US US11/396,239 patent/US7592668B2/en active Active
-
2007
- 2007-03-22 AT AT0913907A patent/AT505584A2/de unknown
- 2007-03-22 DE DE112007000803T patent/DE112007000803T5/de not_active Ceased
- 2007-03-22 JP JP2009503170A patent/JP2009532879A/ja active Pending
- 2007-03-22 KR KR1020087025017A patent/KR101437698B1/ko active IP Right Grant
- 2007-03-22 WO PCT/US2007/064696 patent/WO2007117938A2/en active Application Filing
- 2007-03-22 CN CN2007800124267A patent/CN101416315B/zh active Active
- 2007-03-29 TW TW096111038A patent/TWI455307B/zh not_active IP Right Cessation
-
2009
- 2009-09-17 US US12/562,025 patent/US7936013B2/en active Active
-
2011
- 2011-04-08 US US13/083,337 patent/US20110241172A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106158800A (zh) * | 2010-12-28 | 2016-11-23 | 瑞萨电子株式会社 | 半导体器件 |
CN106158800B (zh) * | 2010-12-28 | 2019-07-30 | 瑞萨电子株式会社 | 半导体器件 |
TWI567974B (zh) * | 2014-07-28 | 2017-01-21 | 萬國半導體股份有限公司 | 用於納米管mosfet的端接設計 |
Also Published As
Publication number | Publication date |
---|---|
KR20090007327A (ko) | 2009-01-16 |
KR101437698B1 (ko) | 2014-09-03 |
TW200802867A (en) | 2008-01-01 |
US20100006927A1 (en) | 2010-01-14 |
DE112007000803T5 (de) | 2009-01-29 |
US7592668B2 (en) | 2009-09-22 |
US20070228490A1 (en) | 2007-10-04 |
JP2009532879A (ja) | 2009-09-10 |
CN101416315B (zh) | 2011-04-27 |
TWI455307B (zh) | 2014-10-01 |
WO2007117938A3 (en) | 2008-05-08 |
US7936013B2 (en) | 2011-05-03 |
AT505584A2 (de) | 2009-02-15 |
US20110241172A1 (en) | 2011-10-06 |
WO2007117938A2 (en) | 2007-10-18 |
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