CN101315515B - 利用具有插入区域的间隔物掩模的频率三倍化 - Google Patents

利用具有插入区域的间隔物掩模的频率三倍化 Download PDF

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Publication number
CN101315515B
CN101315515B CN2008100983623A CN200810098362A CN101315515B CN 101315515 B CN101315515 B CN 101315515B CN 2008100983623 A CN2008100983623 A CN 2008100983623A CN 200810098362 A CN200810098362 A CN 200810098362A CN 101315515 B CN101315515 B CN 101315515B
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China
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mask
spacer
layer
lines
sacrificial
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Expired - Fee Related
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CN2008100983623A
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English (en)
Chinese (zh)
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CN101315515A (zh
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克里斯多佛·D·本彻尔
堀冈启治
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN2008100983623A 2007-06-01 2008-05-30 利用具有插入区域的间隔物掩模的频率三倍化 Expired - Fee Related CN101315515B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US93261807P 2007-06-01 2007-06-01
US60/932,618 2007-06-01
US11/875,205 2007-10-19
US11/875,205 US7846849B2 (en) 2007-06-01 2007-10-19 Frequency tripling using spacer mask having interposed regions

Publications (2)

Publication Number Publication Date
CN101315515A CN101315515A (zh) 2008-12-03
CN101315515B true CN101315515B (zh) 2013-03-27

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CN2008100983623A Expired - Fee Related CN101315515B (zh) 2007-06-01 2008-05-30 利用具有插入区域的间隔物掩模的频率三倍化

Country Status (7)

Country Link
US (1) US7846849B2 (enExample)
EP (1) EP1998362A2 (enExample)
JP (1) JP5236996B2 (enExample)
KR (1) KR100991339B1 (enExample)
CN (1) CN101315515B (enExample)
SG (1) SG148135A1 (enExample)
TW (1) TWI381424B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7807578B2 (en) * 2007-06-01 2010-10-05 Applied Materials, Inc. Frequency doubling using spacer mask
JP5484325B2 (ja) * 2008-06-13 2014-05-07 東京エレクトロン株式会社 半導体装置の製造方法
US9953885B2 (en) * 2009-10-27 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. STI shape near fin bottom of Si fin in bulk FinFET
US7923305B1 (en) * 2010-01-12 2011-04-12 Sandisk 3D Llc Patterning method for high density pillar structures
US8865600B2 (en) * 2013-01-04 2014-10-21 Taiwan Semiconductor Manufacturing Company Limited Patterned line end space
US8828885B2 (en) 2013-01-04 2014-09-09 Taiwan Semiconductor Manufacturing Company Limited Photo resist trimmed line end space
CN104425223B (zh) * 2013-08-28 2017-11-03 中芯国际集成电路制造(上海)有限公司 图形化方法
US9070630B2 (en) * 2013-11-26 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming patterns
US9524878B2 (en) * 2014-10-02 2016-12-20 Macronix International Co., Ltd. Line layout and method of spacer self-aligned quadruple patterning for the same
CN105590894B (zh) * 2014-11-12 2018-12-25 旺宏电子股份有限公司 线路布局以及线路布局的间隙壁自对准四重图案化的方法
CN107785247A (zh) * 2016-08-24 2018-03-09 中芯国际集成电路制造(上海)有限公司 金属栅极及半导体器件的制造方法
US10566194B2 (en) 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning
US10811256B2 (en) * 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
SG11202110987UA (en) * 2019-04-08 2021-10-28 Applied Materials Inc Methods for modifying photoresist profiles and tuning critical dimensions
CN112309838B (zh) * 2019-07-31 2023-07-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US12068168B2 (en) * 2022-02-17 2024-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Processes for reducing line-end spacing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1832109A (zh) * 2005-03-08 2006-09-13 联华电子股份有限公司 掩模的制造方法与图案化制造方法
CN1860586A (zh) * 2003-09-30 2006-11-08 英飞凌科技股份公司 用于制造硬掩模的方法和硬掩模结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR100354440B1 (ko) * 2000-12-04 2002-09-28 삼성전자 주식회사 반도체 장치의 패턴 형성 방법
JP4235404B2 (ja) * 2002-06-12 2009-03-11 キヤノン株式会社 マスクの製造方法
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
JP2004207385A (ja) * 2002-12-24 2004-07-22 Rohm Co Ltd マスク、その製造方法およびこれを用いた半導体装置の製造方法
JP2005203672A (ja) * 2004-01-19 2005-07-28 Sony Corp 半導体装置の製造方法
US7064078B2 (en) * 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
KR100674970B1 (ko) * 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
US7560390B2 (en) * 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
KR100752674B1 (ko) * 2006-10-17 2007-08-29 삼성전자주식회사 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1860586A (zh) * 2003-09-30 2006-11-08 英飞凌科技股份公司 用于制造硬掩模的方法和硬掩模结构
CN1832109A (zh) * 2005-03-08 2006-09-13 联华电子股份有限公司 掩模的制造方法与图案化制造方法

Also Published As

Publication number Publication date
US20080299465A1 (en) 2008-12-04
SG148135A1 (en) 2008-12-31
TW200910419A (en) 2009-03-01
JP2009027146A (ja) 2009-02-05
KR20080106070A (ko) 2008-12-04
EP1998362A2 (en) 2008-12-03
TWI381424B (zh) 2013-01-01
KR100991339B1 (ko) 2010-11-01
JP5236996B2 (ja) 2013-07-17
CN101315515A (zh) 2008-12-03
US7846849B2 (en) 2010-12-07

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