SG11202110987UA - Methods for modifying photoresist profiles and tuning critical dimensions - Google Patents

Methods for modifying photoresist profiles and tuning critical dimensions

Info

Publication number
SG11202110987UA
SG11202110987UA SG11202110987UA SG11202110987UA SG11202110987UA SG 11202110987U A SG11202110987U A SG 11202110987UA SG 11202110987U A SG11202110987U A SG 11202110987UA SG 11202110987U A SG11202110987U A SG 11202110987UA SG 11202110987U A SG11202110987U A SG 11202110987UA
Authority
SG
Singapore
Prior art keywords
methods
critical dimensions
photoresist profiles
modifying
tuning
Prior art date
Application number
SG11202110987UA
Inventor
Meenakshi GUPTA
Rui Cheng
Srinivas Guggilla
Karthik Janakiraman
Diwakar N Kedlaya
Zubin Huang
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of SG11202110987UA publication Critical patent/SG11202110987UA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
SG11202110987UA 2019-04-08 2020-02-21 Methods for modifying photoresist profiles and tuning critical dimensions SG11202110987UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962830759P 2019-04-08 2019-04-08
PCT/US2020/019151 WO2020209939A1 (en) 2019-04-08 2020-02-21 Methods for modifying photoresist profiles and tuning critical dimensions

Publications (1)

Publication Number Publication Date
SG11202110987UA true SG11202110987UA (en) 2021-10-28

Family

ID=72663259

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202110987UA SG11202110987UA (en) 2019-04-08 2020-02-21 Methods for modifying photoresist profiles and tuning critical dimensions

Country Status (7)

Country Link
US (1) US11456173B2 (en)
JP (1) JP2022528697A (en)
KR (1) KR20210138119A (en)
CN (1) CN113795908A (en)
SG (1) SG11202110987UA (en)
TW (1) TW202041700A (en)
WO (1) WO2020209939A1 (en)

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KR100630677B1 (en) * 2003-07-02 2006-10-02 삼성전자주식회사 Etching process having plasma pre-treatment for inducing carbon contained fluorine free - polymer on photoresist patterns
US20050109276A1 (en) 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber
KR100674967B1 (en) 2005-04-06 2007-01-26 삼성전자주식회사 Method of forming photoresist patterns having fine pitch using double patterning technique
US7807578B2 (en) * 2007-06-01 2010-10-05 Applied Materials, Inc. Frequency doubling using spacer mask
US8277670B2 (en) * 2008-05-13 2012-10-02 Lam Research Corporation Plasma process with photoresist mask pretreatment
US9330934B2 (en) * 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US8912097B2 (en) * 2009-08-20 2014-12-16 Varian Semiconductor Equipment Associates, Inc. Method and system for patterning a substrate
TW201308021A (en) * 2011-06-15 2013-02-16 Applied Materials Inc Methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control
TWI492298B (en) * 2011-08-26 2015-07-11 Applied Materials Inc Double patterning etching process
FR3000601B1 (en) 2012-12-28 2016-12-09 Commissariat Energie Atomique METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
WO2015086049A1 (en) 2013-12-10 2015-06-18 Applied Materials, Inc. Evaporation source for organic material, apparatus having an evaporation source for organic material, system having an evaporation deposition apparatus with an evaporation source for organic materials, and method for operating an evaporation source for organic material
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US20180261686A1 (en) 2017-03-13 2018-09-13 Applied Materials, Inc. Transistor sidewall formation process
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Also Published As

Publication number Publication date
US11456173B2 (en) 2022-09-27
WO2020209939A1 (en) 2020-10-15
KR20210138119A (en) 2021-11-18
US20200321210A1 (en) 2020-10-08
TW202041700A (en) 2020-11-16
CN113795908A (en) 2021-12-14
JP2022528697A (en) 2022-06-15

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