CN104934366A - 具有气隙的结构的形成方法 - Google Patents
具有气隙的结构的形成方法 Download PDFInfo
- Publication number
- CN104934366A CN104934366A CN201410129066.0A CN201410129066A CN104934366A CN 104934366 A CN104934366 A CN 104934366A CN 201410129066 A CN201410129066 A CN 201410129066A CN 104934366 A CN104934366 A CN 104934366A
- Authority
- CN
- China
- Prior art keywords
- air gap
- layer
- hard mask
- formation method
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 117
- 230000015572 biosynthetic process Effects 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 42
- 238000004519 manufacturing process Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000003575 carbonaceous material Substances 0.000 claims description 4
- 229910010272 inorganic material Inorganic materials 0.000 claims description 4
- 239000011147 inorganic material Substances 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000007667 floating Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002052 molecular layer Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 BARC) Substances 0.000 description 1
- 239000002194 amorphous carbon material Substances 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Optics & Photonics (AREA)
- Chemical Vapour Deposition (AREA)
- Micromachines (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开一种具有气隙的结构的形成方法,包括下列步骤。在基底的图案区中形成多个图案。在基底上形成牺牲层,且牺牲层的上表面低于图案的上表面,而暴露出图案的多个上部。形成覆盖牺牲层及图案的上部的硬掩模层。对硬掩模层进行回蚀刻制作工艺,以暴露出图案区以外的牺牲层,且留在图案区中的硬掩模层封住图案的上部之间的开口。移除牺牲层,而在相邻两个图案之间形成气隙。
Description
技术领域
本发明涉及一种半导体元件的制造方法,且特别是涉及一种具有气隙的结构的形成方法。
背景技术
在半导体元件中,目前发展出一种具有气隙的结构,以防止各组成构件之间的电性干扰。
以下,以非挥发性存储器元件为例进行说明。典型的非挥发性存储器元件一般是被设计成具有堆叠栅极(stacked-gate)结构,其中包括以掺杂多晶硅制作的浮置栅极(floating Gate)与控制栅极(control gate)。浮置栅极位于控制栅极和基底之间,且处于浮置状态,而控制栅极则与字符线(word Line)相接。此外,非挥发性存储器元件还包括隧道介电层(tunneling dielectric layer)和栅间介电层(inter-gate dielectric layer)分别位于基底和浮置栅极之间以及浮置栅极和控制栅极之间。
在目前提高元件集成度的趋势下,会依据设计规则缩小元件的尺寸。在此情况下,为了防止堆叠栅极结构之间的电容-电阻延迟(resistor-capacitordelay,RC delay)增加以及防止浮置栅极间的耦合干扰升高,进而提高栅极耦合率,会通过在堆叠栅极结构之间形成气隙来解决上述问题。
然而,随着元件集成度增加,现有的非挥发存储器制造方法所制造的非挥发性存储器的气隙比较低,因而导致无法有效地降低电容-电阻延迟以及无法有效地解决浮置栅极间的耦合干扰的问题。
发明内容
本发明的目的在于提供一种具有气隙的结构的形成方法,其可有效地提高气隙比。
为达上述目的,本发明提出一种具有气隙的结构的形成方法,包括下列步骤。在基底的图案区中形成多个图案。在基底上形成牺牲层,且牺牲层的上表面低于图案的上表面,而暴露出图案的多个上部。形成覆盖牺牲层及图案的上部的硬掩模层。对硬掩模层进行回蚀刻制作工艺,以暴露出图案区以外的牺牲层,且留在图案区中的硬掩模层封住图案的上部之间的开口。移除牺牲层,而在相邻两个图案之间形成气隙。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,图案可为单层图案或多层堆叠图案。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,图案的材料包括金属或经掺杂的半导体材料。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,牺牲层的形成方法包括下列步骤。在基底上形成覆盖图案的牺牲材料层。移除部分牺牲材料层。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,牺牲材料层的材料例如是有机材料、无机材料或其混成材料。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,牺牲材料层的形成方法例如是涂布法、化学气相沉积法或物理气相沉积法。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,部分牺牲材料层的移除方法例如是回蚀刻法。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,牺牲层的上表面与图案的上表面之间的距离例如是图案之间的距离的1/2以上。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,硬掩模层的材料例如是氧化硅、氮化硅、氮氧化硅或含碳基介电材料。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,硬掩模层的形成方法例如是化学气相沉积法。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,硬掩模层例如是共形地形成。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,硬掩模层的厚度例如是图案之间的距离的1/2以上。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,在对硬掩模层进行回蚀刻制作工艺的步骤中,硬掩模层还包括在图案的外围形成间隙壁。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,牺牲层的移除方法例如是湿式移除法或干式移除法。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,在形成气隙之后,还包括形成覆盖硬掩模层与图案的介电层。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,介电层的材料例如是氧化硅、硼磷硅玻璃或含碳基材料。
依照本发明的一实施例所述,在上述的具有气隙的结构的形成方法中,介电层的形成方法例如是化学气相沉积法或涂布法。
基于上述,在本发明所提出的具有气隙的结构的形成方法中,由于可通过对硬掩模层进行回蚀刻制作工艺,以暴露出图案区以外的牺牲层,且位于图案区中的硬掩模层封住图案的上部之间的开口,再通过移除牺牲层而形成气隙,因此可使用简易的制作工艺形成具有高气隙比的结构。此外,本发明所提出的具有气隙的结构的形成方法可通过控制图案的上部之间的开口深度来硬掩模层填入开口的深度,进而控制气隙比。另外,在本发明所提出的具有气隙的结构的形成方法中,可通过图案区中的硬掩模层支撑图案的形状,而可避免图案发生弯曲(bending)或倒塌(collapse)的情况。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1A至图1G为本发明的一实施例的具有气隙的结构的制造流程的上视图。
图2A至图2G为沿着图1A至图1G中的I-I’剖面线的剖面图。
图3A至图3G为沿着图1A至图1G中的II-II’剖面线的剖面图。
符号说明
100:基底
102:图案区
104:图案
104a:上部
106:牺牲材料层
108:牺牲层
110:开口
112:硬掩模层
114:气隙
116:介电层
D1、D2:距离
S:间隙壁
T1:厚度
具体实施方式
图1A至图1G为本发明的一实施例的具有气隙的结构的制造流程的上视图。图2A至图2G为沿着图1A至图1G中的I-I’剖面线的剖面图。图3A至图3G为沿着图1A至图1G中的II-II’剖面线的剖面图。
在此实施例中,具有气隙的结构可为各种用于半导体元件的结构,例如是非挥发性存储器的堆叠结构或是字符线的阵列结构等。
首先,请同时参照图1A、图2A及图3A,在基底100的图案区102中形成多个图案104。基底100例如是硅基底。图案104可为单层图案104或多层堆叠图案104,如字符线图案或堆叠栅极图案。图案104的材料包括金属或经掺杂的半导体材料。图案104的形成方法例如是先在基底100上形成图案材料层(未绘示)之后,再对图案材料层进行图案化而形成,但本发明的图案104的形成方法并不限于此。
接着,请同时参照图1B、图2B及图3B,在基底100上形成覆盖图案104的牺牲材料层106。牺牲材料层106的材料例如是有机材料、无机材料或其混成材料。有机材料例如是光致抗蚀剂材料、或无需显影的光致抗蚀剂材料。无机材料例如是底部抗反射涂层材料(bottom anti-reflection coating,BARC)、含碳材料或非晶碳材料。
牺牲材料层106的形成方法例如是涂布法、化学气相沉积法或物理气相沉积法。
然后,请同时参照图1C、图2C及图3C,移除部分牺牲材料层106,以在基底100上形成牺牲层108,且牺牲层108的上表面低于图案104的上表面,而暴露出图案104的多个上部104a。此时,在相邻两个图案104的上部104a之间形成有开口110。部分牺牲材料层106的移除方法例如是回蚀刻法。牺牲层108的上表面与图案104的上表面之间的距离D1例如是图案104之间的距离D2的1/2以上。其中,图案104之间的距离D2也可称为特征尺寸(feature size)。在此实施例中,虽然牺牲层108是以上述方法形成,但本发明的牺牲层108的形成方法并不限于此。
之后,请同时参照图1D、图2D及图3D,形成覆盖牺牲层108及图案104的上部104a的硬掩模层112。此时,硬掩模层112例如是填满开口110,且位于图案区102中的硬掩模层112的上表面例如是高于图案104的上表面,但本发明并不限于此。硬掩模层112的材料与牺牲层108的材料例如是具有高蚀刻选择比。硬掩模层112的材料例如是氧化硅、氮化硅、氮氧化硅或含碳基介电材料。硬掩模层112的形成方法例如是化学气相沉积法,如原子层沉积法(atomic layer deposition,ALD)或分子层沉积法(molecular layerdeposition,MLD)。此外,当牺牲层108的材料为光致抗蚀剂材料时,牺牲层108的形成方法可选择采用低温的原子层沉积法或分子层沉积法,以避免对牺牲层108造成损害。在此实施例中,硬掩模层112例如是共形地形成,且硬掩模层112的厚度T1例如是图案104之间的距离D2的1/2以上,而使得共形的硬掩模层112可封住图案104的上部104a之间的开口110,但本发明的硬掩模层112的形成方法并不限于此。
接下来,请同时参照图1E、图2E及图3E,对硬掩模层112进行回蚀刻制作工艺,以暴露出图案区102以外的牺牲层108,且留在图案区102中的硬掩模层112封住图案104的上部104a之间的开口110。在对硬掩模层112进行回蚀刻制作工艺的步骤中,硬掩模层112可在图案104的外围形成间隙壁S。此外,经回蚀刻后的硬掩模层112可暴露出图案104的上表面,但本发明并不限于此。
再者,请同时参照图1F、图2F及图3F,移除牺牲层108,而在相邻两个图案104之间形成气隙114。牺牲层108的移除方法例如是湿式移除法或干式移除法。湿式移除法例如是湿式去光致抗蚀剂法或湿式蚀刻法。干式移除法例如是干式去光致抗蚀剂法或干式蚀刻法。由于牺牲层108的材料与硬掩模层112的材料可具有高蚀刻选择比(如,1:1000),所以可轻易地移除移除牺牲层108,且在移除牺牲层108之后,硬掩模层112仍然可封住图案104的上部104a之间的开口110。
随后,可依制作工艺需要选择性地形成覆盖硬掩模层112与图案104的介电层116。介电层116的材料例如是氧化硅、硼磷硅玻璃或含碳基材料。介电层116的形成方法例如是化学气相沉积法或涂布法。此外,在形成介电层116的步骤中,可通过制作工艺条件的控制来尽可能避免介电层116进入到气隙114中。
基于上述实施例可知,上述实施例所提出的具有气隙114的结构的形成方法中,由于可通过对硬掩模层112进行回蚀刻制作工艺,以暴露出图案区102以外的牺牲层108,且留在图案区102中的硬掩模层112封住图案104的上部104a之间的开口110,再通过移除牺牲层108而形成气隙114,因此可使用简易的制作工艺形成具有高气隙比的结构。此外,上述实施例所提出的方法可通过控制图案104的上部104a之间的开口110的深度来控制硬掩模层112填入开口110的深度,进而控制气隙比。另外,在上述实施例所提出的方法中,可通过图案区102中的硬掩模层112支撑图案104的形状,而可避免图案104发生弯曲或倒塌的情况。
此外,由于上述实施例所提出的具有气隙114的结构的形成方法具有上述特点,所以在将上述方法应用于半导体元件的制作时,可使得半导体元件具有较佳的电性表现,如可防止电容-电阻延迟或提高栅极耦合率。
综上所述,本发明的上述实施例所提出的具有气隙的结构的形成方法至少具有以下特点。上述实施例所提出的具有气隙的结构的形成方法可使用简易的制作工艺形成具有高气隙比的结构。此外,上述实施例所提出的具有气隙的结构的形成方法可控制气隙比。另外,上述实施例所提出的具有气隙的结构的形成方法可避免图案发生弯曲或倒塌的情况。
虽然已以实施例公开本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (17)
1.一种具有气隙的结构的形成方法,包括:
在一基底的一图案区中形成多个图案;
在该基底上形成一牺牲层,且该牺牲层的上表面低于该些图案的上表面,而暴露出该些图案的多个上部;
形成覆盖该牺牲层及该些图案的该些上部的一硬掩模层;
对该硬掩模层进行一回蚀刻制作工艺,以暴露出该图案区以外的该牺牲层,且留在该图案区中的该硬掩模层封住该些图案的该些上部之间的开口;以及
移除该牺牲层,而在相邻两个图案之间形成一气隙。
2.如权利要求1所述的具有气隙的结构的形成方法,其中该些图案包括单层图案或多层堆叠图案。
3.如权利要求1所述的具有气隙的结构的形成方法,其中该些图案的材料包括金属或经掺杂的半导体材料。
4.如权利要求1所述的具有气隙的结构的形成方法,其中该牺牲层的形成方法包括:
在该基底上形成覆盖该些图案的一牺牲材料层;
移除部分该牺牲材料层。
5.如权利要求4所述的具有气隙的结构的形成方法,其中该牺牲材料层的材料包括有机材料、无机材料或其混成材料。
6.如权利要求4所述的具有气隙的结构的形成方法,其中该牺牲材料层的形成方法包括涂布法、化学气相沉积法或物理气相沉积法。
7.如权利要求4所述的具有气隙的结构的形成方法,其中部分该牺牲材料层的移除方法包括回蚀刻法。
8.如权利要求1所述的具有气隙的结构的形成方法,其中该牺牲层的上表面与该些图案的上表面之间的距离为该些图案之间的距离的1/2以上。
9.如权利要求1所述的具有气隙的结构的形成方法,其中该硬掩模层的材料包括氧化硅、氮化硅、氮氧化硅或含碳基介电材料。
10.如权利要求1所述的具有气隙的结构的形成方法,其中该硬掩模层的形成方法包括化学气相沉积法。
11.如权利要求1所述的具有气隙的结构的形成方法,其中该硬掩模层是共形地形成。
12.如权利要求11所述的具有气隙的结构的形成方法,其中该硬掩模层的厚度为该些图案之间的距离的1/2以上。
13.如权利要求1所述的具有气隙的结构的形成方法,其中在对该硬掩模层进行该回蚀刻制作工艺的步骤中,该硬掩模层还包括在该些图案的外围形成一间隙壁。
14.如权利要求1所述的具有气隙的结构的形成方法,其中该牺牲层的移除方法包括湿式移除法或干式移除法。
15.如权利要求1所述的具有气隙的结构的形成方法,其中在形成该气隙之后,还包括形成覆盖该硬掩模层与该些图案的一介电层。
16.如权利要求15所述的具有气隙的结构的形成方法,其中该介电层的材料包括氧化硅、硼磷硅玻璃或含碳基材料。
17.如权利要求15所述的具有气隙的结构的形成方法,其中该介电层的形成方法包括化学气相沉积法或涂布法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103110712 | 2014-03-21 | ||
TW103110712A TWI555119B (zh) | 2014-03-21 | 2014-03-21 | 具有氣隙的結構的形成方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104934366A true CN104934366A (zh) | 2015-09-23 |
Family
ID=54121473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410129066.0A Pending CN104934366A (zh) | 2014-03-21 | 2014-04-01 | 具有气隙的结构的形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9230856B2 (zh) |
CN (1) | CN104934366A (zh) |
TW (1) | TWI555119B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102503215B1 (ko) | 2016-03-28 | 2023-02-24 | 삼성전자 주식회사 | 발광 소자 패키지 |
JP2020521972A (ja) | 2017-05-26 | 2020-07-27 | カリフォルニア インスティチュート オブ テクノロジー | 制御可能なスペクトル帯域幅及び解像度を有するスペクトルフィルタ |
CN113557415A (zh) | 2019-02-06 | 2021-10-26 | 加州理工学院 | 紧凑型高光谱中红外光谱仪 |
WO2021092579A1 (en) | 2019-11-08 | 2021-05-14 | California Institute Of Technology | Infrared spectrometer having dielectric-polymer-based spectral filter |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1495877A (zh) * | 2002-09-13 | 2004-05-12 | 希普雷公司 | 空气隙的形成 |
US20090267166A1 (en) * | 2008-04-23 | 2009-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
US20090280644A1 (en) * | 2008-05-06 | 2009-11-12 | Commissariat A L' Energie Atomique | Process for Producing Air Gaps in Microstructures, Especially of the Air Gap Interconnect Structure Type for Integrated Circuits |
US20120238099A1 (en) * | 2011-03-18 | 2012-09-20 | Kabushiki Kaisha Toshiba | Method of manufacturing electronic part |
US20130056817A1 (en) * | 2011-09-01 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including device isolation structures and method of forming the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7666754B2 (en) * | 2007-10-18 | 2010-02-23 | Tokyo Electron Limited | Method and system for forming an air gap structure |
US7772706B2 (en) | 2007-12-27 | 2010-08-10 | Intel Corporation | Air-gap ILD with unlanded vias |
KR101887413B1 (ko) | 2012-01-17 | 2018-08-10 | 삼성전자 주식회사 | 비휘발성 메모리 장치의 제조 방법 |
US20140138790A1 (en) * | 2012-11-21 | 2014-05-22 | Spansion Llc | Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same |
-
2014
- 2014-03-21 TW TW103110712A patent/TWI555119B/zh active
- 2014-04-01 CN CN201410129066.0A patent/CN104934366A/zh active Pending
- 2014-06-27 US US14/316,816 patent/US9230856B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1495877A (zh) * | 2002-09-13 | 2004-05-12 | 希普雷公司 | 空气隙的形成 |
US20090267166A1 (en) * | 2008-04-23 | 2009-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
US20090280644A1 (en) * | 2008-05-06 | 2009-11-12 | Commissariat A L' Energie Atomique | Process for Producing Air Gaps in Microstructures, Especially of the Air Gap Interconnect Structure Type for Integrated Circuits |
US20120238099A1 (en) * | 2011-03-18 | 2012-09-20 | Kabushiki Kaisha Toshiba | Method of manufacturing electronic part |
US20130056817A1 (en) * | 2011-09-01 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including device isolation structures and method of forming the same |
Also Published As
Publication number | Publication date |
---|---|
US20150270336A1 (en) | 2015-09-24 |
US9230856B2 (en) | 2016-01-05 |
TW201537675A (zh) | 2015-10-01 |
TWI555119B (zh) | 2016-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103515216B (zh) | 半导体元件的制造方法 | |
CN102751334B (zh) | 非易失性存储器元件及其制造方法 | |
CN106356374A (zh) | 快闪存储器及其制作方法 | |
US20150255476A1 (en) | Eeprom device and forming method and erasing method thereof | |
CN104934366A (zh) | 具有气隙的结构的形成方法 | |
CN110718460B (zh) | 一种改善sadp中奇偶效应的工艺方法 | |
CN104241204B (zh) | 3d nand闪存的形成方法 | |
CN104425220A (zh) | 图案的形成方法 | |
US8502297B2 (en) | Non-volatile memory and fabricating method thereof | |
CN104851886A (zh) | 分栅式存储器件及其制造方法 | |
CN105448703A (zh) | 一种刻蚀方法 | |
CN101303972A (zh) | 形成半导体器件微图案的方法 | |
KR101887413B1 (ko) | 비휘발성 메모리 장치의 제조 방법 | |
CN103208459B (zh) | 反及闸型快闪存储装置的制造方法 | |
US20160086966A1 (en) | Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same | |
CN105374753A (zh) | 一种存储器的制造方法 | |
CN107946304B (zh) | 一种用于尺寸缩减NORFlash单元工艺集成方法 | |
CN104952806A (zh) | 存储元件及其制造方法 | |
CN104517849A (zh) | 快闪存储器的形成方法 | |
KR20080081581A (ko) | 비휘발성 메모리 소자의 제조 방법 | |
CN105529331B (zh) | 非易失性存储器装置及其制造方法 | |
CN111863826A (zh) | 图形化掩膜的制作方法及三维nand存储器的制作方法 | |
TWI469269B (zh) | 嵌入式快閃記憶體之字元線的製造方法 | |
CN104362151A (zh) | Nor型闪存结构及其制造方法 | |
US20090047765A1 (en) | Method of manufacturing non-volatile memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150923 |