CN101283450A - 3d直通硅体系结构的集成微通道 - Google Patents
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Abstract
本发明的一些实施例包括与用于从3D直通硅体系结构除热的集成微通道相关的装置和方法。
Description
技术领域
本发明的实施例涉及微电子封装。具体来说,本发明的实施例涉及3D直通硅体系结构的除热。
背景技术
在微电子封装方面,正在不断努力生产更小且更快的电子器件。3D封装体系结构,包括堆叠管芯体系结构,可提供优于2D封装体系结构的几个优点(例如更小的尺寸和减小的互连距离)。
典型的2D封装体系结构可包括以倒装芯片方式连接到衬底的管芯,使得管芯的有源表面(包括器件和金属层)朝向衬底。然后可在管芯的暴露背面上提供冷却解决方案。冷却解决方案例如可包括热沉、集成放热器或风扇。
图1示出一种典型的3D封装100,包括衬底110、中央处理单元(CPU)管芯120、动态随机存取存储器(DRAM)管芯130、闪存管芯140和模拟管芯150。衬底110通常可包括印刷电路板或母板。为了使3D封装100工作,各组件的有源表面必须电连接到衬底110或者相邻组件的有源表面。为了互连这些有源表面,导电直通硅通路(TSV)160可贯穿这些组件。
例如,CPU管芯120可通过倒装芯片方式连接到衬底110,使得CPU管芯120的有源表面朝向衬底110。DRAM管芯130可采用凸点焊接连接到CPU管芯120,使得DRAM管芯130的有源表面朝向CPU管芯120的非有源表面。CPU管芯120的TSV然后可将DRAM管芯130的有源表面电连接到CPU管芯120的有源表面,或连接到衬底110。
通过类似的方式,可电互连各组件的有源表面。
附图说明
在附图的各图中通过实例而非限制方式示出了本发明,附图中相似参考标号表示相似单元,附图包括:
图1示出现有技术装置。
图2A-2B示出截面型侧视图,其中管芯附连到衬底,冷却解决方案附连到管芯,并且第二管芯附连到冷却解决方案。
图3A-3H示出用于形成具有微通道和通孔的冷却解决方案的方法。
具体实施方式
在各种实施例中,描述了与3D晶片或管芯封装体系结构相关的装置和方法。但是,实施各种实施例可以没有具体细节中的一个或多个,或者可以采用其它方法、材料或组件。在其它情况下,没有详细示出或描述众所周知的结构、材料或操作,以免模糊了本发明各种实施例的各个方面。类似地,为了便于说明,阐述了具体数量、材料和配置,以便提供对本发明的透彻理解。然而,没有这些具体细节也可实施本发明。此外,要理解,附图所示的各种实施例是说明性的表示,并不一定按比例绘制。
为了生产更小且更快的电子器件,可增大半导体芯片(或管芯)的封装密度。用于增大封装密度的一种解决方案可包括3D封装体系结构、诸如芯片堆叠。在操作中,堆叠中的芯片的有源区或区域可能发热。为了增强芯片的性能、使用具有增强性能能力的芯片或者实现高功率封装,可去除产生的热量。典型的3D封装体系结构可能没有提供任何热量去除或热解决方案。
通常,在单个芯片封装中,可用背面冷却解决方案、诸如集成放热器或风扇来去除热量。但是,在堆叠芯片布置中,可能使用背面冷却解决方案是行不通的,因为某些芯片的背面可能由于空间限制或者由于与电连接布线不一致而没有暴露出来。简言之,本发明的实施例可提供用于包含用于芯片间电布线的通路的堆叠芯片的冷却解决方案。
图2A和图2B示出根据本发明可提供堆叠芯片除热的装置200的截面视图。图2B示出沿图2A的线段A-A’得到的视图。
装置200包括衬底210、管芯220、冷却解决方案230和管芯270。冷却解决方案230包括衬底240、通孔260和微通道250。管芯220可包括通孔225。
衬底210可包括用于安装管芯220的任何适当衬底。在各种实施例中,衬底210可包括印刷电路板(PCB)、母板或内插板。衬底210可包括导电迹线和导电焊盘或凸点,以便帮助安装管芯220。管芯220可通过任何适当的技术安装到衬底210。在一个实施例中,管芯220可通过焊料凸点、铜凸点、导电连接焊盘(landing pad)等以倒装芯片方式连接到衬底210,使得管芯220的有源表面朝向衬底210。在一个实施例中,通孔225可提供通过管芯220的电布线。在一个实施例中,通孔225可包含铜。
冷却解决方案230和管芯220可通过任何适当的技术连接。在一个实施例中,冷却解决方案230和管芯220可通过扩散粘结进行连接。在一个实施例中,冷却解决方案230和管芯220均可包括硅,并且它们可通过硅-硅扩散粘结进行连接。在其它实施例中,冷却解决方案230可通过包括凸点或连接焊盘的凸点焊接技术附连到管芯220。在各种实施例中,冷却解决方案230的尺寸可比管芯220更大、更小或与其相同。
管芯270和冷却解决方案230可通过任何适当的直通硅通路技术进行连接。在一个实施例中,冷却解决方案230和管芯270可通过扩散粘结进行连接。在一个实施例中,冷却解决方案230和管芯270均可包括硅,并且它们可通过硅-硅扩散粘结进行连接。在其它实施例中,冷却解决方案230可通过包括凸点或连接焊盘的凸点焊接技术附连到管芯270。在各种实施例中,管芯270的有源表面可朝向冷却解决方案230,或者管芯270的有源表面可避开冷却解决方案230。在一个实施例中,管芯270可包括导电通孔(未示出),以便提供通过管芯270的电布线。在一个实施例中,冷却解决方案230可包括粘结焊盘或凸点,以帮助连接到管芯270。
管芯220和管芯270可包括任何适当的管芯、集成电路或芯片。例如,管芯220和管芯270可包括中央处理单元(CPU)、动态随机存取存储器(DRAM)、模拟器件或闪存管芯的任何组合。在一个实施例中,管芯220和管芯270均可包括CPU。在另一个实施例中,管芯220可包括CPU,而管芯270可包括DRAM管芯。在一个实施例中,管芯220可包括减薄的管芯。在另一个实施例中,管芯270可包括减薄的管芯。
此外,任何数量的附加管芯或者与冷却解决方案230类似的冷却解决方案可以任何布置堆叠在管芯270之上。堆叠在管芯270之上的管芯可包括CPU、DRAM、模拟器件或闪存的任何组合。在一个实施例中,管芯220可包括CPU,管芯270可包括DRAM,并且闪存和模拟器件可堆叠在管芯270之上。在另一个实施例中,管芯220和管芯270可包括CPU以及包含冷却解决方案的堆叠,并且DRAM管芯可堆叠在管芯270之上。
如上所述,冷却解决方案230包括衬底240、微通道250和通孔260。通孔260可延伸过衬底240,以便提供导电布线。在一个实施例中,通孔260可提供管芯220与管芯270之间的最小长度或直接电布线。通孔260可包括任何适当的导电材料或者这类材料的组合。在一个实施例中,通孔260可包含铜。衬底240可包括任何适当的材料。在一个实施例中,衬底240可包括硅,并且通孔260可以是直通硅通路(TSV)。
微通道250可在衬底240内为冷却剂(未示出)提供一个基本上封闭的区域。在一个实施例中,冷却剂可流过微通道250,以便从管芯220和管芯270去除热量。在一个实施例中,可提供单个微通道。单个微通道可基本上贯穿整个衬底240。在其它实施例中,可提供任何数量的分立微通道。在一个实施例中,微通道250可设计成符合管芯220、管芯270或者两者的除热需求。在一个实施例中,微通道250可对需要更大除热的管芯220或管芯270的区域、诸如热点提供更多微通道或通道区。
如图2B所示,可与微通道250一起提供输入/输出280。可根据需要提供任何数量的输入/输出。例如,如果使用单个微通道,则可使用单个或多个输入/输出。如果使用多个分立的微通道,则可为每个微通道提供至少一个输入/输出。
冷却剂可包括可除热的任何适当材料。在一个实施例中,冷却剂可包括液体。在一个实施例中,冷却剂可包括两相流动冷却剂。在一个实施例中,冷却剂可在冷却解决方案230与可冷却或冷凝冷却剂的一个或多个外部热交换器之间流动。
图3A-3H示出一种可提供根据本发明的冷却解决方案的方法。
图3A示出起始衬底300。衬底300可包括任何适当材料。在一个实施例中,衬底300可包括硅。在一个实施例中,衬底300可以是晶片。在另一个实施例中,衬底300可以是晶片的一部分或芯片。
如图3B所示,可在衬底300中形成开口310和开口320。在一个实施例中,开口310随后可形成微通道,而开口320随后可形成通孔,这在下面进一步论述。
开口310可以为任何适当宽度。在一个实施例中,开口310可具有大约5到10微米范围的宽度。在另一个实施例中,开口310可具有大约6到8微米范围的宽度。在一个实施例中,开口310可具有大约7到10微米范围的宽度。开口310还可具有任何适当的深度,只要它们比开口320浅。因此,开口310可被认为是浅开口,而开口320可被认为是深开口。在一个实施例中,开口310可具有大约50到100微米范围的深度。在另一个实施例中,开口310可具有大约60到80微米范围的深度。在一个实施例中,开口310可具有大约75到100微米范围的深度。
开口310可形成供给微通道的图案,该微通道基本上贯穿或穿过整个衬底300或者衬底300的一部分。例如,如果衬底300是芯片或管芯,则开口310可形成基本上贯穿整个衬底300的图案。在另一个实施例中,如果衬底300是晶片,则开口310可形成用于几个微通道布局的图案,其中每个微通道布局对应于一个管芯,使得该晶片可对准集成电路的晶片(图3G),以为各集成电路提供微通道布局。在另一个实施例中,开口310可形成为芯片或管芯提供多个分立微通道的图案。
开口320可具有任何尺寸,并且可符合3D体系结构的通孔的期望图案。在一个实施例中,当由上向下看时,开口320可具有一般圆形或椭圆形。开口320可具有任何深度。在一个实施例中,开口320的深度可在大约100到150微米范围内。在另一个实施例中,开口320的深度可在大约80到120微米范围内。在一个实施例中,开口320的深度可在大约50到100微米范围内。
在一个实施例中,开口320的深度可大于开口310的深度。在一个实施例中,开口320可比开口310深大约5到10微米。在另一个实施例中,开口320可比开口310深大约2到8微米。在一个实施例中,开口320可比开口310深大约10到20微米。在另一个实施例中,开口320可贯穿衬底300。
开口310和开口320可通过任何适当的技术形成。在一个实施例中,它们可通过两个光刻和蚀刻步骤形成。在一个实施例中,开口310和开口320可通过以下步骤形成:在衬底300上形成抗蚀图案,蚀刻衬底300的暴露部分以形成开口310或开口320,去除第一抗蚀图案,在衬底310上形成第二抗蚀图案,蚀刻衬底300的暴露部分以形成其余开口,以及去除第二抗蚀图案。
图3C示出第二起始衬底330。衬底330可包括任何适当的材料。在一个实施例中,衬底330可包括硅。在一个实施例中,衬底330可以是晶片。在另一个实施例中,衬底330可以是晶片的一部分或芯片。
如图3D所示,可在衬底330中形成开口340。在一个实施例中,其中一些开口340随后可形成一部分通孔。在一个实施例中,其中一些开口340随后可形成微通道的输入/输出。
开口340可具有任何适当的深度和宽度。在一个实施例中,开口340可具有对应于开口320的图案和尺寸的图案。开口340可通过任何适当的技术形成。在一个实施例中,它们可通过光刻和蚀刻形成。在一个实施例中,开口340可通过以下步骤形成:在衬底330上形成抗蚀图案,蚀刻衬底330的暴露部分以形成任一个开口340,以及去除抗蚀图案。在一个实施例中,开口340可贯穿衬底330。
如图3E所示,可对准和粘结衬底300和330。衬底300和330可通过任何适当的技术来对准和粘结。在一个实施例中,可对准衬底300和330,使得开口320和340基本上对准。在一个实施例中,多个开口340可与开口310对准,使得可形成微通道的输入和输出(为了清楚起见,这种对准在图3E中未示出)。在一个实施例中,衬底300和330可通过扩散粘结进行粘结。在另一个实施例中,衬底300和330可包括硅,并且它们可通过硅-硅扩散粘结进行粘结。在其它实施例中,可使用粘合剂或环氧树脂来粘结衬底300和330。
如图3F所示,可减薄衬底300和330以形成装置335。在所示的截面看来,衬底已经分开了;但是,衬底可能保持连续,如在其它可得到的截面示出的。图3F还示出通孔350的形成。在图3F中,为了清楚起见,未示出衬底300与330之间的任何接缝。衬底300和330可通过任何适当的技术、如背面研磨技术来减薄。
在所示的实施例中,粘结示为在减薄之前。但是,如果需要的话,减薄也可在粘结之前执行。在一个实施例中,衬底300可在粘结之前减薄。在另一个实施例中,衬底330可在粘结之前减薄。在一个实施例中,衬底300和330二者都可在粘结之前减薄。在另一个实施例中,可不需要减薄任一个衬底或两个衬底。
如图3G所示,装置335可对准并粘结到衬底360。衬底360可包括通孔370和凸点380。在一个实施例中,衬底360可包括芯片或管芯。在一个实施例中,衬底360可包括集成电路。在一些实施例中,衬底360可包括CPU、DRAM、模拟器件或闪存器件。在另一个实施例中,衬底360可包括集成电路的晶片。在另一个实施例中,装置335可对准衬底360,使得一些通孔350与一些通孔370对准。在各种实施例中,衬底360的有源表面可朝向装置335,或者有源表面可避开装置335。
如图3H所示,可形成导电通孔390。导电通孔390可包括任何适当的导电材料。在一个实施例中,导电通孔390可包括铜。导电通孔390可通过例如溅射、化学或物理汽相沉积、电镀、无电镀等任何适当的技术形成。
如图所示,装置335可粘结到衬底,并且可形成导电通孔。在其它实施例中,在形成导电通孔390之前装置335可不粘结到衬底。在一个实施例中,可在装置335中形成导电通孔390(图3F),以形成具有微通道和导电通孔的装置。以该方式形成的装置可通过例如扩散粘结或凸点焊接粘结等任何适当技术附连到管芯或多个管芯。
如图3I所示,装置335可对准并粘结到衬底410。衬底410可包括通孔420。在一个实施例中,衬底410可包括芯片或管芯。在一个实施例中,衬底410可包括集成电路。在一些实施例中,衬底410可包括CPU、DRAM、模拟器件或闪存器件。在另一个实施例中,衬底410可包括集成电路的晶片。在另一个实施例中,装置335可对准衬底400,使得一些通孔420与一些通孔370对准。在一个实施例中,衬底410可通过扩散粘结进行粘结。在一个实施例中,衬底410可通过凸点焊接粘结进行附连。在一个实施例中,可在衬底410、装置330或者它们两者上形成凸点,以便于粘结。在各种实施例中,衬底410的有源表面可朝向装置335,或者有源表面可避开装置335。
如果以上技术与具有分立集成电路组件和微通道冷却解决方案的晶片一起使用,则图3H或图3I的实施例可被切割成小片,以形成各个管芯和冷却解决方案组件。
本说明书中提到“一个实施例”或“实施例”是指结合该实施例所述的具体特征、结构、材料或特性包含在本发明的至少一个实施例中。因此,在本说明书中各种位置出现的短语“在一个实施例中”或“在实施例中”不一定指的是本发明的同一实施例。此外,具体特征、结构、材料或特性可通过任何适当方式结合在一个或多个实施例中。
要理解,以上描述是说明性而非限制性的。对于本领域的技术人员,在阅读了以上描述后,许多其它实施例是显然的。因此,应当参照所附权利要求书,连同这种权利要求书赋予权利的等效方案的整个范围一起来确定本发明的范围。
Claims (20)
1.一种用于从管芯除热的装置,包括:
衬底,包含用于冷却剂的基本上封闭的微通道;以及
导电通路,贯穿所述衬底。
2.如权利要求1所述的装置,其中所述微通道包括输入和输出。
3.如权利要求1所述的装置,其中所述衬底包括用于第二冷却剂的第二微通道。
4.如权利要求1所述的装置,其中所述微通道的宽度在大约5到10微米的范围,而高度在大约50到100微米的范围。
5.一种装置,包括:
集成电路管芯,包含通孔;以及
衬底,附连到所述集成电路管芯,其中所述衬底包括第二通孔和基本上封闭的微通道,以从所述集成电路管芯除热。
6.如权利要求5所述的装置,其中所述集成电路管芯和所述衬底通过硅-硅粘结剂进行粘结。
7.如权利要求5所述的装置,其中所述衬底与所述集成电路管芯的有源表面相对。
8.如权利要求7所述的装置,还包括:
第二衬底,电连接到所述集成电路管芯的所述有源表面。
9.如权利要求7所述的装置,还包括:
第二集成电路管芯,附连到所述衬底。
10.如权利要求9所述的装置,其中所述集成电路管芯包括中央处理单元,而所述第二集成电路管芯包括第二中央处理单元。
11.如权利要求9所述的装置,其中所述集成电路管芯包括中央处理单元,而所述第二集成电路管芯包括动态随机存取存储器。
12.如权利要求11所述的装置,还包括:闪存组件,附连到所述第二集成电路管芯,其中所述第二集成电路管芯包括第三通孔。
13.一种方法,包括:
在衬底中形成深开口和浅开口;
在第二衬底中形成开口;
粘结所述衬底和所述第二衬底,其中所述深开口和所述开口基本上对准;
减薄所述衬底;以及
在所述深开口和所述开口中形成导电通孔。
14.如权利要求13所述的方法,还包括:
减薄所述第二衬底。
15.如权利要求13所述的方法,其中所述第二衬底中的所述开口贯穿所述第二衬底。
16.如权利要求13所述的方法,其中所述衬底和所述第二衬底包括硅,并且其中粘结所述衬底和所述第二衬底包括硅-硅扩散粘结。
17.如权利要求13所述的方法,还包括:
切割所述衬底和所述第二衬底,其中所述衬底和所述第二衬底包括晶片。
18.如权利要求13所述的方法,其中在所述衬底中形成所述深开口和所述浅开口包括:
在所述衬底上形成第一图案;
蚀刻所述衬底由所述第一图案暴露的部分,以形成所述深开口;
在所述衬底上形成第二图案;以及
蚀刻所述衬底由所述第二图案暴露的部分,以形成所述浅开口。
19.如权利要求13所述的方法,还包括:
将所粘结的衬底和第二衬底安装到第三衬底,其中所述第三衬底包括集成电路和第二导电通孔。
20.如权利要求13所述的方法,其中在所述衬底中形成所述深开口和所述浅开口包括形成第二浅开口,其中在所述第二衬底中形成所述开口包括在所述第二衬底中形成第二开口,并且其中粘结所述衬底和所述第二衬底对准所述第二浅开口和所述第二开口,以形成微通道的输入。
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CN101283450B (zh) | 2012-05-02 |
JP5114414B2 (ja) | 2013-01-09 |
DE112006002686T5 (de) | 2008-10-02 |
US8012808B2 (en) | 2011-09-06 |
TW200731484A (en) | 2007-08-16 |
TWI371837B (en) | 2012-09-01 |
WO2007044577A1 (en) | 2007-04-19 |
JP2009512215A (ja) | 2009-03-19 |
US20070085198A1 (en) | 2007-04-19 |
US20090201643A1 (en) | 2009-08-13 |
US7432592B2 (en) | 2008-10-07 |
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