CN101192626A - 存储器件 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
Abstract
一种存储器件，其包括掺杂有第一导电杂质的区域；掺杂有第二导电杂质并形成在所述掺杂有第一导电杂质的区域上的第一多晶硅层；形成在所述第一多晶硅层上并掺杂有第一导电杂质的第二多晶硅层；形成在所述第一多晶硅层横向侧的电荷捕获层；和形成在所述电荷捕获层横向侧的控制栅极。
Description
背景技术
快闪存储器件具有EPROM和EEPROM的优点，EPROM具有编程和擦除特性，EEPROM具有电编程和擦除特性。快闪存储器件能够存储1位数据并进行电编程和擦除操作。
如在例图1中所示，快闪存储器件可以包括形成在硅半导体衬底1上和/或上方的薄隧道氧化物层3、形成在隧道氧化物层3上和/或上方的浮置栅极4、形成在浮置栅极4上和/或上方的绝缘层5、形成在绝缘层5上和/或上方的控制栅极6、和形成在硅半导体衬底1上和/或上方的源极/漏极区2。
发明内容
实施方案涉及一种存储器件，其包括：掺杂有第一导电杂质的区域；掺杂有第二导电杂质并形成在所述掺杂有第一导电杂质的区域上和/或上方的第一多晶硅层；形成在所述第一多晶硅层上和/或上方并掺杂有第一导电杂质的第二多晶硅层；形成在所述第一多晶硅层的横向侧的电荷捕获层；和形成在所述电荷捕获层的横向侧的控制栅极。
实施方案涉及一种存储器件，其包括：掺杂有第一导电杂质的区域；掺杂有第二导电杂质并形成在所述掺杂有第一导电杂质的区域上和/或上方的第一多晶硅层；形成在所述第一多晶硅层上和/或上方并掺杂有第一导电杂质的第二多晶硅层；形成在所述第一多晶硅层的两个横向侧的电荷捕获层；和形成在所述电荷捕获层的横向侧的第一和第二控制栅极。
实施方案涉及一种存储器件，其包括：形成在半导体衬底中的源极和漏极区；形成在所述源极和漏极区之间的沟道区；与所述沟道区相邻的电荷捕获层；和与所述电荷捕获层相邻的控制栅极，其中所述源极区、沟道区和漏极区垂直对准，并且所述沟道区、电荷捕获层和控制栅极水平对准。
实施方案涉及一种存储器件，其包括：形成在半导体衬底中的源极区、共沟道区和漏极区，其中所述源极区、共沟道区和漏极区沿第一方向对准；在所述共沟道区中捕获电荷的多个电荷捕获层；和向其施加控制电压的多个控制栅极。
附图说明
例图1示出快闪存储器件。
例图2～9示出根据实施方案的快闪存储器件。
具体实施方式
在以下实施方案的说明中，当描述层(膜)、区域、图案或结构形成形成在层(膜)、区域、图案或结构的“上/上面/上方/上部”或“下/下面/下方/下部″时，是指它们直接与所述层(膜)、区域、图案或结构接触，或它们通过在其间插入其它的层(膜)、区域、图案或结构而与所述层(膜)、区域、图案或结构间接接触。因此，其含义必须基于本发明的范围来确定。
如在例图2和3中说明的，根据实施方案的快闪存储器件可包括半导体衬底，在其上形成掺杂有第一导电杂质的区域110。第一导电杂质可以包括N-型杂质如磷(P)或砷(As)，或P-型杂质如硼(B)。根据实施方案，第一导电杂质包括N-型杂质。此外，所述半导体衬底可以掺杂有N-型杂质。
可以在掺杂有第一导电杂质的区域110上和/或上方形成第一多晶硅层120。第一多晶硅层120可以掺杂有不同于所述第一导电杂质的第二导电杂质。如果第一导电杂质是N-型杂质，那么第二导电杂质是P-型杂质，因此第一多晶硅层120形成P-阱。
可以在第一多晶硅层120上和/或上方形成第二多晶硅层130。第二多晶硅层130可以掺杂有第一导电杂质。
因此，掺杂有第一导电杂质的区域110、第一多晶硅层120和第二多晶硅层130可以形成垂直堆叠结构，其顺序掺杂有N-型杂质/P-型杂质/N-型杂质。
可以在第一多晶硅层120和第二多晶硅层130的两侧横向形成电荷捕获层140。电荷捕获层140可以包括绝缘层。如例图3中所示，根据实施方案，电荷捕获层140可以包括ONO层，其中顺序沉积第一氧化物层141、氮化物层142和第二氧化物层143。具有ONO层的电荷捕获层140可包括选自SiO2-Si3N4-SiO2、SiO2-Si3N4-Al2O3、SiO2-Si3N4-Al2O3、和SiO2-Si3N4-SiO2-Si3N4-SiO2中的一种。
可以在电荷捕获层140上和/或上方形成包括多晶硅的第一控制栅极150和第二控制栅极160。具体而言，第一控制栅极150和第二控制栅极160可以形成在掺杂有第一导电杂质的区域110上和/或上方和形成在第一多晶硅层120和第二多晶硅层130的横向两侧。
如例图4中所示，根据实施方案的快闪存储器件可以包括形成得比第一控制栅极150和第二控制栅极160更高的第二多晶硅层130。
如例图5中所示，根据实施方案的快闪存储器件可以包括形成在第一多晶硅层120和第二多晶硅层130的横向侧的电荷捕获层140。电荷捕获层可通过顺序沉积第一氧化物层141、氮化物层142和第二氧化物层143形成具有ONO结构。具有ONO结构的电荷捕获层140可以包括选自SiO2-Si3N4-SiO2、SiO2-Si3N4-Al2O3、SiO2-Si3N4-Al2O3和SiO2-Si3N4-SiO2-Si3N4-SiO2中的一种。
另外，具有不同于电荷捕获层140的ONO层的结构的绝缘层144可以形成在第一控制栅极150和第二控制栅极160与掺杂有第一导电杂质的区域110之间。
如例图6中所示，根据实施方案的快闪存储器件可以包括从掺杂有第一导电杂质的区域110的预定部分突出的突出部111。第一多晶硅层120可以形成在突出部111上和/或上方。突出部111可以包括与掺杂有第一导电杂质的区域110的材料相同的材料。
如例图7中所示，根据实施方案的快闪存储器件可以包括形成在半导体衬底100上和/或上方的绝缘层105并包括沟槽103。掺杂有第一导电杂质的区域110可以形成在沟槽103中。
如例图8中所示，根据实施方案的快闪存储器件可以包括半导体衬底100，其是P-型半导体衬底。掺杂有第一导电杂质的区域110可以作为N-型多晶硅层形成在P-型半导体衬底100的预定区域上和/或上方。另外，绝缘层105可以形成在掺杂有第一导电杂质的区域110的两个横向侧面。
如例图9中所示，根据实施方案的快闪存储器件可以包括掺杂有第二杂质并包括P-型多晶硅的区域210。可以在掺杂有第二杂质的区域210上和/或上方形成掺杂有N-型杂质以形成N-阱的第一多晶硅层220和掺杂有P-型杂质的第二多晶硅层230。电荷捕获层240可以形成在第一多晶硅层220和第二多晶硅层230的两个横向侧。包括多晶硅的第一控制栅极250和第二控制栅极260可以形成在电荷捕获层240上和/或上方。
根据实施方案，包括掺杂有第一杂质的区域110和掺杂有第二杂质的区域210的快闪存储器件可以与第二多晶硅层130和230共同形成具有垂直结构的源极/漏极区。此外，掺杂有P-型杂质以形成P-阱的第一多晶硅层120和掺杂有N-型杂质以形成N-阱的第一多晶硅层220可以用作作为电荷(或空穴)通道的沟道。
电荷捕获层140可以形成为具有ONO层，所述ONO层包括顺序沉积的第一氧化物层141、氮化物层142和第二氧化物层143，电荷可以在氮化物层142上编程或擦除，第一氧化物层141可用作隧道氧化物层，以将电荷从沟道引导到氮化物物层142，并且第二氧化层143可用作阻挡氧化物层，以防止电荷从氮化物层142移动到第一控制栅极150和第二控制栅极160。
同时，当对第一控制栅极150施加电压时，电荷(或空穴)从掺杂有第一杂质并作为源极的区域110中释放，并且释放出的电荷可以在电荷捕获层140的氮化物层142中编程。然后，如果关闭施加于第一控制栅极150的电压，则可以擦除在氮化物层142中编程的电荷(或空穴)。
同样地，当对第二控制栅极160施加电压时，从掺杂有第一杂质并且作为源极的区域110释放出电荷(或空穴)，并且释放出的电荷可以在电荷捕获层140的氮化物层142中编程。然后，如果关闭施加于第二控制栅极160的电压，可以擦除在氮化物层142中编程的电荷(或空穴)。
因此，根据实施方案，在形成于具有垂直结构的源极和漏极之间的沟道的两侧提供电荷捕获层，使得快闪存储器件可储存2位数据而不增加快闪存储器件的尺寸。另外，如果快闪存储器件与多级位技术结合，那么一个单元可存储四位到八位。
在本说明书中对“一个实施方案”、“实施方案”、“例示实施方案”等的任何引用都表示与实施方案相关的具体特征、结构、或性能包括在本发明的至少一个实施方案中。在本说明书中不同地方出现的这些术语不必都表示相同的实施方案。此外，当关于任何实施方案记载具体特征、结构或性能时，认为其在本领域技术人员实现与其他的实施方案相关这些特征、结构或性能的范围内。
尽管已经在本文中描述了实施方案，但应该理解本领域技术人员可以设计大量其它的变化和实施方案，而这些也在本公开内容原理的精神和范围内。更具体地，在公开文件、附图和所附的权利要求的范围内，在本发明的组合排列的构件和/或结构中可能具有各种变化和变型。除构件和/或结构的变化和变型之外，对本领域技术人员而言，可替代的用途将是显而易见的。
Claims (20)
1.一种器件，包括：
掺杂有第一导电杂质的区域；
掺杂有第二导电杂质并形成在所述掺杂有第一导电杂质的区域上的第一多晶硅层；
形成在所述第一多晶硅层上并掺杂有第一导电杂质的第二多晶硅层；
形成在所述第一多晶硅层的横向侧的电荷捕获层；和
形成在所述电荷捕获层的横向侧的控制栅极。
2.权利要求1的器件，其中所述电荷捕获层包括第一氧化物层、氮化物层和第二氧化物层。
3.权利要求1的器件，其中所述电荷捕获层包括选自SiO2-Si3N4-SiO2、SiO2-Si3N4-Al2O3、SiO2-Si3N4-Al2O3和SiO2-Si3N4-SiO2-Si3N4-SiO2中的一种。
4.权利要求1的器件，其中所述第二多晶硅层突出超过所述控制栅极。
5.权利要求1的器件，还包括形成在所述掺杂有第一导电杂质的区域上的突出部，并所述第一多晶硅层形成在所述突出部上。
6.权利要求1的器件，还包括形成在所述掺杂有第一导电杂质的区域两侧的绝缘层。
7.一种器件，包括：
掺杂有第一导电杂质的区域；
掺杂有第二导电杂质并形成在所述掺杂有第一导电杂质的区域上的第一多晶硅层；
形成在所述第一多晶硅层上并掺杂有第一导电杂质的第二多晶硅层；
形成在所述第一多晶硅层的两个横向侧的电荷捕获层；和
形成在所述电荷捕获层的横向侧的第一和第二控制栅极。
8.权利要求7的器件，其中所述电荷捕获层包含第一氧化物层、氮化物层和第二氧化物层。
9.权利要求7的器件，其中所述电荷捕获层包括选自SiO2-Si3N4-SiO2、SiO2-Si3N4-Al2O3、SiO2-Si3N4-Al2O3、和SiO2-Si3N4-SiO2-Si3N4-SiO2中的一种。
10.权利要求7的器件，其中所述第二多晶硅层突出超过所述控制栅极。
11.权利要求7的器件，还包括形成在所述掺杂有第一导电杂质的区域上的突出部，并且所述第一多晶硅层形成在所述突出部上。
12.权利要求7的器件，还包括形成在所述掺杂有第一导电杂质的区域两侧的绝缘层。
13.权利要求7的器件，其中所述电荷捕获层形成在所述第二多晶硅层的两侧。
14.权利要求7的器件，其中所述电荷捕获层形成在所述掺杂有第一导电杂质的区域与所述第一和第二栅极之间。
15.权利要求7的器件，还包括形成在所述掺杂有第一导电杂质的区域与所述第一和第二栅极之间的绝缘层。
16.一种存储器件，包括：
源极区；
漏极区；
形成在所述源极区与漏极区之间的沟道区；
与所述沟道区相邻的至少一个电荷捕获层；和
与所述电荷捕获层相邻的至少一个控制栅极，
其中所述源极区、所述沟道区和所述漏极区垂直对准，并且所述沟道区、所述电荷捕获层和所述控制栅极水平对准。
17.权利要求16的器件，其中所述沟道区、所述电荷捕获层和所述控制栅极的至少一些部分在相同的水平面上对准。
18.权利要求16的器件，其中所述电荷捕获层包括水平对准的第一氧化物层、氮化物层和第二氧化物层。
19.权利要求16的器件，其中所述电荷捕获层形成在所述第一多晶硅层的两侧。
20.权利要求16的器件，其中所述至少一个电荷捕获层包括在所述沟道区中捕获电荷的多个电荷捕获层，并且所述至少一个控制栅极包括向其施加控制电压的多个控制栅极。
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| JP (1) | JP2008141173A (zh) |
| KR (1) | KR100776139B1 (zh) |
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| DE (1) | DE102007048345B4 (zh) |
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| CN108346448A (zh) * | 2018-03-14 | 2018-07-31 | 上海华虹宏力半导体制造有限公司 | 闪存存储器及其控制方法 |
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- 2007-10-18 JP JP2007270925A patent/JP2008141173A/ja active Pending
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346448A (zh) * | 2018-03-14 | 2018-07-31 | 上海华虹宏力半导体制造有限公司 | 闪存存储器及其控制方法 |
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| Publication number | Publication date |
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| US20080128790A1 (en) | 2008-06-05 |
| CN101192626B (zh) | 2010-06-09 |
| JP2008141173A (ja) | 2008-06-19 |
| DE102007048345A1 (de) | 2008-06-05 |
| KR100776139B1 (ko) | 2007-11-15 |
| DE102007048345B4 (de) | 2010-07-01 |
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