CN1653615A - 非易失半导体闪存及制造方法 - Google Patents

非易失半导体闪存及制造方法 Download PDF

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CN1653615A
CN1653615A CNA038106345A CN03810634A CN1653615A CN 1653615 A CN1653615 A CN 1653615A CN A038106345 A CNA038106345 A CN A038106345A CN 03810634 A CN03810634 A CN 03810634A CN 1653615 A CN1653615 A CN 1653615A
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gate electrode
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F·霍夫曼恩
E·兰德格拉夫
W·雷斯纳
M·斯佩奇特
M·斯塔德勒
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Infineon Technologies AG
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Abstract

在半导体内存中，具有捕捉层(5)或浮动栅电极作为储存媒体的多重鳍式场效晶体管(FinFET)配置乃存在于一由半导体材料制成的鳍片(3)的顶侧，该栅电极(4)材料亦存在于该等鳍片之两侧壁，以形成侧壁晶体管；而在栅电极之间则形成了属于所对应鳍片的一字符线的部分。

Description

非易失半导体闪存及制造方法
将浮动栅记忆晶体管的尺寸缩小至小于100nm对晶体管的性质具有不利的影响，其系导因于并非所有的尺寸都能够缩小至同一规模大小；这是因为为了将资料储存达至少十年之年限，栅介电质必须具有一特定之最小厚度。
由Y.K.Choi等人公开的“Sub-20nm CMOS FinFET Technologies”International electron Device Meeting(IEDM)2001描述了一种具有双栅的FinFET。FinFET包括半导体材料的鳍或窄带，其将源区和漏区彼此连接、作为沟道区提供并提供有啮合其上的在横向形式为桥的带状栅电极。
本发明的目的之一在于提供一具有高储存密度之非易失性快闪半导体内存，其系能以一低成本而加以制造；除此之外，本发明并提供一相关的制造方法。
此一目的可藉由具有如权利要求1之半导体内存而达成；进一步的配置则揭露于其附属项中。
半导体内存具有一位线与字符线之列与行的排列，在一字符线与一位线的交叉点上，则配置了一记忆单元。该等位线系以一由半导体材料所制得之鳍片(fin)而各连接至传导性掺杂之源极/漏极区，其中在两个沿字符线方向而相邻的源极/漏极区之间，则各具一沟渠区。
该沟槽区能够藉由一栅电极而被驱动，该栅电极系连接至一字符线并与该沟槽区之间藉由一栅介电质而呈电性绝缘。在该鳍片之顶侧具有一储存层，特别是一传导性浮动栅电极、或是一氧化物-氮化物-氧化物结构层(捕捉层)，其系用于藉由将热电子射入沟渠中而对该记忆单元进行编程，以及用于藉由将热电洞射入沟渠中而对该记忆单元进行拭除，其系位于该栅电极与该半导体材料鳍片之间。
在半导体内存的情形中，具有捕捉层或是浮动栅电极作为储存媒体之多重鳍式场效晶体管(FinFET)配置系存在于一由半导体材料所制成之鳍片的顶侧，该栅电极之材料若适合用来控制栅电极，则同样存在于该等鳍片之两侧壁，以形成侧壁晶体管；而在栅电极之间则形成了属于所对应鳍片之字符线的部分。
此外，该两侧壁晶体管与在储存媒体(顶部晶体管)下方之信道最好是用来读取个别的记忆单元，侧壁晶体管与顶部晶体管之电荷电压系以该储存媒体之一电位能函数而偏移，因此能够使用一高读取电流与低电压，利用该侧壁鳍式场效晶体管来读取内存之内容，而不像传统之浮动栅极晶体管；电荷载子能够储存于在源极侧与漏极侧之储存媒体，使得每一记忆晶体管能够储存两位，这使其储存密度可以达到每一位为2F2；举例而言，这样的编程可以藉由捕捉信道热电子(CHEs)而产生，该内存能够被配置为一次编程内存或是可再编程内存。
关于该半导体内存与一相关的制作方法之实例系参考第1图至第8图而更加详细说明如下，其中：
第1图系说明了该半导体内存之一平行于两平行位线间之一截面；
第2图系说明了该半导体内存之一平行于一字符线之一截面；
第3图系说明了该半导体内存之一概略之平面图；
第4图与第5图系说明了在该内存制造方法中的中间产品剖面图，该剖面系平行于两位线间之位线；以及
第6图至第8图系说明了在该内存造方法中沿一位线之中间产品。
第1图说明了该半导体内存之一平行于两平行位线间、且横向于字符线之一截面；该半导体内存最好是制作于一SOI(Silicon OnInsulator)基板上；一厚的硅块层1系与一薄的绝缘层2同时提供，欲作为组件之一主要硅薄层系配置于其上。
在该半导体内存中，此一主要硅层系图形化以形成个别的鳍片3或网状结构；其中有复数鳍片3或网状结构系彼此存在并彼此平行排列。
该等鳍片或是网状结构系以栅电极4而桥接，在该等鳍片与该等栅电极之间具有一薄的介电质以作为栅极介电质(栅极氧化物)，其未独立表示于该等图式中。一储存层5系位于该等鳍片3之顶侧与该栅电极4之间；举例而言，此一储存层可为一捕捉信道热电子(捕捉层)之膜层序列，一ONO层(氧化物-氮化物-氧化物层)系特别适合于此一构想；此外，也可以使用一浮动栅电极作为储存媒体，此一电极系藉由绝缘材料而与该栅电极4所有通路以及该等鳍片3之半导体材料电性绝缘；此一形式之储存媒体以及一编程与拭除操作本身，系从其它半导体内存而被了解。
在该等个别之鳍片之间存在有一介电质6，举例而言，其可为一氮化物，或是在此例中系为一氮化硅；该栅电极可为一金属或最好是多晶硅，其系适于传导性掺杂，在其顶侧具有一电绝缘层7，例如可以使用TEOS(原硅酸四乙酯)；此一形式之膜层制造系已被了解。
第2图说明了该半导体内存之一平行于一字符线之一截面；在此一截面中，该鳍片3系与该图式之平面平行。掺杂区系形成于该鳍片3中而作为源极/漏极区8，该等位线9系用以作为掺杂区，最好是以该半导体材料之一薄阻障层10隔开；举例而言，该等位线系为钨。隔离组件11最好是由氮化物或二氧化硅所形成，其配置于该等位线9之侧边已将该等位线9与该栅电极4电性绝缘。
第3图系以一概略的平面图来说明该等字符线WL1、WL2、...与该等位线BL0、BL1、BL2...之排列方式；第3图亦指出在第1图与第2图中所表示之截面的位置。如覆盖之轮廓线所示，由半导体材料所制成之该等鳍片3在图式中系以虚线表示；以一规则间隔排列之该源极/漏极区8系已清楚标示；该字符线至该栅电极4系形成于该等位线之间，在位线区域中的字符线结构将于下文中更详细加以描述；该字符线在该等鳍片3之侧壁处具有连续部分。
第4图系藉由一较佳制造方法之中间产品来说明根据第1图之一剖面图。由一SOI基板开始，该SOI基板含有一所使用之主要硅层，且具有一硅块层1与一绝缘层2、一氮化物层12与一沉积于此一基板顶侧之多晶硅层13；该等膜层系根据如第4图所示之截面并利用一光罩技术而被蚀刻，以产生鳍片3，其彼此系呈平行之取向；并移除剩下的阻罩。该等鳍片系个别藉由一层多晶硅而三边环绕，邻近字符线之多晶硅层系藉由一间隔蚀刻而彼此分离；第4图中之该多晶硅层13系于两位线之间，用以连接个别鳍片间彼此之位于侧面的该等多晶硅层。
此外，电性绝缘或具有一电性绝缘部分之该储存层5系可作用为一栅极介电质，为了将字符线从彼此隔离，该栅电极系于该等鳍片3之末端处分离；在该等鳍片间之间隔中，系填充了一电性绝缘介电质6，最好是氮化硅。在去除了该等鳍片3顶侧之介电质材料后，一电绝缘层7系被形成，其最好藉由TOES而形成。
第6图说明了该制造方法在沿一位线之截面的中间产品；在如第5图所示之电绝缘层7形成之后，该栅电极4之材料系被回蚀于一与第6图所示之部分分开之区域中，此系藉由一合适之光罩技术而完成，其涵盖了在所欲位线之间的区域，因此只有所欲去除的相关膜层(TOES、多晶硅)部分会被适当地回蚀。
根据第7图，在该相关区域中，在形成字符线之该等栅电极4材料的残余部分上所形成之孔洞系以电型绝缘材料14填充并加以磨平；在该等栅电极的边缘处，在该源极/漏极区之间的该电性绝缘材料14系藉由一间隔蚀刻而回蚀，以形成该栅电极4之传导性材料的侧面覆盖；在此一方式中，可保护该侧之该储存层5并避免其与字符线间之短路发生。
根据第8图中所说明的，在沿着所欲位线之区域进行源极与漏极注入(n+注入)之后，该位线所欲材料系用于该半导体内存之顶侧；首先，较佳的是，举例而言，同样提供一扩散阻障10，使用于由钨所形成之位线9，以避免该金属向外扩散至该半导体内存中；该等位线系图形化为彼此平行之细长段，表面则可藉由CMP(化学机械光)加以磨平。
该等记忆单元系藉由该等鳍片侧壁之两晶体管以及位于该储存媒体下方之晶体管而加以读取，该等栅电极4系个别形成于位线间之该等鳍片上，因而得以桥接该等鳍片；该侧壁晶体管具有高激活电流(oncurrent)，假设其具有相当于氧化物厚度之栅极介电质；由于侧栅极效应，该储存层藉由部分偏移了门槛电压的方式而影响该鳍式场效晶体管(FinFET)之激活电流。其优势包含了：
a)由于其简化之制程而具有低生产成本；
b)于低电压具有更高的读取电流；
c)与传统鳍式场效晶体管(FinFET)间距有兼容性；以及
d)每一位可具有2F2之高储存密度。
因此，当该半导体内存作为一OTP(一次编程)内存之用时，可大幅节省了一次6V编程电压所需要之电荷泵送区域面积；在此一情形中，该等侧壁晶体管系作为读取晶体管，而该栅电极之部分与在鳍片顶侧之储存层系特别用以提供储存操作，相较于传统之内存，此方式可于较低电压处产生一个较高的读取电流，以及产生一较短的读取时间。
组件符号说明
1   硅块层
2   绝缘层
3   鳍片
4   栅电极
5   储存层
6   介电质
7   绝缘层
8   源极/漏极区
9   位线
10  阻障层
11  隔离组件
12  氮化物层
13  多硅层
14  电绝缘材料
BL  位线
WL  字符线

Claims (5)

1.一半导体内存，具有位线(BL)与字符线(WL)的一行与列的排列方式，其中
-一记忆单元，系配置于一位线与一字符线的一交叉点；
-该等位线乃连接至一半导体材料中的导电性掺杂源极/漏极区(8)；
-在沿字符方向上彼此相距一距离的各两源极/漏极区(8)之间有一沟渠区域，该沟渠区域能够藉由一连接至一字符线并与该沟渠区域电性绝缘的一栅电极(4)而驱动；
-在栅电极(4)与半导体材料之间具有一储存层(5)，其用于该记忆单元的编程，
其特征在于：
该源极/漏极区(8)是形成于该半导体材料的鳍片(3)中，
其彼此间以一距离平行排列，
各储存层(5)乃位在一鳍片(3)的顶侧，
该栅电极(4)配置于该鳍片(3)的顶侧与侧壁上，以及
该字符线乃由栅电极材料的部分所形成、其乃涂布于该鳍片(3)的该等侧壁，且栅电极(4)乃沿着该鳍片(3)方向而彼此电性连接。
2.如权利要求1之半导体内存，其中该记忆层(5)为一氧化物-氮化物-氧化物膜层序列。
3.如权利要求1之半导体内存，其中该记忆层(5)为一浮动栅电极，其系藉由一绝缘材料而与该栅电极(4)周围的所有通路、该鳍片(3)之半导体材料电性绝缘。
4.如权利要求1至3中任一项之半导体内存，其中该等鳍片(3)的形式乃为一SOI基板的主要硅层的细长状部分。
5.一种半导体内存的制造方法，该半导体内存具有一位线(BL)与字符线(WL)的一行与列的排列方式，其中
-一记忆单元，系配置于一位线与一字符线的一交叉点；
-该等位线乃连接至一半导体材料中的导电性掺杂源极/漏极区(8)；
-在沿字符方向上彼此相距一距离的各两源极/漏极区(8)之间有一沟渠区域，该沟渠区域能够藉由一连接至一字符线并与该沟渠区域电性绝缘的一栅电极(4)而驱动；
-在栅电极(4)与半导体材料之间具有一储存层(5)，其用于该记忆单元的编程，
其特征在于：
在一第一步骤中，半导体材料鳍片(3)被形成，其彼此间以一距离而平行排列，且一储存层(5)乃应用至一鳍片(3)的一顶侧；
在一第二步骤中，一薄介电层乃设于该等鳍片之表面作为栅介电质；以及
在一第三步骤中，所提供的一栅电极(4)材料乃用于该鳍片(3)的顶侧与侧壁；
在一第四步骤中，一介电质(6)乃被导入该等鳍片(3)之间；
在一第五步骤中，利用一屏蔽技术，在该等栅电极之间的区域对该等栅电极材料回蚀以形成字符线，且将掺杂注入引进至该等鳍片，以形成源极/漏极区(8)；
在一第六步骤中，横向于该等鳍片的位线(9)乃由电传导材料形成，该等位线乃将该源极/漏极区电传导连接至另一个与该字符线横向的源极/漏极区。
CNB038106345A 2002-05-10 2003-05-09 非易失半导体存储器及制造方法 Expired - Fee Related CN100359696C (zh)

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