CN100359696C - 非易失半导体存储器及制造方法 - Google Patents

非易失半导体存储器及制造方法 Download PDF

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CN100359696C
CN100359696C CNB038106345A CN03810634A CN100359696C CN 100359696 C CN100359696 C CN 100359696C CN B038106345 A CNB038106345 A CN B038106345A CN 03810634 A CN03810634 A CN 03810634A CN 100359696 C CN100359696 C CN 100359696C
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gate electrode
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F·霍夫曼恩
E·兰德格拉夫
W·雷斯纳
M·斯佩奇特
M·斯塔德勒
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Infineon Technologies AG
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Abstract

本发明公开一种非易失半导体存储器及制造方法。在半导体存储器中，具有捕捉层(5)或浮动栅电极作为储存媒体的多重鳍式场效应晶体管(FinFET)配置存在于一由半导体材料制成的鳍片(3)的顶侧，该栅电极(4)材料亦存在于该鳍片的两侧壁，以形成侧壁晶体管；而在栅电极之间则形成了属于所对应鳍片的一字线的部分。

Description

非易失半导体存储器及制造方法
将浮动栅存储晶体管的尺寸缩小至小于100nm对晶体管的性质具有不利的影响，这是由于并非所有的尺寸都能够缩小至同一规模大小；这是因为为了将资料储存达至少十年的年限，栅介电质必须具有一特定的最小厚度。
由Y.K.Choi等人公开的“Sub-20nm CMOS FinFET Technologies”International electron Device Meeting(IEDM)2001描述了一种具有双栅的FinFET。FinFET包括半导体材料的鳍或窄带，其将源区和漏区彼此连接、作为沟道区并提供有啮合其上的在横向形式为桥的带状栅电极。
本发明的目的之一在于提供一具有高储存密度的非易失性快闪半导体存储器，其能以一低成本而加以制造；除此之外，本发明并提供一相关的制造方法。
为达此一目的，本发明提供一种半导体存储器，其具有位线与字线的一行列排列方式，其中所述半导体存储器还具有一存储单元，排列于一位线与一字线的一交叉点；所述位线连接至一半导体材料中的导电性掺杂源极/漏极区；在沿字线方向上彼此相距一距离的各两源极/漏极区之间有一沟道区域，该沟道区域能够由一连接至一字线并与该沟道区域电性绝缘的一栅电极而驱动；在栅电极与半导体材料之间具有一存储层，其用于该存储单元的编程；所述半导体存储器的特征在于该源极/漏极区是形成于该半导体材料的鳍片中，所述鳍片彼此间以一距离平行排列，各储存层位于一鳍片的顶侧，该栅电极排列于该鳍片的顶侧与侧壁上，以及该字线由施加于该鳍片的所述侧壁的部分栅电极材料所形成，且栅电极沿着该鳍片方向而彼此电性连接。
半导体存储器具有一位线与字线的列与行的排列，在一字线与一位线的交叉点上，则配置了一存储单元。该位线以一由半导体材料所制得的鳍片(fin)而各连接至导电性掺杂的源极/漏极区，其中在两个沿字线方向而相邻的源极/漏极区之间，则各具一沟道区。
该沟道区能够通过一栅电极而被驱动，该栅电极连接至一字线并与该沟道区之间通过一栅介电质而呈电性绝缘。在该鳍片的顶侧具有一储存层，特别是一导电性浮动栅电极、或是一氧化物-氮化物-氧化物结构层(捕捉层)，其用于通过将热电子射入沟道中而对该存储单元进行编程，以及用于通过将热电洞射入沟道中而对该存储单元进行拭除，其位于该栅电极与该半导体材料鳍片之间。
在半导体存储器的情形中，具有捕捉层或是浮动栅电极作为储存媒体的多重鳍式场效应晶体管(FinFET)存在于一由半导体材料所制成的鳍片的顶侧，该栅电极的材料若适合用来控制栅电极，则同样存在于该鳍片的两侧壁，以形成侧壁晶体管；而在栅电极之间则形成了属于所对应鳍片的字线的部分。
此外，该两侧壁晶体管与在储存媒体(顶部晶体管)下方的沟道最好是用来读取个别的存储单元，侧壁晶体管与顶部晶体管的电荷电压以该储存媒体之一电位能函数而偏移，因此能够使用一高读取电流与低电压，利用该侧壁鳍式场效应晶体管来读取存储器的内容，而不像传统的浮动栅极晶体管；电荷载子能够储存于在源极侧与漏极侧的储存媒体，使得每一存储晶体管能够储存两位，这使其储存密度可以达到每一位为2F2；举例而言，这样的编程可以通过捕捉沟道热电子(CHEs)而产生，该存储器能够被配置为一次编程存储器或是可再编程存储器。
关于该半导体存储器与一相关的制作方法的实例参考第1图至第8图而更加详细说明如下，其中：
第1图说明了该半导体存储器的一平行于两平行位线间的一截面；
第2图说明了该半导体存储器的一平行于一字线的一截面；
第3图说明了该半导体存储器的一概略的平面图；
第4图与第5图说明了在该存储器制造方法中的中间产品剖面图，该剖面平行于两位线间的位线；以及
第6图至第8图说明了在该存储器造方法中沿一位线的中间产品。
第1图说明了该半导体存储器的一平行于两平行位线间、且与字线横切的一截面；该半导体存储器最好是制作于一SOI(Silicon OnInsulator)基板上；一厚的硅块层1与一薄的绝缘层2同时提供，欲作为组件的一主要硅薄层配置于其上。
在该半导体存储器中，此一主要硅层图形化以形成个别的鳍片3或网状结构；其中有复数鳍片3或网状结构彼此存在并彼此平行排列。
该鳍片或是网状结构以栅电极4而桥接，在该鳍片与该栅电极之间具有一薄的介电质以作为栅极介电质(栅极氧化物)，其未独立表示于该图式中。一储存层5位于该鳍片3的顶侧与该栅电极4之间；举例而言，此一储存层可为一捕捉沟道热电子(捕捉层)的膜层序列，一ONO层(氧化物-氮化物-氧化物层)特别适合于此一构想；此外，也可以使用一浮动栅电极作为储存媒体，此一电极通过绝缘材料而与该栅电极4所有通路以及该鳍片3的半导体材料电性绝缘；此一形式的储存媒体以及一编程与拭除操作本身，从其它半导体存储器而被了解。
在该个别的鳍片之间存在有一介电质6，举例而言，其可为一氮化物，或是在此例中为一氮化硅；该栅电极可为一金属或最好是多晶硅，其适于导电性掺杂，在其顶侧具有一电绝缘层7，例如可以使用TEOS(原硅酸四乙酯)；此一形式的膜层制造已被了解。
第2图说明了该半导体存储器的一平行于一字线的一截面；在此一截面中，该鳍片3与该图式的平面平行。掺杂区形成于该鳍片3中而作为源极/漏极区8，该位线9用以作为掺杂区，最好是以该半导体材料的一薄阻挡层10隔开；举例而言，该位线为钨。隔离组件11最好是由氮化物或二氧化硅所形成，其配置于该位线9的侧边已将该位线9与该栅电极4电性绝缘。
第3图以一概略的平面图来说明该字线WL1、WL2、...与该位线BL0、BL1、BL2...的排列方式；第3图亦指出在第1图与第2图中所表示的截面的位置。如覆盖的轮廓线所示，由半导体材料所制成的该鳍片3在图式中以虚线表示；以一规则间隔排列的该源极/漏极区8已清楚标示；该字线至该栅电极4形成于该位线之间，在位线区域中的字线结构将于下文中更详细加以描述；该字线在该鳍片3的侧壁处具有连续部分。
第4图通过一较佳制造方法的中间产品来说明根据第1图的一剖面图。由一SOI基板开始，该SOI基板含有一所使用的主要硅层，且具有一硅块层1与一绝缘层2、一氮化物层12与一沉积于此一基板顶侧的多晶硅层13；该膜层根据如第4图所示的截面并利用一光罩技术而被蚀刻，以产生鳍片3，其彼此呈平行的取向；并移除剩下的阻罩。该鳍片个别通过一层多晶硅而三边环绕，邻近字线的多晶硅层通过一间隔蚀刻而彼此分离；第4图中的该多晶硅层13于两位线之间，用以连接个别鳍片间彼此的位于侧面的该多晶硅层。
此外，电性绝缘或具有一电性绝缘部分的该储存层5可作用为一栅极介电质，为了将字线从彼此隔离，该栅电极于该鳍片3的末端处分离；在该鳍片间的间隔中，填充了一电性绝缘介电质6，最好是氮化硅。在去除了该鳍片3顶侧的介电质材料后，一电绝缘层7被形成，其最好通过TOES而形成。
第6图说明了该制造方法在沿一位线的截面的中间产品；在如第5图所示的电绝缘层7形成之后，该栅电极4的材料被回蚀于一与第6图所示的部分分开的区域中，此通过一合适的光罩技术而完成，其涵盖了在所欲位线之间的区域，因此只有所欲去除的相关膜层(TOES、多晶硅)部分会被适当地回蚀。
根据第7图，在该相关区域中，在形成字线的该栅电极4材料的残余部分上所形成的孔洞以电型绝缘材料14填充并加以磨平；在该栅电极的边缘处，在该源极/漏极区之间的该电性绝缘材料14通过一间隔蚀刻而回蚀，以形成该栅电极4的导电性材料的侧面覆盖；在此一方式中，可保护该侧的该储存层5并避免其与字线间的短路发生。
根据第8图中所说明的，在沿着所欲位线的区域进行源极与漏极注入(n+注入)之后，该位线所欲材料用于该半导体存储器的顶侧；首先，较佳的是，举例而言，同样提供一扩散阻挡10，使用于由钨所形成的位线9，以避免该金属向外扩散至该半导体存储器中；该位线图形化为彼此平行的细长段，表面则可通过CMP(化学机械  光)加以磨平。
该存储单元通过该鳍片侧壁的两晶体管以及位于该储存媒体下方的晶体管而加以读取，该栅电极4个别形成于位线间的该鳍片上，因而得以桥接该鳍片；该侧壁晶体管具有高激活电流(on current)，假设其具有相当于氧化物厚度的栅极介电质；由于侧栅极效应，该储存层通过部分偏移了门槛电压的方式而影响该鳍式场效应晶体管(FinFET)的激活电流。其优势包含了：
a)由于其简化的制程而具有低生产成本；
b)于低电压具有更高的读取电流；
c)与传统鳍式场效应晶体管(FinFET)间距有兼容性；以及
d)每一位可具有2F2的高储存密度。
因此，当该半导体存储器作为一OTP(一次编程)存储器之用时，可大幅节省了一次6V编程电压所需要的电荷泵送区域面积；在此一情形中，该侧壁晶体管作为读取晶体管，而该栅电极的部分与在鳍片顶侧的储存层特别用以提供储存操作，相较于传统的存储器，此方式可于较低电压处产生一个较高的读取电流，以及产生一较短的读取时间。
组件符号说明
1    硅块层
2    绝缘层
3    鳍片
4    栅电极
5    储存层
6    介电质
7    绝缘层
8    源极/漏极区
9    位线
10   阻挡层
11   隔离组件
12   氮化物层
13   多晶硅层
14   电绝缘材料
BL   位线
WL   字线

Claims (5)

1.一半导体存储器，具有位线与字线的一行列排列方式，其中
-一存储单元，排列于一位线与一字线的一交叉点；
-所述位线连接至一半导体材料中的导电性掺杂源极/漏极区(8)；
-在沿字线方向上彼此相距一距离的各两源极/漏极区(8)之间有一沟道区域，该沟道区域能够由一连接至一字线并与该沟道区域电性绝缘的一栅电极(4)而驱动；
-在栅电极(4)与半导体材料之间具有一存储层(5)，其用于该存储单元的编程，
其特征在于：
该源极/漏极区(8)是形成于该半导体材料的鳍片(3)中，所述鳍片彼此间以一距离平行排列，
各存储层(5)位于一鳍片(3)的顶侧，
该栅电极(4)排列于该鳍片(3)的顶侧与侧壁上，以及
该字线由施加于该鳍片(3)的所述侧壁的部分栅电极材料所形成，且栅电极(4)沿着该鳍片(3)方向而彼此电性连接。
2.如权利要求1的半导体存储器，其中该存储层(5)为一氧化物-氮化物-氧化物膜层序列。
3.如权利要求1的半导体存储器，其中该存储层(5)为一浮动栅电极，其由一绝缘材料而与该栅电极(4)周围的所有通路、该鳍片(3)的半导体材料电性绝缘。
4.如权利要求1至3中任一项的半导体存储器，其中所述鳍片(3)的形式为一SOI基板的硅层的细长状部分。
5.一种半导体存储器的制造方法，该半导体存储器具有一位线与字线的行列排列方式，其中
-一存储单元，排列于一位线与一字线的一交叉点；
-所述位线连接至一半导体材料中的导电性掺杂源极/漏极区(8)；
-在沿字线方向上彼此相距一距离的各两源极/漏板区(8)之间有一沟道区域，该沟道区域由连接至一字线并与该沟道区域电性绝缘的一栅电极(4)而加以驱动；
-在栅电极(4)与半导体材料之间具有一存储层(5)，其用于该存储单元的编程，
其特征在于：
在一第一步骤中，形成半导体材料鳍片(3)，其彼此间以一距离而平行排列，且施加一存储层(5)至一鳍片(3)的一顶侧；
在一第二步骤中，于所述鳍片的表面形成一薄介电层以作为栅介电质；以及
在一第三步骤中，所提供的一栅电极(4)材料用于该鳍片(3)的顶侧与侧壁；
在一第四步骤中，于所述鳍片(3)之间形成一介电质(6)；
在一第五步骤中，利用一掩膜技术，在所述栅电极之间的区域对所述栅电极材料回蚀以形成字线，且将掺杂注入引进至所述鳍片，以形成源极/漏板区(8)；
在一第六步骤中，与所述鳍片横向交错的位线(9)是由导电材料形成，所述位线将该源极/漏极区导电连接至另一个与该字线横向交错的源极/漏极区。
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