CN101167169A - 以高效率转移应力之形成接触绝缘层之技术 - Google Patents
以高效率转移应力之形成接触绝缘层之技术 Download PDFInfo
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Abstract
通过在形成金属硅化物之前移除用于形成高度复杂的横向掺质分布的外间隔体109,得到与习知工艺兼容的高度工艺兼容性,同时可使接触衬垫层(contact liner layer)115的位置更加接近沟道区,从而使得有高效率的应力转移机构可用来在沟道区中产生对应的应变(strain)。
Description
【发明所属之技术领域】
一般而言,本发明是有关于集成电路的形成,且更具体而言,有关于在制造场效应晶体管的期间在有间隔体元件(spacer element)的情形下形成接触绝缘层。
【先前技术】
集成电路的制造需要根据指定的电路布局在给定的芯片区上形成大量的电路元件。一般而言,目前实行多种工艺技术,其中,就复杂的电路而言,例如微处理器、储存芯片、及其类似者,由于在操作速度及/或耗电量方面有优异的特性,CMOS技术是目前最有效的方法。使用CMOS技术制造复杂的集成电路时,形成数百万个互补晶体管(亦即,N型沟道晶体管与P型沟道晶体管)于包含结晶半导体层(crystallinesemiconductor layer)的衬底上。不论所考虑的是N型沟道晶体管或是P型沟道晶体管,MOS晶体管都包含所谓的PN结(junction),该PN结系藉由经高度掺杂之漏极区与源极区的界面以及配置于漏极区与源极区之间的反向掺杂沟道区(inversely doped channel region)所形成。
藉由形成于沟道区上且藉由薄的绝缘层使其与该沟道区分开的栅极而控制该沟道区的导电系数(conductivity),亦即,导电沟道的驱动电流能力。在施加适当的控制电压于栅极而形成导电沟道后,沟道区的导电系数取决于掺质浓度、多数电荷载子(majority chargecarrier)的移动率(mobility)、以及(就该沟道区在晶体管宽度方向中的延伸为给定的情形而言)源极区与漏极区之间的距离(也被称作沟道长度)。在此,在施加控制电压于栅极后,结合在绝缘层下快速产生导电沟道的能力,沟道区的导电系数实质地决定MOS晶体管的效能。因此,缩短沟道长度以及减少与其相关联的沟道电阻率(resistivity),使得沟道长度成为增加集成电路之操作速度的主要设计准则。
不过,缩减晶体管的尺寸产生多个与此相关联的问题而必须予以处理以免不当地抵消掉稳定减少MOS晶体管之沟道长度所获得的有利条件。在此方面的一主要问题为发展出增强的光微影及蚀刻策略以便可靠及可再生产地制造具有关键尺寸的电路元件(例如晶体管的栅极)供新一代的装置使用。此外,在漏极区与源极区的垂直方向以及横向(lateral direction)中,需要高度复杂的掺质分布(dopant profile)以提供与所欲之沟道的可控制性相结合的低片电阻率(sheetresistivity)与低接触电阻率。此外,以泄露电流的控制而言,PN结相对于栅极绝缘层的垂直位置也是关键性的设计准则。在此,缩减沟道长度也需要减少漏极区和源极区相对于栅极绝缘层及沟道区所形成之界面的深度,从而需要复杂的注入技术。根据其它的方法,以对该栅极有指定偏移(offset)的方式形成外延成长区(其系称作加高的漏极区与源极区)以增加该加高之漏极区与源极区的导电系数,同时维持对栅极绝缘层有浅的PN结。
不拘所使用的技术方法,复杂的间隔体技术都需要产生高度复杂的掺质分布且在栅极与漏极区及源极区中以自对齐(self-aligned)的方式形成金属硅化物区时作为掩模。由于连续减少关键尺寸的大小(亦即,晶体管的栅极长度),必需调整与上述工艺步骤有关的工艺技术甚至可能发展新的工艺技术,已提出藉由增加给定沟道长度之沟道区内的电荷载子移动率来增强晶体管元件的装置效能。原则上,可使用至少两个机构,以组合或分开的方式,增加沟道区内的电荷载子移动率。首先,可减少沟道区内的掺质浓度,从而降低电荷载子的散射情况而使导电系数增加。不过,降低沟道区内的掺质浓度明显影响晶体管装置的阈值电压,从而使得降低掺质浓度变成较不具吸引力的方法,除非发展出可调整所欲之阈值电压的其它机构。
第二,可修改沟道区内的晶格结构(lattice structure),例如藉由产生拉伸应变(tensile strain)或压缩应变(compressivestrain),这会导致电子及空穴的移动率改变。例如,在沟道区中产生拉伸应变增加电子的移动率,其中,取决于拉伸应变的大小,可得到移动率的增量达百分之20,接着,直接转变为导电系数的对应增量。另一方面,沟道区内的压缩应力(compressive stress)可增加空穴的移动率,从而提供用来增强P型晶体管之效能的可能性。
结果,已提出在沟道区中或下方导入,例如,硅/锗层或硅/碳层以产生拉伸应力或压缩应力。虽然藉由在沟道区中或下方导入应力产生层可显著增强晶体管效能,不过须大费工夫才能实现形成对应的应力层(stress layer)于习知且经充分证实的CMOS技术。例如,必须开发额外的外延成长技术且具体实施于工艺流程内以便在沟道区中或下方的适当位置形成含锗或碳的应力层。因此,显著增加工艺复杂度,从而也增加生产成本以及生产良率降低的可能性。
另一种有效的方法是在绝缘层内产生应力,该绝缘层系形成于晶体管元件形成后以埋设该等晶体管且容纳金属接触栓(contact)以提供电气连接至晶体管的漏极/源极区和栅极。该绝缘层通常包含至少一蚀刻终止层或衬垫(etch stop layer or liner)与另一相对于该蚀刻终止层或衬垫可选择性地加以蚀刻的介电层。在以下的说明中,此绝缘层会被称作接触层且对应的蚀刻终止层将以接触衬垫层(contactliner layer)表示。为了得到用于在晶体管之沟道区中产生应变的有效率之应力转移机构(stress transfer mechanism),必须将在沟道区附近的接触衬垫层放置在靠近沟道区。不过,在需要三重间隔体方法(triple spacer approach)以实现高度复杂之横向掺质分布的先进晶体管架构中,是用间隔体“吸收”接触衬垫层中大量的应力,从而使得习知的三重间隔体方法目前用来在先进晶体管的沟道区中产生应变较不具吸引力,尽管相较于外延成长应力层具有工艺复杂度上的优点。
鉴于上述情况,亟须一种能在沟道区中产生应力的改良技术而不需要既复杂又昂贵的外延成长技术。
【发明内容】
以下提出本发明的精简概要以供基本了解本发明的一些方面。此概要不是本发明的详尽概观,不是旨在识别本发明的关键性或重要元件或描述本发明的范畴。其唯一的目的是要以简化的形式提出一些概念作为以下所述较详细的说明的前言。
一般而言,本发明是针对一种使得形成接近各个晶体管元件的沟道区的接触衬垫层(亦即,用来埋设晶体管元件以形成电气接触贯穿其中的介电层堆栈的蚀刻终止层)成为可能的技术。因此,可形成或处理该接触衬垫层以呈现指定的内应力(internal stress),然后以高效率将该内应力转移到沟道区以便在那产生对应的应变,从而提供改善电荷载子移动率(mobility)及因而提高晶体管元件的整体效能的可能性。
根据本发明的一示范具体实施例,提供一种方法,包含:形成包含栅极结构的晶体管元件,该栅极结构包含至少一内间隔体元件与外间隔体元件。此外,随后将该外间隔体元件移除以及在该晶体管元件上形成接触衬垫层。
根据本发明的另一示范具体实施例,提供一种方法,包含:形成具有第一栅极结构的第一晶体管元件,该第一栅极结构包含至少一内与外间隔体元件。此外,形成第二晶体管元件,其具有包含至少一内与外间隔体元件的第二栅极结构。该方法更包含:移除该第一与第二栅极结构的外间隔体元件。此外,在该第一晶体管元件上形成具有第一内应力的第一接触衬垫层以及在该第二晶体管元件上形成具有第二内应力的第二接触衬垫层。
尽管本发明容许不同的修改以及替代性的形式,在此仍以附图中的实施例图标特定的具体实施例且详述细节。不过,应了解,本文特定具体实施例的说明不是想要把本发明限定为本文所揭示的特定形式,反而是,本发明是要涵盖落入如附上权利要求书所界定的本发明精神及范畴内的所有修改、等价物、及替代物。
【实施方式】
以下描述本发明的示范具体实施例。为求清楚,本专利说明书中没有描述实际具体实作的所有特征。当然,应了解在开发任一此类的实际具体实施时,必须完成许多与具体实作有关的决策以达成开发人员的特定目标,例如遵循与系统有关以及与商业有关的限制,这些都会因具体实作不同而有所不同。此外,应了解致力于这种开发是即复杂又耗时的,决不是一般熟谙此艺者在得知本揭示内容即可进行的例行事务。
以下参考附图描述本发明。示意地图标于附图的各种结构、系统、及装置的目的只是用来做解释且藉此使得熟谙此艺者所习知的细节不会混淆本发明。然而,为了描述及解释本发明的示范实施例,仍内含附图于说明中。应了解及解释本文所使用之字词及用语的意思是与熟谙相关技艺者所了解的字词及用语一致。没有特别定义的术语及用语(亦即,不同于熟谙此艺者所了解的一般及惯用的定义)想要用来表示本文中之术语或用语的一致用法。若想要使术语或用语具有特定意思的情形,亦即,不同于熟谙此艺者所了解的意思,这种特殊定义会在专利说明书中以直接不仿真两可地提供该术语或用语之特殊定义的方式明白地提出。
一般而言,本发明系针对将应力有效率地由接触衬垫层转移到沟道区的问题,同时仍然与习知工艺保持高度的兼容性。为此目的,根据注入(implantation)及硅化物所要求的条件,将间隔体元件设置成具有一尺寸以便将注入物(implant)种类(例如,硼与磷)的大扩散率纳入考虑,不过,可显著减少始于漏极区与源极区的有效距离是在于在形成接触衬垫层之前将最外面的间隔体移除。因此,可将最外面间隔体元件的移除工艺设计成藉此不会不当地影响任何要形成于栅极与漏极区及源极区上的硅化物区(silicide region)。参考附图,以下更详细地描述本发明的进一步示范具体实施例。
图1a至1e系示意地图标半导体装置100的截面图。该半导体装置100包含衬底101,其系表示任何适合用来形成集成电路之电路元件的衬底。例如,该衬底101可为块体(bulk)硅衬底、绝缘层上覆硅(SOI)衬底、或任何其它有结晶半导体层(其系适合形成有晶体管元件于其中)形成于其上的适当衬底。在中间的制造阶段中形成于该衬底101中及上的是晶体管元件150,其中该晶体管元件150包含形成于栅极绝缘层103上的栅极102,该栅极绝缘层103使该栅极102与沟道区104分开,该沟道区104可代表该衬底101之一部分或任何形成于该衬底101上的适当半导体层之一部分。就像在高度复杂以硅为基底的集成电路(例如,CPU、内存芯片、ASIC(特定应用集成电路)及其类似者)中会遭遇的,该晶体管元件150可代表任何类型的场效应晶体管,例如有100nm及显著更短之栅极长度(亦即,图1a中之栅极102的水平尺寸)的N型沟道晶体管或P型沟道晶体管。结果,该栅极绝缘层103可具有范围约从1.2nm或更小到数nm的适当厚度,这取决于栅极102的整体尺寸。应了解,本发明极有利于结合具有栅极长度约为100nm甚或约50nm及更短的比例极精密之晶体管元件,然而,原则上,本发明也容易应用于较不复杂的晶体管元件。
该半导体装置100更包含形成于栅极102之侧壁上的偏移间隔体(offset spacer)105。该偏移间隔体105可由任何适当的介电材料构成,例如二氧化硅、氮化硅、氮氧化硅、及其类似者。根据用于形成在衬底101内所形成的与沟道区104的延伸区106相邻的横向掺质分布的工艺条件,选定该偏移间隔体105的宽度。该半导体装置100可进一步包含:形成为与该栅极102之侧壁相邻的内间隔体元件107,其中该内间隔体元件107可藉由衬垫108而与该偏移间隔体105分开,该衬垫108系由相对于内间隔体107之材料有中高蚀刻选择性(etchselectivity)的介电材料构成。在一示范具体实施例中,该内间隔体107可由氮化硅构成,而衬垫108(也形成于衬底101的水平部分以及栅极102之顶部上)可由二氧化硅构成。对于这样的材料成分,已知有多种具有公认有效之高蚀刻选择性的各向异性蚀刻配方。在其它具体实施例中,该内间隔体107可由二氧化硅或氮氧化硅构成,而该衬垫108可由氮化硅构成藉此对于公认有效之各向异性蚀刻配方也能呈现中高蚀刻选择性。装置100可进一步包含外间隔体元件109,其宽度系经选定以符合用于待随后进行以形成与延伸区106之深漏极区与源极区相邻的离子注入工艺(ion implantation process)的工艺条件。藉由蚀刻终止层110使该外间隔体元件109与该内间隔体107分开,该蚀刻终止层110也覆盖衬垫108的水平部分且由对于外间隔体109之材料呈现中高蚀刻选择性的材料构成。在一示范具体实施例中,该外间隔体109可由二氧化硅构成,而该蚀刻终止层110可由氮化硅构成。在其它具体实施例中,对于外间隔体109与蚀刻终止层110可提供不同的材料成分,只要保持这两种材料之间有必要的蚀刻选择性。例如,在一具体实施例中,该外间隔体109可由氮化硅构成,而该蚀刻终止层110可由二氧化硅构成。
如图1a所示,用于形成该半导体装置100的典型工艺流程可包含以下的工艺。在形成适当的栅极绝缘材料层与栅极材料(例如,以二氧化硅、富氮之二氧化硅的形式用于栅极绝缘层104以及以预掺杂或未掺杂之多晶硅(polysilicon)的形式用于栅极102)之后,可基于先进的光微影及蚀刻技术进行公认有效之图案化工艺。在图案化该栅极绝缘层104与该栅极102之后,可藉由沉积适当的介电材料(例如,二氧化硅、氮化硅、及其类似者)而形成该偏移间隔体105,其有预定之厚度实质地对应于该偏移间隔体105的宽度。之后,可进行适当的各向异性蚀刻工艺以移除装置100之水平部分上的多余材料,例如在栅极102的上表面与在衬底101的暴露部分上。随后,可进行离子注入程序以形成该等延伸区106之一部分,其中可进行其它的注入循环以于衬底101及/或晕圈区(halo region,未图标)内形成预先非晶化区(pre-amorphized region,未图标)以便得到用于形成该等延伸区106和深漏极区与源极区的所需要的注入条件及掺质分布,随后对此将予以说明。之后,可藉由沉积适当的材料形成该衬垫108,在一具体实施例中,该适当的材料可为可根据公认有效之电浆增强化学气相沉积(PECVD)技术而沉积的二氧化硅。在其它具体实施例中,可以氮化硅的形式沉积该衬垫108。随后,用PECVD技术可沉积用于内间隔体107的间隔体材料,其中选定该衬垫108的材料成分以相对于内间隔体107呈现高蚀刻选择性。在一示范具体实施例中,当衬垫108实质由二氧化硅构成时,该内间隔体材料107可由氮化硅构成。在其它的具体实施例中,该内间隔体材料107可由二氧化硅或氮氧化硅构成,而该衬垫108可由氮化硅形成。
之后,公认有效之各向异性蚀刻配方可用来移除间隔体材料的多余材料,从而形成该内间隔体107,而该各向异性蚀刻工艺可靠地停止于该衬垫108之上与之中。之后,根据装置需求,可进行另一适当的注入工艺以微调该等延伸区106的横向掺质分布。接下来,例如,在一具体实施例中以氮化硅层的形式,可共形沉积(conformallydeposit)该蚀刻终止层110,之后在此具体实施例中可沉积及各向异性蚀刻由二氧化硅构成的间隔体材料以形成该外间隔体元件109。在本技艺中对应的各向异性蚀刻配方都是公认有效的。在其它的示范具体实施例中,可将该蚀刻终止层110沉积为二氧化硅层,而由氮化硅层形成该外间隔体109。
图1b系示意地图标处于另一先进制造阶段的半导体装置100。如图所示,移除一部分的蚀刻终止层110(其系形成于栅极102上以及衬底101的暴露之水平部分上(图1a))。此时用110a表示剩余的蚀刻终止层110。此外,在该等延伸区106旁边形成深源极区与漏极区111。
可藉由蚀刻步骤形成图标于图1b的装置100,在特定具体实施例中可将该蚀刻步骤设计成为实质为各向异性的蚀刻工艺用来选择性移除蚀刻终止层110的暴露部分。因此,可使用公认有效的选择性蚀刻配方,其中当蚀刻终止层110与衬垫108由呈现某一程度之蚀刻选择性的不同材料形成时,该蚀刻工艺能可靠地停止于该衬垫108之中及之上。由于此一蚀刻工艺是用来移除蚀刻终止层110的暴露之水平部分,蚀刻终止层110a的侧面延伸(lateral extension)(以110b表示)得以界定而实质与外间隔体元件109的宽度相对应。此外,在后续用于形成深漏极区与源极区111以及也用于进一步掺杂该栅极102的注入期间,对应的层堆栈(包括图1a中之层110与108)减少,从而利于控制用来形成源极/漏极区111的离子注入程序。在注入后,可进行快速热退火工艺(rapid thermal anneal process)以活化在该等延伸区106与该深漏极/源极区111之内的掺质而且也使先前预先非晶化(pre-amorphization)以及其它注入工艺所造成之结晶损坏(crystalline damage)再结晶。
图1c系示意地图标根据替代具体实施例之用于形成深源极/漏极区111以及用于测定蚀刻终止层110a之侧面延伸110b的半导体装置200。在图1c中,将用于形成蚀刻终止层110a的蚀刻工艺组构成藉此也移除衬垫108的暴露之水平部分,从而形成残留物108a。因此,将对应的蚀刻程序设计成可靠地停止于衬底101的半导体材料上,在本发明的特定具体实施例中,该衬底101实质由硅构成。结果,在后续用于形成深漏极/源极区111的注入工艺期间暴露栅极102以及衬底101的对应区。之后,可进行快速热退火工艺,随后对此也会参考图1b加以说明。
在高度先进晶体管元件中,通常高度掺杂区(例如,栅极102)以及深漏极/源极区111之接触区的导电系数系藉由在该等区域的上部分上提供金属化合物而增加,因为相较于更加高度掺杂的硅材料,金属-硅化合物可能有较高的导电系数。例如,通常提供钛、钴、以及在高度先进的装置中为镍,以形成具有降低之电阻率的对应金属硅化物区。在沉积任何适当的金属例如镍及其类似者之前,例如当由如图1b所示之半导体装置100开始时,必须暴露对应的表面部分,及/或当在考虑中的表面部分已实质暴露时,通常可移除表面污染,如图1c所示。在衬垫108实质由二氧化硅构成的具体实施例中,可根据高选择性蚀刻化学进行用来暴露相关表面部分及/或用来移除污染物(特别是,氧化物残留物)的对应蚀刻工艺,这不会实质影响栅极102和衬底101以及蚀刻终止层110a。例如,可使用经稀释的氢氟酸(fluoric acid,HF)对硅与氮化硅选择性地移除氧化物及氧化物残留物。
图1d系示意地图标在可选择性移除表面污染及/或暴露各个表面部分的对应蚀刻工艺之后的半导体装置100。此外,在一特定具体实施例中,此高度选择性蚀刻工艺也用来实质完全移除外间隔体元件109。如图所示,该半导体装置100包含衬垫108a,此时该衬垫108a藉由对应的选择性蚀刻工艺而进一步减少,从而产生衬垫108b。此外,由于该蚀刻工艺之等向特性,在某些情况中,可能形成由蚀刻终止层110a垂直勾画出轮廓的受蚀刻面积(under-etch area)。同样地,在长时间持续的蚀刻工艺期间可能暴露栅极102的上侧壁部分102a,其中如果偏移间隔体105是由与衬垫108b实质相同的材料构成也可能使其减少。此时对应地减少之偏移间隔体以105a表示。在其它的具体实施例中,该衬垫108与该外间隔体109可由二氧化硅以外的介电材料构成,例如氮化硅,同时该蚀刻终止层110a可由二氧化硅构成。就此情形而言,可使用实质相同的工艺流程以及适当的蚀刻化学(例如热磷酸)以移除外间隔体109以及暴露相关的表面部分。
之后,根据公认有效的配方,藉由溅镀(sputter deposition)可沉积适当的金属。例如,基于装置需求,可沉积钴、钛、镍、或其它耐火金属。在该金属的溅镀沉积(其系有中度方向性的沉积技术)期间,一部分的蚀刻终止层110a也实质防止金属沉积。结果,除了暴露的上侧壁部分102a以外,由外间隔体元件109之尺寸实质决定的区域尽管被横向尺寸110b移除,仍实质局部地限制金属沉积。在后续用于开始沉积之金属与硅之间的化学反应的热处理期间,在暴露的硅部分(例如栅极102的上表面与上侧壁部分102a以及衬底101的暴露表面部分)上形成金属硅化物较佳。
金属硅化物在漏极/源极区111中的形成实质取决于蚀刻终止层110a的侧面延伸110b,如果外间隔体109仍在适当的位置这是成立的,即使已产生受蚀刻区(under-etch region),在此情形下也可大幅阻碍金属渗透(metal penetration)而且也可显著减少朝向沟道区104的金属扩散。结果,金属硅化物的形成被限制于漏极/源极区111初始由外间隔体109界定的一部分(图1b与1c),同时可使待形成于金属硅化物形成之后的接触衬垫层的材料更加靠近沟道区104,从而显著增强用于在沟道区104中产生所欲之应变的应力转移机构。
图1e系示意地图标完成上述工艺序列之后的半导体装置100。因此,该装置100包含在该等漏极/源极区111内的金属硅化物区113,彼等之位置及尺寸实质由外间隔体109界定,亦即,由蚀刻终止层110a及其侧面延伸110b界定。此外,在栅极102的上部分(upper portion)上形成对应的金属硅化物区114,其中减少之偏移间隔体105a(图1d)提供增加的表面积(亦即,上侧壁部分102a),其能用来将硅转换为金属硅化物,从而使得较大部分的栅极102被转换为高度导电的材料。此外,该装置100包含形成于晶体管元件150上的接触衬垫层115,该接触衬垫层115可由例如氮化硅构成且有指定的内应力。如众所周知者,在沉积氮化硅的PECVD工艺期间,可选定沉积参数,例如压力、温度、偏压、及其类似者,以便得到范围从约1GPa(十亿巴斯卡)的拉伸应力至约1GPa的压缩应力的指定内应力。结果,可选定对应的内应力以便在沟道区104中有效率地产生对应的应变,最终可增强晶体管的操作。此外,由于可选定PECVD工艺的工艺参数以得到高度无方向性的沉积行为(behavior),也可填满(至少是一部分)任何已形成的受蚀刻区,以实质避免在包围着晶体管元件150的介电材料内有任何空洞(void)。
结果,藉由移除外间隔体109(这可在预清洗工艺期间完成,如通常在形成金属硅化物之前所要求者),可使接触衬垫层115的相关部分更加靠近沟道区104,从而显著提高应力的移转而使电荷载子移动率增加。同时,与习知工艺技术保持高度的兼容性而对延伸区106与漏极/源极区111的高度复杂横向掺质分布的形成没有负面影响。此外,增加栅极102在移除外间隔体109期间暴露的表面积,亦即,上侧壁部分102a,提高了电极导电系数,这对晶体管150效能的增加也有贡献。
图2系示意地图标根据本发明之另一示范具体实施例之半导体装置200的截面图。该半导体装置200可包含形成于衬底201上的第一晶体管元件250与第二晶体管元件260。关于该衬底201的架构,所用的准则可与之前解释衬底101时所用的相同。此外,该第一与该第二晶体管元件250、260包含的元件实质与在说明之前图1e时所描述者相同。亦即,第一与第二晶体管元件250、260可包含含有栅极202的栅极结构,该栅极202上形成有藉由衬垫208b而与内间隔体207分开的偏移间隔体205a。在该内间隔体207上可形成有对应的蚀刻终止层210a。就一致性而言,将第一与第二晶体管元件250、260的间隔体207称作“内”间隔体元件,虽然在此制造阶段将不再提供“外”间隔体元件。此外,第一与第二晶体管元件250、260可包含藉由栅极绝缘层203而与栅极202分开的沟道区204。可提供延伸区206和深源极/漏极区211,其中系形成各自的金属硅化物区(例如镍硅化物区213)于该深漏极/源极区211内。在该栅极202的上部分可形成对应的金属硅化物区214。在用于形成对应延伸区206、源极/漏极区211、以及沟道区204的掺质类型上,第一与第二晶体管元件250、260彼此可不相同,使得例如第一晶体管250可为N型沟道晶体管,而第二晶体管260可为P型沟道晶体管。在其它具体实施例中,额外地或替换地,在其它的晶体管特性(例如栅极长度、该等栅极绝缘层203的厚度、及其类似者)上,第一与第二晶体管250、260可不相同。此外,在第一与第二晶体管元件250、260上形成接触衬垫层215。最后,可用光刻胶掩模216覆盖该第一晶体管元件250。
如图2所示,用来形成半导体装置200的典型工艺流程所包含的工艺实质与先前参考半导体装置100时所描述者相同,其中在形成延伸区206与源极/漏极区211期间,以及在任何之前所进行之以在各个沟道区204中产生适当垂直掺质分布的注入程序中,可进行适当的掩模步骤(masking step)以便将不同类型的掺质导入第一与第二晶体管元件250、260。在形成装置200期间,在用来形成源极/漏极区的对应注入之前可提供外间隔体元件,在形成金属硅化物区214、213之后及之前可移除该等外间隔体元件,如同之前在说明图1d与1e时所描述者。此外,可根据适当的沉积技术而形成接触衬垫层215以具有指定的内应力,其可适当地予以选定以便增加第一晶体管元件250的效能。例如,当此晶体管元件为N型沟道晶体管时,接触衬垫层215的内应力可为具有适当大小的拉伸应力以提供拉伸应变于第一晶体管元件250的沟道区204,因为拉伸应变可增加电子移动率。在形成接触衬垫层215后,基于可用来形成不同类型之延伸区206和源极/漏极区211的任何光微影掩模也可形成该光刻胶掩模216。之后,该装置200可经受处理(treatment)217,该处理217系经设计成在第二晶体管元件260上形成接触衬垫层部分215a,其所呈现的内应力会与形成于第一晶体管元件250上的接触衬垫层215的不同。
在一示范具体实施例中,该处理217可包含用任何适当的离子种类,例如氙、氩、及其类似者,之离子注入工艺,其可改变所沉积之接触衬垫层215的内部结构,从而产生某一程度的应力松弛(relaxation)。例如,拉伸应力对P型沟道晶体管之沟道区中的空穴移动率有负面影响,因此藉由施加用于应力松弛的处理217,使层215的初始产生应力实质不会影响第二晶体管元件260的沟道区204。在其它具体实施例中,可以固有的(inherent)压缩应力形成层215,例如当第一晶体管元件250为P型沟道晶体管时,且随后用处理217松弛压缩应力藉此消除或至少降低压缩应力对第二晶体管元件260(可能为N型沟道晶体管)之沟道区204的影响。因此,由于带有应力之层215紧邻于各自的沟道区204,故可最有效地提高P型沟道晶体管250的效能,然而可根据装置需求调整压缩应力对N型沟道晶体管260的影响。特别是,藉由适当地控制处理217可控制应力松弛以便在晶体管250与260的操作期间实现增强的对称程度。
在其它的示范具体实施例中,处理217可包含:以任何适当的蚀刻工艺移除部分215a,之后,用另一具有所欲之内应力的接触衬垫层取代部分215a以大幅改善第二晶体管元件260的效能。因此,也可将该另一接触衬垫层沉积于第一晶体管元件250上,从而有可能减弱初始所沉积之接触衬垫层215的影响,然而,这在调整初始所沉积之接触衬垫层215的固有应力(inherent stress)大小的时候才纳入考虑。
结果,本发明提供一种用于把应力由接触衬垫层移转到晶体管元件中之沟道区的改良技术,其中系藉由移除用来产生适当横向掺质分布的外间隔体元件而实现紧邻于沟道区的接触衬垫层。此外,在形成金属硅化物区之前可进行该移除工艺,从而可得到与习知工艺流程兼容的高度兼容性,同时在金属沉积之前进行的预清洗工艺能有利地也用来移除该外间隔体。此外,外间隔体的移除工艺可能也暴露栅极的增加部分,从而额外提高该栅极中的金属硅化物形成,这可使彼之导电系数增加。外间隔体的移除结合金属硅化物预清洗工艺的进行是在前段工艺(front end of line;FEoL)中,因而可防止任何金属交叉污染。
以上所揭示的特定具体实施例系只供图解说明,显然对熟谙此艺者而言,在获得本文的教导内容后,可以不同但等效的方式修改和实施本发明。例如,可以不同的顺序进行以上所提出的工艺步骤。此外,除了以下权利要求书中所描述的内容以外,不希望本发明受限于本文所描述的构造或设计中的细节。因此,显然可改变及修改以上所揭示的特定具体实施例,而且所有此类的变化体都视为仍在本发明的范畴及精神内。因此,在此声请保护以下所提出的权利要求书。
【图式简单说明】
参考以下结合附图的说明可了解本发明,其中类似的元件用类似的元件符号表示,其中:
图1a至1e为晶体管元件的截面图,其系根据进一步示范具体实施例示意地图标形成接近沟道区之接触衬垫层的各种工艺阶段;以及
图2为包含两个晶体管元件的半导体装置的截面图,其系根据本发明之更进一步示范具体实施例示意地图标该两个晶体管元件系容纳接近各自之沟道区的接触衬垫层且该接触衬垫层的各个部分有不同的内应力。
【主要元件符号说明】
100 半导体装置、装置
101 衬底
102 栅极
102a 上侧壁部分
103 栅极绝缘层
104 沟道区
105 偏移间隔体
105a 减少的偏移间隔体
106 延伸区
107 内间隔体元件
108 衬垫
108a 残留物
108b 衬垫
109 外间隔体元件
110 蚀刻终止层
110a 剩余的蚀刻终止层、蚀刻终止层
110b 侧面延伸
111 深源极区与漏极区、深漏极/源极区
113 金属硅化物区
114 金属硅化物区
115 接触衬垫层
150 晶体管元件
200 导体装置
201 衬底
202 栅极
203 栅极绝缘层
204 沟道区
205a 偏移间隔体
206 延伸区
207 内间隔体、间隔体
210a 蚀刻终止层
211 源极/漏极区
214 金属硅化物区
215 接触衬垫层、层
215a 接触衬垫层部分、部分
216 光刻胶掩模
217 处理
250 第一晶体管元件、晶体管
260 第二晶体管元件、晶体管
Claims (11)
1.一种方法,包含下列步骤:
形成包含栅极结构102的晶体管元件150,该栅极结构包含至少一个内间隔体元件107与一个外间隔体元件109;
移除该外间隔体元件109;以及
在该晶体管元件150上形成接触衬垫层115。
2.如权利要求1所述的方法,其中形成该晶体管元件的步骤包含:
在半导体区上形成栅极102;形成至少一个与该栅极102的侧壁相邻的该内间隔体元件107
形成蚀刻终止层110以分隔该至少一个内间隔体元件107与该外间隔体元件109;以及
使用该内间隔体元件与外间隔体元件作为注入掩模形成漏极/源极区111。
3.如权利要求1所述的方法,其中形成该接触衬垫层115的步骤包含:沉积介电材料并使用沉积参数在该接触衬垫层中实现预定的内应力。
4.如权利要求2所述的方法,还包含:在形成该接触衬垫层115之前在该栅极102及该漏极/源极区111上形成硅化物区,其中在形成该硅化物区之前移除该外间隔体元件109。
5.如权利要求4所述的方法,其中形成该外间隔体元件109的步骤包含:沉积该蚀刻终止层110、沉积间隔体材料层、各向异性蚀刻该间隔体材料层以形成该外间隔体元件109、以及使用该外间隔体元件109作为蚀刻掩模蚀刻该蚀刻终止层110。
6.如权利要求1所述的方法,还包含:在形成该内间隔体元件与外间隔体元件107,109之前形成与该栅极102的该侧壁相邻的偏移间隔体元件105。
7.如权利要求6所述的方法,还包含:在形成该内间隔体元件107之前形成衬垫108,该衬垫108在形成该内间隔体元件107的过程中充当蚀刻终止层。
8.一种方法,包含下列步骤:
形成具有第一栅极202结构的第一晶体管元件250,该第一栅极结构包含至少一个内间隔体元件207与外间隔体元件209;
形成具有第二栅极202结构的第二晶体管元件,该第二栅极结构包含至少一个内间隔体元件207与外间隔体元件209;
移除该第一与第二栅极结构的该外间隔体元件209;以及
在该第一晶体管元件250上形成具有第一内应力的第一接触
衬垫层215,以及在该第二晶体管元件260上形成具有第二内应力的第二接触衬垫层215A。
9.如权利要求8所述的方法,其中该第一与第二内应力不相同。
10.如权利要求8所述的方法,其中形成该第一与第二接触衬垫层的
步骤包含:在该第一与第二晶体管元件上沉积具有该第一内应力的接触衬垫层、以及选择性松弛形成于该第二晶体管元件上的该接触衬垫层以得到该第二内应力。
11.如权利要求8所述的方法,其中形成该第一与第二接触衬垫层的
步骤包含:在该第一与第二晶体管元件上沉积具有该第一内应力的接触衬垫层、选择性移除在该第二晶体管元件上的该接触衬垫层的一部分、以及在该第一与该第二晶体管元件上沉积另一具有该第二内应力的接触衬垫层。
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CN109830433A (zh) * | 2017-11-23 | 2019-05-31 | 联华电子股份有限公司 | 制作半导体元件的方法 |
CN109830433B (zh) * | 2017-11-23 | 2021-03-30 | 联华电子股份有限公司 | 制作半导体元件的方法 |
CN110010608A (zh) * | 2017-11-30 | 2019-07-12 | 台湾积体电路制造股份有限公司 | 存储器件及其形成方法 |
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US7354838B2 (en) | 2008-04-08 |
JP5204645B2 (ja) | 2013-06-05 |
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CN101167169B (zh) | 2011-11-23 |
TWI443750B (zh) | 2014-07-01 |
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