CN101138081A - 集成电路及其制造方法 - Google Patents

集成电路及其制造方法 Download PDF

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CN101138081A
CN101138081A CNA2006800073364A CN200680007336A CN101138081A CN 101138081 A CN101138081 A CN 101138081A CN A2006800073364 A CNA2006800073364 A CN A2006800073364A CN 200680007336 A CN200680007336 A CN 200680007336A CN 101138081 A CN101138081 A CN 101138081A
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A·M·韦特
S·卢宁
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GlobalFoundries Inc
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Abstract

提供一种集成电路及其制造方法。该集成电路(20)包括主体硅衬底(bulk silicon substrate)(24)，其具有〈100〉晶向的第一区域(64，66)及〈110〉晶向(crystalline orientation)的第二区域(66，64)。绝缘层上硅(silicon on insulator，SOI)层(62)叠放设置于一部分的主体硅衬底上。至少一场效应晶体管(96，98)形成在该绝缘层上硅层(62)中，至少一P沟道场效应晶体管(90，92)形成在该〈110〉晶向的第二区域(66，64)中，且至少一N沟道场效应晶体管(90，92)形成在该〈100〉晶向的第一区域(64，66)中。

Description

集成电路及其制造方法
技术领域
本发明通常是关于FETIC及其制造方法，且尤其是关于具有SOI装置的FETIC及PFET和NFET混合定向(Hybrid Orientation，HOT)装置及其制造方法。
背景技术
现今集成电路(IC)主要经由使用多个互相连结的场效应晶体管(FET)，亦称为金属氧化物半导体场效应晶体管(MOSFET或MOS晶体管)，而施行。IC通常使用P沟道和N沟道FET而形成，且IC于是称为互补MOS或CMOS电路。经由叠放设置在绝缘层上的硅薄层形成FET，可达成FETIC的某些效能改良。例如，该等绝缘层上硅(SOI)FET展现低接面电容(junction capacitance)且因此可以高速操作。其中制造有FET的硅衬底，不论是主体硅衬底或SOI，通常为<100>晶向。选择此晶向是因为<100>晶向达到最高的电子移动率且因此达到最高速的N沟道FET。在CMOS电路中可达到的额外效能增进为藉由增进P沟道FET的空穴移动率。空穴移动率可藉由在具有<110>晶向的硅上制造P沟道FET而增进。混合定向技术(HOT)系对N沟道FET使用<100>晶向且对P沟道FET使用<110>晶向。
因此，期望在单一集成电路中结合所要之绝缘层上硅FET特性与所要之可由混合定向技术获得的特性。此外，期望提供制造CMOS集成电路的方法，该CMOS集成电路结合在相同衬底上之SOIFET与主体HOT N沟道及P沟道FET。再者，其它本发明所期望之特性从后续详细说明结合所附图式及前述技术领域及先前技术之描述而变为明显。
发明内容
提供一种CMOS集成电路，利用主体混合定向(HOT)晶体管与绝缘层上硅晶体管结合而获得优势。该集成电路利用在<110>晶向的主体硅中增加空穴移动率且在<100>晶向的主体硅中增加电子移动率而获得优势。该集成电路包括主体硅衬底，其具有<100>晶向的第一区域及<110>晶向的第二区域。绝缘层上硅层叠放设置于一部份的该主体硅衬底上。至少一场效应晶体管形成在该绝缘层上硅层中，至少一P沟道场效应晶体管形成在该<110>晶向的第二区域中，且至少一N沟道场效应晶体管形成在该<100>晶向的第一区域中。
提供一种制造该CMOS集成电路的方法。该方法包括提供使具有第一晶向的硅衬底有第二晶向的叠放设置硅层的步骤。绝缘层上硅层是形成叠放设置于一部份的该硅层上。具有该第一晶向的第一外延层成长在该硅衬底的一部份上且具有该第二晶向的第二外延层成长在该硅层的一部份上。第一HOT场效应晶体管形成在该第一外延层中，第二HOT场效应晶体管形成在该第二外延层中，且第三场效应晶体管形成在该绝缘层上硅层中。
附图说明
本发明之后配合下述图式描述，其中类似组件符号标示类似构件，且其中：
图1至13以剖面图示意地描述集成电路之一实施例及其制造方法之步骤；以及
图14至18以剖面图示意地描述根据本发明之另一实施例之制造集成电路之方法步骤。
主要组件符号说明
20CMOS集成电路22硅层
24硅载体衬底
26绝缘层上硅层(SOI层)
28箭头30氧化硅层、绝缘材料层
34晶圆36氧化物、氧化物层
38、54氮化硅层40、44、56、156光刻胶层
42、46、58、158沟槽48、152、162间隔物
49、50外延硅层、外延区域
52多晶硅59绝缘材料
60浅沟槽隔离(STI)
62绝缘层上硅区域(SOI区域)
64、66区域70、72部份
90N沟道HOT FET92P沟道HOT FET
96、98FET100栅极电极
102栅极绝缘层104源极与漏极区域
154、164层
具体实施方式
下列详细说明仅用于解释而非用于限制本发明或本发明之应用与用途。再者，并不使用任何出现在前述技术领域、先前技术、发明内容或后续实施方式之表示或暗含的理论限制本发明。
图1至13示意地描述根据本发明多种实施例之CMOS集成电路20及制造该CMOS集成电路之方法步骤。在这些描述性实施例中，只有绘示小部份的CMOS集成电路20。多种制造CMOS装置的步骤为习知，所以为了简短起见，许多习知步骤在此只有简短提及或整个忽略而没有提供已广为所知的制程细节。
如图1所示，根据本发明之一实施例的方法开始于硅层22接合至硅载体衬底24。如在此处所使用，术语“硅层”和“硅衬底”系用于包含通常用于半导体产业之相对纯硅材料以及硅与其它元素(如锗、碳等)混合以形成结晶半导体材料。硅层22及硅载体衬底24将用于形成主体混合定向(HOT)晶体管。以已知之晶圆接合技术将硅层22接合至硅载体衬底24，且该硅层由例如化学机械平坦化(CMP)技术而薄化至约300奈米(nm)之厚度。硅层及硅载体衬底具有不同晶向。选择硅层或硅载体衬底之一以具有<100>晶向，且选择另一者以具有<110>晶向。在较佳实施例中，但非用于限制，硅层会具有<100>晶向且硅载体衬底会具有<110>晶向。在本发明之另一实施例中，硅层会具有<110>晶向且硅载体衬底会具有<100>晶向。<100>晶向或<110>晶向系意指晶向在真实晶向的约±2°内。硅层和硅载体衬底两者较佳具有每平方至少约18至33欧姆(18-33 Ohms per square)的电阻。硅可为N型或P型之杂质掺杂，但较佳为掺杂P型。
图2绘示一方法，而图3与4绘示另一方法，两者皆依据本发明之实施例用以形成绝缘层上硅(SOI)层26叠放设置在硅层22上。图2绘示藉由SIMOX制程形成薄SOI层26之制程。SIMOX制程为习知制程，其中氧离子植入硅层22之次表面(sub-surface)区域，如箭头28所示。硅层及植入之氧接着加热以形成次表面氧化硅层30，该次表面氧化硅层30使SOI层26与硅层22的其余部份电性隔离。SOI层具有约10至100 nm之厚度。SOI层26的厚度根据植入离子的能量而定；亦即，调整植入能量使得植入之氧离子的范围正好超过SOI层26的期望厚度。SOI层26会具有与硅层22相同之晶向，且较佳具有<100>晶向。
在绘示于图3及4之另一实施例中，SOI层26藉由晶圆接合制程形成。如图3所绘示，如二氧化硅之绝缘材料层30(本文中亦有称为＂绝缘材料30″、″绝缘层30″)形成在硅层22的上表面及/或第二硅晶圆34之表面上。晶圆34接合至硅载体衬底24，使得绝缘材料30将硅层22及第二硅晶圆34分开。如图4所绘示，第二硅晶圆藉由例如CMP薄化，以留下薄硅层26在绝缘层30上，该绝缘层30叠放设置在硅层22上。薄硅层26，在此实施例中，可具有10至200nm之厚度，且可轻浓度杂质(lightly impurity doped)掺杂为N型或P型。较佳薄硅层26为杂质掺杂P型至每平方约30欧姆且具有<100>晶向。根据本发明之此实施例，薄硅层26不必与硅层22具有相同晶向。此外，硅层22在此实施例中可较薄，因为绝缘层上硅层26藉由接合至硅层22而形成，而非由硅层22形成。
如图5所示，在绝缘层上硅层26的表面上，将SOI衬底(无论由SIMOX制程或晶圆接合制程形成)氧化以形成具有约5至20nm厚度之薄垫氧化物36。具有约50至200nm之厚度之氮化硅层38接着沉积至垫氧化物36上。垫氧化物可藉由在氧气环境中加热SOI衬底而生长。氮化硅可经由，例如，由二氯硅烷与氨之反应以低压化学气相沉积(LPCVD)或电浆强化化学气相沉积(PECVD)而沉积。氮化硅层如下所述接着使用为CMP抛光停止层(polish stop)。
光刻胶层40施于氮化硅层38之表面且被微影图案化(photolichographically patterned)如图6所示。以图案化之光刻胶层做为蚀刻掩膜而蚀刻出通过氮化硅层38、氧化物层36、绝缘层上硅层26、绝缘层30、硅层22且至硅载体衬底24的上部的沟槽42。沟槽可藉由反应性离子蚀刻(RIE)制程进行蚀刻，使用CF4或CHF3化学品以蚀刻绝缘层，及使用氯或溴化氢化学品以蚀刻硅。光刻胶层40在沟槽42蚀刻完成后移除。或者，微影图案化光刻胶层40可在用于做为氮化硅层38蚀刻的蚀刻掩膜之后移除。氮化硅之蚀刻层可接着做为硬掩膜以掩膜氧化物36、绝缘层上硅26、绝缘层30、硅层22的蚀刻。又在此另一制程中，蚀刻步骤在蚀刻至硅载体衬底24之上部后终止。
移除光刻胶层40之后，施用另一光刻胶层44覆盖沟槽42及氮化硅层38之剩余部份，且被微影图案化如图7所示。以图案化之光刻胶层44做为蚀刻掩膜而蚀刻出通过硅层22上方之叠放设置层且进入硅层22的上部的第二沟槽(沟槽46)。如同沟槽42，沟槽46可藉由反应性离子蚀刻而蚀刻。光刻胶层44可在完成沟槽46的蚀刻后移除，或者，在蚀刻氮化硅层38之后移除。在另一制程中，图案化之氮化硅层接着做为硬掩膜以掩膜而蚀刻出通过氧化物36、SOI层26、绝缘层30且进入硅层22之上部的沟槽。在此例示之延伸进入硅载体层24之一部份的沟槽42为在延伸进入硅层22之一部份的沟槽46之前蚀刻。根据本发明之另一实施例(未图标)，两沟槽的形成顺序可相反且沟槽46可先形成。
在移除光刻胶层44之后，氧化硅或氮化硅层沉积在包括两沟槽42及44内之结构表面。氧化物或氮化物层被非等向性蚀刻(如藉由RIE)以形成侧壁间隔物48在沟槽42及沟槽46的垂直侧壁上，如图8所示。
根据本发明之一实施例，选择性外延硅层49及50接着生长于暴露之硅表面上。外延硅层49生长在位于沟槽42底部之硅载体衬底24之暴露表面上，且外延硅层50生长在位于沟槽46底部之硅层22的暴露表面上。外延硅层可经由在HCl存在下还原硅烷(SiH4)或二氯硅烷(SiH2Cl2)而生长。氯源的存在促进生长的选择特性，亦即，与在绝缘层(氧化硅或氮化硅)表面上相比外延硅优先生长在暴露硅表面上。外延硅层生长之晶向模仿其生长于其上之硅材料的晶向。于较佳实施例中，外延硅层49以相同于硅载体衬底24之<110>晶向生长而外延硅层50以相同于硅层22之<100>晶向生长。侧壁间隔物48延缓在沟槽46的边缘与尤其是沟槽42的边缘上之沉积硅成核(nucleation)。当不存在侧壁间隔物时，外延生长可能在沟槽边缘及沟槽底部所暴露之硅上成核，造成较不理想之外延硅层。这在外延硅层生长于沟槽42中时特别为真，因为生长层可能在暴露在沟槽边缘之<100>晶向硅层22上以及在暴露于沟槽底部之<110>晶向硅载体衬底24上成核。可能会发生一些硅过度生长超出氮化硅层38的顶部表面之高度，且一些硅可以多晶硅52之形式沉积在氮化硅层38上。多晶硅52可形成因为外延生长制程不是完美选择性的。在氮化硅层上的硅沉积会是多晶硅而非单晶硅，因为氮化硅没有提供沉积硅可模仿之结晶结构。
过度生长超出氮化硅层38之顶部高度之选择性外延硅以及多晶硅52可藉由CMP移除如图10所示。氮化硅层38使用做为CMP之抛光停止层。
在外延硅层平坦化之后，于该结构上沉积另一氮化硅层54。光刻胶层56施于氮化硅层54上，且被图案化如图11所示。移除间隔物48且沟槽58经由反应性离子蚀刻使用图案化之光刻胶层为蚀刻掩膜而形成。
移除间隔物48及形成沟槽58之后，移除光刻胶层56且沟槽58藉由例如LPCVD或PECVD而以沉积氧化物或其它绝缘材料59填满。所沉积之绝缘材料59填满沟槽58，但亦沉积在氮化硅层54上。在氮化硅层54上之过多绝缘材料使用CMP抛光移除以完成浅沟槽隔离(STI)60之形成，如第12图所示。氮化硅层54使用做为CMP制程期间之抛光停止层。在此技术领域具有通常知识者会了解，在介于组成集成电路之装置间，可使用许多已知制程及许多已知材料来形成STI或其它形式之电性隔离，且因此该些已知制程及材料不需在此讨论。图12所示之结构包括绝缘层上硅区域62及两主体硅区域64及66，其中一者具有<100>晶向且另一者具有<110>晶向。在形成浅沟槽隔离之后，分别在主体区域64及66之外延硅49及50可适当地以已知方法，例如经由离子植入，进行杂质掺杂。根据本发明之较佳实施例，主体区域64具有<110>晶向且以N型杂质而杂质掺杂，且主体区域66具有<100>晶向且以P型杂质而杂质掺杂。无论硅载体衬底24为<110>晶向且硅层22为<100>晶向，或硅载体衬底24为<100>晶向且硅层22为<110>晶向，<100>晶向区域系以P型杂质而杂质掺杂且<110>晶向区域系以N杂质而杂质掺杂。SOI区域62亦可适当地以相同方式杂质掺杂。如果SOI区域62将用于制造CMOS装置，区域62之部份70可以P型杂质掺杂而形成P型井以用于形成N沟道FET，且区域62之其它部份72可以N型杂质掺杂而形成N型井以用于形成P沟道FET。多种区域的杂质掺杂可由已知方法进行，根据欲制造之装置种类决定植入物种、剂量及能量。所选区域的植入可经由例如以图案化之光刻胶掩膜其它区域而进行。
在剥除剩余之层36、38及54之后，实质上共平面之SOI层26与各主体硅区域64及66之表面为暴露的，且此结构可用于制造施行所需集成电路功能之必须FET。可使用习知CMOS制程技术实施多种装置、在SOI区域62之部份70与72中之CMOS装置及在区域64与66中之主体HOT P沟道与N沟道FET之制造。用于制造CMOS装置之多种制造流程对此领域具有通常知识者为已知者且不需在此叙述。在此领域具有通常知识者知道多种制造流程系根据参数而定，如所使用之最小几何、可用于激活IC之电源供应、IC所期望之处理速度等。无论用于完成IC制造之制程流程为何，根据本发明之一实施例之IC20包括制造于具有<100>晶向之主体硅区域66之主体N沟道HOTFET90、制造于具有<110>晶向之主体硅区域64之主体P沟道HOT FET92、及分别制造于SOI区域62之部份70与72之CMOS晶体管N沟道SOIFET96及P沟道SOIFET98。虽然未图标，一些电性隔离形式例如浅沟槽隔离可在FET96与98之间施行，或者，可连接接面104在一起以经由pn接面的性质提供电性隔离。于例示实施例中，硅载体衬底24及外延硅49为<110>晶向且P沟道HOT FET92为形成于区域64中。又根据例示实施例，硅层22及外延硅50为<100>晶向且N沟道HOT FET90形成于区域66中。选择硅载体衬底为<110>晶向在此例示实施例为随机的；在此领域具有通常知识者会了解硅载体衬底24及硅层22之晶向可互换而未偏离本发明之范围及目的。
如图13所示，各主体HOT FET90与92及各SOIFET96及98包括叠放设置在栅极绝缘层102上之栅极电极100，且源极与漏极区域104位于栅极电极的两侧。栅极电极可为多晶硅、金属、硅化物等。栅极绝缘层可为二氧化硅、氮氧化硅、高介电常数材料等，根据所施行特定电路功能所需而定。该源极与漏极区域可包含单一杂质掺杂区域或多个对准杂质掺杂区域(aligned impurity doped region)。虽然未图标，导电接触栓(contact)与导电线路(trace)可与适当栅极电极及源极与漏极区域耦合，以使集成电路之多种晶体管互连。
根据例示实施例，尤其如图6至10所示，<100>及<110>晶向外延区域49及50在相同步骤生长，且其表面在相同步骤抛光。根据本发明之进一步实施例，两个外延区域可分别生长如图14至18所示。根据本发明之此实施例之方法类似于前述方法直至图6所述之步骤。然而不同于图7所示之蚀刻第二沟槽，氧化硅或氮化硅层沉积在氮化物层38之表面上及沟槽42内。沉积层经反应性离子蚀刻以形成侧壁间隔物152在沟槽42之边缘上如图14所示。
根据本发明之此实施例，尤其如图15所示，经由如上所述之选择性外延生长制程生长选择性硅外延层154在沟槽42中。层154之生长为成核在沟槽42底部所暴露之硅载体衬底24之部份，且以相同于衬底24之晶向生长。
施用另一光刻胶层156覆盖氮化物层38之表面及硅外延层154之表面。该光刻胶层经微影图案化且做为掩膜以用于蚀刻出延伸进入硅层22之额外沟槽158，如图16所示。沟槽158可以RIE制程蚀刻。
蚀刻沟槽158之后，移除光刻胶层156且沉积另一氧化硅或氮化硅层在氮化物层38之表面及硅外延层154之表面上。所沉积之氧化硅或氮化硅层经反应性离子蚀刻以形成在沟槽158壁上之侧壁间隔物162，如图17所示。根据本发明之进一步实施例，所沉积之层系通过保持在外延层154表面上之图案化光刻胶层而被蚀刻，因此未从外延层154移除该层。
根据本发明之此实施例，如图18所示，选择性硅外延层164以上述之选择性外延生长制程生长于沟槽158中。层164的生长为成核在沟槽158底部所暴露之硅层22之部份，且以相同于硅层22之晶向生长。如果用于形成间隔物162的沉积层保留在外延层154上，该层避免在层164之生长期间在层154上的进一步外延生长。
在氮化物层38的任何过度外延硅生长可藉由CMP移除，无论是以生长外延层164后之单一CMP步骤，或是以两个分开步骤，在每一分开外延硅生长步骤之后进行一次。CMP步骤或多个步骤可用于移除任何用于形成间隔物162之沉积层之所余部份。在CMP移除多余外延硅之后，结构相同于图10所示者。制造积体结构的制程可接着如图11至13所示之步骤完成。如前述实施例，两个沟槽被蚀刻且接着以外延硅填满之顺序可反转且不偏离本发明之范围。
虽至少一例示实施例已于前述详细说明，须了解存在数量繁多的改变。亦须了解的是例示实施例仅用于例示，且非用于以任何方式限制本发明之范围、应用或配置。反而前述详细说明系提供在相关技术领域中具有通常知识者方便的准则以应用例示实施例。须了解在功能及组件配置可进行多种变化而不偏离本发明的范围，本发明的范围如所附权利要求书及其法律上均等物所界定者。

Claims (10)

1.一种集成电路(20)，包括：
主体硅衬底(24)，包括具有<100>晶向的第一区域(64，66)及<110>晶向的第二区域(66，64)；
叠放设置在该主体硅衬底的一部份上的绝缘层上硅层(62)；
至少一场效应晶体管(96，98)，形成于该绝缘层上硅层(62)中；
至少一P沟道场效应晶体管(90，92)，形成在该第二区域(66，64)中；以及
至少一N沟道场效应晶体管(90，92)，形成在该第一区域(64，66)中。
2.如权利要求1所述的集成电路(20)，其中，该第一区域(64)包括形成在该硅衬底(24)上的P型杂质掺杂区域，且该第二区域(66)包括形成在接合至该硅衬底(24)的硅层(22)上的N型杂质掺杂区域。
3.如权利要求1所述的集成电路(20)，其中，该第二区域(64)包括形成在该硅衬底(24)上的N型杂质掺杂区域，且该第一区域(66)包括形成在接合至该硅衬底的硅层(22)上的P型杂质掺杂区域。
4.一种集成电路(20)，包括：
硅衬底(24)，具有第一晶向；
第一硅层(22)，具有不同于该第一晶向的第二晶向且接合至该硅衬底(24)，该第一硅层(22)具有上表面；
绝缘层(30)，在该第一硅层(22)的上表面上；
第二硅层(26)，在该绝缘层(30)上；
第一晶向的第一区域(49)，生长在该硅衬底(24)上；
第二晶向的第二区域(50)，生长在该第一硅层(22)上；
第一沟道导电型的第一场效应晶体管(92)，形成在该第一区域(49)中；
第二沟道导电型的第二场效应晶体管(90)，形成在该第二区域(50)中；以及
互补场效应晶体管(96，98)，形成在该第二硅层(26)中。
5.如权利要求4所述的集成电路(20)，其中，该第一晶向包括<110>晶向且该第二晶向包括<100>晶向。
6.如权利要求4所述的集成电路(20)，其中，该第一晶向包括<100>晶向且第二晶向包括<110>晶向。
7.一种制造集成电路(20)的方法，包括下列步骤：
提供具有第一晶向的硅衬底(24)；
提供叠放设置在该硅衬底(24)上的硅层(22)，该硅层(22)具有不同于该第一晶向的第二晶向；
形成绝缘层上硅层(26)叠放设置在该硅层的一部份上；
在该硅衬底(24)的一部份上生长具有该第一晶向的第一外延层(49)；
在该硅层(22)的一部份上生长具有该第二晶向的第二外延层(50)；以及
在该第一外延层(49)中形成第一场效应晶体管(92)、在该第二外延层(50)中形成第二场效应晶体管(90)及在该绝缘层上硅层(26)中形成第三场效应晶体管(96，98)。
8.如权利要求7所述的方法，其中，提供具有第一晶向的硅衬底(24)的步骤包括提供具有<100>晶向的硅衬底(24)的步骤，而且，提供叠放设置在该硅衬底上的硅层(22)的步骤包括提供具有<110>晶向的硅层(22)的步骤。
9.如权利要求7所述的方法，其中，提供具有第一晶向的硅衬底(24)的步骤包括提供具有<110>晶向的硅衬底(24)的步骤，且其中，提供叠放设置在该硅衬底(24)上的硅层(22)的步骤包括提供具有<100>晶向的硅层(22)的步骤。
10.如权利要求9所述的方法，其中，在该第一外延层(49)中形成第一场效应晶体管(92)的步骤包括形成P沟道场效应晶体管的步骤，以及在该第二外延层(50)中形成第二场效应晶体管(90)的步骤包括形成N沟道场效应晶体管的步骤。
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