US20050040463A1 - Transistor structures and processes for forming same - Google Patents

Transistor structures and processes for forming same Download PDF

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US20050040463A1
US20050040463A1 US10/956,196 US95619604A US2005040463A1 US 20050040463 A1 US20050040463 A1 US 20050040463A1 US 95619604 A US95619604 A US 95619604A US 2005040463 A1 US2005040463 A1 US 2005040463A1
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Zhongze Wang
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • This invention relates to a semiconductor device and fabrication thereof and, more particularly, to Source-Drain On Insulator (SDOI) transistor structures and fabrication methods thereof.
  • SDOI Source-Drain On Insulator
  • SDOI transistors utilize Source-Drain On Insulator (SDOI) transistors for various applications.
  • An SDOI transistor is a high performance transistor that has a very low junction capacitance, comparable to that of a Silicon On Insulator (SOI) transistor, but doesn't possess a floating body effect that is prevalent in SOI transistors.
  • SOI Silicon On Insulator
  • the floating body effect of an SOI transistor has some advantages and some disadvantages. On the positive side, it results in higher current drive and better substrate-threshold voltage (V T ) swing (body effect is defined as V T sensitivity to body voltage drop (Vb)). On the negative side it can result in history effect and high off-state current leakage. It is advantageous to use SOI transistors on circuits that need high current drive and are tolerant to off-state current leakage. However, for other circuits, such as pass gate logic, the floating body effect will cause problems.
  • Vc equals the control voltage
  • Vt equals the transistor threshold voltage
  • Vb the body voltage
  • the present invention addresses various characteristics of devices, such as an SOI transistor, and particularly addresses such issues as history effect and high current drive.
  • a significant focus of the present invention comprises SDOI field effect transistor structures and fabrication methods thereof, which will become apparent to those skilled in the art from the following disclosure.
  • An exemplary implementation of the present invention includes source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried depletion layer under the channel region, which provides electrical isolation between the body and the channel of each transistor structure.
  • SDOI source-drain on insulator
  • SDOI source-drain on insulator
  • an SDOI transistor structure is formed by creating electrical isolation below the SDOI transistor channel region that spans completely between the SDOI insulators.
  • the electrical isolation may be formed by implanting an appropriate conductive dopant to form a depletion layer below the channel region.
  • the electrical isolation may be formed by implanting an appropriate conductive dopant to form a p-n junction below the channel region of an SDOI transistor structure that spans completely between SDOI insulators.
  • FIG. 1 is a cross-sectional view of a semiconductor substrate section showing an example of a completed SDOI transistor structure of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor substrate section showing the early stages of an SDOI transistor following a PWell implant and a PWell drive into a P type substrate.
  • FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 following a patterning of nitride, a trench etch into the PWell region.
  • FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 following the formation of oxide to define a source-drain location over oxide for an SDOI transistor.
  • FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 following the patterning and etching of oxide component of the SDOI transistor.
  • FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 following the selective deposition of epitaxial silicon, followed by the deposition of amorphous silicon.
  • FIG. 7 is a subsequent cross-sectional view taken from FIG. 6 following the planarization of the epitaxial silicon and amorphous silicon, the removal of the patterned nitride, the placing and patterning of photoresist, followed by an n-depletion layer implant.
  • FIG. 8 is a subsequent cross-sectional view taken from FIG. 7 following the formation of an SDOI transistor gate and a self-aligned source-drain extension implant.
  • FIG. 9 is a subsequent cross-sectional view taken from FIG. 8 following the formation of SDOI transistor gate spacers followed by a source-drain implant to complete transistor formation.
  • FIG. 10 is an overhead plan view of FIG. 9 showing a completed SDOI transistor structure of an embodiment of the present invention
  • FIG. 11 is a subsequent cross-sectional view taken from FIG. 6 following the planarization of the epitaxial silicon and amorphous silicon, the removal of the patterned nitride, the placing and patterning of photoresist, followed by a PWell implant.
  • FIG. 12 is a subsequent cross-sectional view taken from FIG. 11 following the formation of an SDOI transistor gate and a self-aligned source-drain extension implant.
  • FIG. 13 is a subsequent cross-sectional view taken from FIG. 12 following the formation of SDOI transistor gate spacers followed by a source-drain implant to complete transistor formation.
  • FIG. 14 is an overhead plan view of FIG. 13 showing a completed SDOI transistor of an embodiment of the present invention.
  • FIG. 15 is a simplified block diagram of a semiconductor system comprising a processor and memory device to which the present invention may be applied.
  • wafer and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
  • SOI silicon-on-insulator
  • SOS silicon-on-sapphire
  • doped and undoped semiconductors epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
  • previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation.
  • the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.
  • FIG. 1 depicts an example of an embodiment of a completed Source-Drain On Insulator (SDOI) transistor structure of the present invention.
  • a semiconductor substrate 10 has a conductive Well 11 implanted therein.
  • a transistor gate 16 formed from a conductive material overlies gate oxide 15 .
  • an underlying depletion layer or a p-n junction (region 13 ) spans between the bottom surfaces of the shallow trench isolation material 12 .
  • Implanted source-drain regions (electrodes) 18 are formed from amorphous silicon and epitaxial silicon and transistor gate spacers 17 isolate the vertical sidewalls of transistor gate 16 .
  • the fabrication methods to form variations of the Source-Drain On Insulator (SDOI) transistor structure of the present invention now follow.
  • oxide layer 21 is formed over semiconductive substrate 20 , such as a p-type silicon substrate. Oxide layer 21 acts as a buffer from subsequent p or n-type conductive Well implants.
  • Mask layer 22 such as a photoresist, is placed to define a subsequently formed conductive Well.
  • a p-type implant is performed, such as a Boron implant, to form PWell 23 .
  • an effective PWell implant comprises a series of Boron implants, including a first Boron implant dose of approximately 5 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 25 KeV, a second Boron implant dose of approximately 1 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 100 KeV and a third Boron implant dose of approximately 3 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 180 KeV.
  • oxide layer 21 has been stripped and a quality gate oxide layer 30 is grown on semiconductive substrate 20 , followed by the deposition of nitride layer 31 , having a thickness of anywhere from 500-900 Angstroms.
  • photoresist 32 is placed, patterned and then etched along with exposed portions of nitride 31 to define the active area of a SDOI transistor structure.
  • shallow trenches 33 are formed into semiconductor substrate 20 .
  • a preferred depth of trenches 33 is approximately 3000 Angstroms and an etch using CF 4 , at flow rate of 40 sccm and temperature of 70° C., for a time duration of approximately 10 seconds, is sufficient to obtain the desired trench depth.
  • an insulation material 40 such as oxide, is deposited and planarized down to the surface of nitride 31 to form the insulation component (i.e., trench isolation material) of the SDOI transistor structure.
  • photoresist 51 is placed and patterned, which is followed by oxide 40 being etched selective to nitride 31 in order to recess oxide 40 below the lower level of nitride 31 to expose the silicon of PWell 23 .
  • oxide 40 being etched selective to nitride 31 in order to recess oxide 40 below the lower level of nitride 31 to expose the silicon of PWell 23 .
  • an etch using C 4 F 6 at flow rate of 8 sccm and temperature of 70° C. for a time period of approximately 20 seconds will recess oxide 40 to leave approximately 2000 Angstroms of oxide 40 .
  • Photoresist 51 is then stripped.
  • a silicon epi deposition to form silicon structures 60 may be accomplished by decomposing DCS (Si 2 H 2 Cl 2 ) in an H2 and HCl environment at 800 to 1000° C.
  • a preferred silicon epi thickness is 500 to 1500 Angstroms.
  • amorphous silicon 61 is deposited to cover exposed oxide regions 40 , epi silicon structures 60 and exposed nitride 31 .
  • An amorphous silicon deposition to form amorphous silicon layer 61 may be accomplished by decomposing SiH4 at approximately 500° C.
  • a preferred amorphous silicon thickness is 2000 to 3000 Angstroms.
  • amorphous silicon 61 and epi silicon structures 60 are preferably planarized back to nitride 31 (seen in FIG. 5 ), such as using chemical mechanical Planarization (CMP). Planarized amorphous silicon 61 and planarized epi silicon structures 60 will become the source drain regions of the SDOI transistor structure following a subsequent source-drain implant.
  • nitride 31 is removed, such as by using a 125-150° C. phosphorus acid etch to remove the nitride selective to silicon and oxide, to expose the underlying silicon of PWell 23 .
  • N-depletion layer 71 serves an important function in this exemplary embodiment of the present invention as it provides electrical isolation between the transistor body (resident in PWell 23 ) and p-region 72 .
  • P-region 72 will function as the channel for the SDOI transistor structure.
  • N-depletion layer 71 functions properly when the depth of the n-depletion is such that it completely spans between laterally spaced oxide regions 40 and yet is sufficiently deep to avoid hindering proper operation of an overlying channel region.
  • performing an n-depletion implant into PWell 23 with oxide regions 40 having a thickness of approximately 2800 Angstroms, a Phosphorus implant dose of approximately 5 ⁇ 10 11 to 1 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 180 KeV, will obtain the desired implant depth for the n-type depletion layer 71 .
  • the thickness of oxide regions 40 should be in the order of 2500 Angstroms or greater.
  • the body to channel isolation provided by n-type depletion layer 71 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient.
  • the improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the depletion layer.
  • the method is not dependent on channel length or the desired threshold voltage (V T ) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust V T although if so desired, one may be performed without altering the effectiveness of n-depletion 71 spanning between the bottoms of the shallow trench isolation 40 .
  • a conductive material such as metal, conductive polysilicon or metal silicide, is formed, patterned and etched to form transistor gate 81 and an underlying gate oxide 80 , by means known to those skilled in the art.
  • source-drain extension implant such as an Arsenic (As) implant, to form an n-channel transistor, is performed to form source-drain extension regions 82 that are self-aligned to gate 81 .
  • One implant example is an As implant dose of approximately 2 ⁇ 10 14 Atoms/cm 2 , with an implant energy of approximately 8 KeV. Because the As implant is very shallow, it will not connect to or alter the functionality of underlying n-depletion region 71 .
  • transistor gate spacers 90 are formed followed by a source-drain implant, such as an Arsenic (As) implant dose of approximately 2 ⁇ 10 15 Atoms/cm 2 , with an implant energy of approximately 15 KeV, to form source-drain regions (electrodes) 91 to complete the formation of a Source-Drain On Insulator (SDOI) transistor structure of the present invention. Fabrication methods known to those skilled in the art are then used to complete the processing of the semiconductor device.
  • As Arsenic
  • SDOI Source-Drain On Insulator
  • FIG. 10 depicts an overhead view of a completed Source-Drain On Insulator (SDOI) transistor structure as described in the process steps taken in FIG. 2-9 .
  • SDOI Source-Drain On Insulator
  • underlying substrate 20 (not seen) has been implanted with conductive dopants to form PWell 23 .
  • Source/drain regions 91 are implanted into PWell 23 and the underlying channel region 72 is shown with dashed lines and underlies SDOI transistor gate 81 .
  • the sidewalls of SDOI transistor gate 81 are isolated by insulation spacers 90 .
  • FIGS. 2-6 and FIGS. 11-13 A second exemplary fabrication of an embodiment of the present invention is depicted in FIGS. 2-6 and FIGS. 11-13 .
  • This embodiment covers the case for selecting a p-type silicon substrate 20 .
  • an NWell implant is performed, such as an Arsenic or Phosphorus implant, to form NWell 23 into silicon substrate 20 .
  • An example of the NWell implant comprises a phosphorous implant of approximately 3 ⁇ 10 12 Atoms/cm 2 ; with an implant energy of approximately 150 KeV followed by a phosphorous implant of approximately 5 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 360 KeV.
  • the NWell implant does not need to be performed as will be discussed further in this embodiment.
  • amorphous silicon 61 and epi silicon structures 60 are preferably planarized back to nitride 30 (seen in FIG. 6 ), such as using chemical mechanical Planarization (CMP). Planarized amorphous silicon 61 and planarized epi silicon structures 60 will become the source drain regions of the SDOI transistor structure following a subsequent source-drain implant.
  • nitride 30 is removed, such as by using a 125-150° C. phosphorus acid etch to remove the nitride selective to silicon and oxide, to expose the underlying silicon of NWell 23 .
  • photoresist 110 is placed and patterned to allow for a following PWell implant that forms p-n junction 111 at the base of and extending between laterally spaced oxide regions 40 .
  • P-n junction 111 serves an important function in this exemplary embodiment of the present invention as it provides electrical isolation between the transistor body (resident in NWell 23 ) and PWell region 112 .
  • PWell region 112 will function as a channel for the SDOI transistor structure.
  • the p-n junction functions properly when the depth of p-n junction 111 is such that it completely spans between laterally spaced oxide regions 40 and is also sufficiently deep to avoid hindering proper operation of an overlying channel region.
  • oxide regions 40 having a thickness of approximately 2800 Angstroms
  • performing a PWell implant into NWell 23 requires a Boron implant dose of approximately 5 ⁇ 10 12 Atoms/cm 2 , with an implant energy of approximately 30 KeV.
  • the NWell implant is not preformed
  • a p-n junction will be formed at the base of and extending between laterally spaced oxide regions 40 .
  • the desired effect of the p-n junction is attained and the NWell implant is not necessary (though it may be implemented if so desired).
  • the body to channel isolation provided by p-n junction 111 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient.
  • the improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the p-n junction.
  • the method is not dependent on channel length or the desired threshold voltage (V T ) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust V T , although if so desired, one may be performed without altering the effectiveness of p-n junction 111 spanning between the bottoms of the laterally spaced shallow trench isolation regions (oxide regions 40 ).
  • a conductive material such as metal, conductive polysilicon and metal silicide, is formed, patterned and etched to form transistor gate 121 and underlying gate oxide 120 , by means known to those skilled in the art.
  • source-drain extension implant such as an Arsenic (As) implant to form an n-channel transistor, is performed to form source-drain extension regions 122 that are self-aligned to gate 121 .
  • One implant example is an As implant dose of approximately 2 ⁇ 10 14 Atoms/cm 2 , with an implant energy of approximately 10 KeV. Because the As implant is very shallow it will not connect to or alter the functionality of underlying p-n junction 111 spanning between the bottom of the shallow trench isolation regions (oxide regions 40 ).
  • transistor gate spacers 130 are formed followed by a source-drain implant, such as an Arsenic (As) implant dose of approximately 2 ⁇ 10 15 Atoms/cm 2 , with an implant energy of approximately 15 KeV, to form source-drain regions (electrodes) 131 to complete the formation of a Source-Drain On Insulator (SDOI) transistor structure of the present invention. Fabrication methods known to those skilled in the art are then used to complete the processing of the semiconductor device.
  • As Arsenic
  • SDOI Source-Drain On Insulator
  • FIG. 14 depicts an overhead view of a completed Source-Drain On Insulator (SDOI) transistor structure as described in the process steps taken in FIG. 2-6 and 11 - 13 .
  • SDOI Source-Drain On Insulator
  • underlying substrate 20 (not seen) has been implanted with conductive dopants to form PWell 23 .
  • Source/drain regions 131 are implanted into PWell 23 and the underlying channel region 112 is shown with dashed lines and underlies SDOI transistor gate 121 .
  • the sidewalls of SDOI transistor gate 121 are isolated by insulation spacers 130 .
  • the exemplary embodiments have been discussed in reference to forming n-channel SDOI transistor structures. However, these concepts, taught in the exemplary embodiments, may be utilized by one of ordinary skill in the art to form p-channel SDOI transistor structures as well, by simply replacing the implants with the proper type of doping implant. For example, in exemplary embodiment of FIGS. 2-6 and 11 - 13 , the NWell implant demonstrated for FIG. 2 would be replaced with a PWell implant, the PWell implant demonstrated for FIG. 11 would be replaced with an NWell implant and the n-type source-drain implant demonstrated for FIG. 12 would be replaced with a p-type source-drain implant.
  • the completed SDOI transistor structure and the fabrication method used therefor may be for various types of devices, such as embedded memory devices, and may be used in numerous semiconductor applications and particularly in, but not limited to, DRAMs.
  • the present invention may be applied to a semiconductor system, such as the one depicted in FIG. 15 , the general operation of which is known to one skilled in the art.
  • FIG. 15 represents a general block diagram of a semiconductor system comprising a processor 150 and a memory device 151 showing the basic sections of a memory integrated circuit, such as row and column address buffers, 153 and 154 , row and column decoders, 155 and 156 , sense amplifiers 157 , memory array 158 and data input/output 159 , which are manipulated by control/timing signals from the processor through control 152 .
  • a memory integrated circuit such as row and column address buffers, 153 and 154 , row and column decoders, 155 and 156 , sense amplifiers 157 , memory array 158 and data input/output 159 , which are manipulated by control/timing signals from the processor through control 152 .

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Abstract

Source drain on insulator (SDOI) transistors and methods of forming SDOI transistors are described. The SDOI transistors are formed to provide electrical isolation between the body and the channel of the transistor. The electrical isolation comprises either a depletion layer or a p-n junction formed below the SDOI transistor channel region that spans laterally between the SDOI insulators.

Description

  • This application is a divisional to U.S. patent application Ser. No. 10/463,159, filed Jun. 17, 2003.
    • FIELD OF THE INVENTION
  • This invention relates to a semiconductor device and fabrication thereof and, more particularly, to Source-Drain On Insulator (SDOI) transistor structures and fabrication methods thereof.
    • BACKGROUND OF THE INVENTION
  • Semiconductor devices utilize Source-Drain On Insulator (SDOI) transistors for various applications. An SDOI transistor is a high performance transistor that has a very low junction capacitance, comparable to that of a Silicon On Insulator (SOI) transistor, but doesn't possess a floating body effect that is prevalent in SOI transistors.
  • The floating body effect of an SOI transistor has some advantages and some disadvantages. On the positive side, it results in higher current drive and better substrate-threshold voltage (VT) swing (body effect is defined as VT sensitivity to body voltage drop (Vb)). On the negative side it can result in history effect and high off-state current leakage. It is advantageous to use SOI transistors on circuits that need high current drive and are tolerant to off-state current leakage. However, for other circuits, such as pass gate logic, the floating body effect will cause problems.
  • One example of the undesirable operations the floating body effect may cause in a pass logic gate may be seen in an example wherein: Vc equals the control voltage, Vt equals the transistor threshold voltage, and Vb equals the body voltage. During the “on” state the gate is at Vc, the source is at Vc, the drain is at Vc−VT, and the body is at approximately Vc−VT. When the device is switched to the “off” state, the gate goes to zero volts, the source stays at Vc and the body goes to Vb˜Vc/2 (i.e., the history effect). When the drain switches to zero volts, the n+junction between the source and the body becomes forward biased and will draw large bipolar current (i.e., undesirable high current drive).
  • The present invention addresses various characteristics of devices, such as an SOI transistor, and particularly addresses such issues as history effect and high current drive. A significant focus of the present invention comprises SDOI field effect transistor structures and fabrication methods thereof, which will become apparent to those skilled in the art from the following disclosure.
    • SUMMARY OF THE INVENTION
  • An exemplary implementation of the present invention includes source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried depletion layer under the channel region, which provides electrical isolation between the body and the channel of each transistor structure.
  • Another exemplary implementation of the present invention include source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried p-n junction under the channel region, which provides substantial (if not complete) electrical isolation between the body and the channel of each transistor structure.
  • In one exemplary implementation, an SDOI transistor structure is formed by creating electrical isolation below the SDOI transistor channel region that spans completely between the SDOI insulators. The electrical isolation may be formed by implanting an appropriate conductive dopant to form a depletion layer below the channel region.
  • In an alternate exemplary implementation, the electrical isolation may be formed by implanting an appropriate conductive dopant to form a p-n junction below the channel region of an SDOI transistor structure that spans completely between SDOI insulators.
    • BRIEF DESCRIPTION OF THE DRAWING
  • FIG. 1 is a cross-sectional view of a semiconductor substrate section showing an example of a completed SDOI transistor structure of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor substrate section showing the early stages of an SDOI transistor following a PWell implant and a PWell drive into a P type substrate.
  • FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 following a patterning of nitride, a trench etch into the PWell region.
  • FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 following the formation of oxide to define a source-drain location over oxide for an SDOI transistor.
  • FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 following the patterning and etching of oxide component of the SDOI transistor.
  • FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 following the selective deposition of epitaxial silicon, followed by the deposition of amorphous silicon.
  • FIG. 7 is a subsequent cross-sectional view taken from FIG. 6 following the planarization of the epitaxial silicon and amorphous silicon, the removal of the patterned nitride, the placing and patterning of photoresist, followed by an n-depletion layer implant.
  • FIG. 8 is a subsequent cross-sectional view taken from FIG. 7 following the formation of an SDOI transistor gate and a self-aligned source-drain extension implant.
  • FIG. 9 is a subsequent cross-sectional view taken from FIG. 8 following the formation of SDOI transistor gate spacers followed by a source-drain implant to complete transistor formation.
  • FIG. 10 is an overhead plan view of FIG. 9 showing a completed SDOI transistor structure of an embodiment of the present invention
  • FIG. 11 is a subsequent cross-sectional view taken from FIG. 6 following the planarization of the epitaxial silicon and amorphous silicon, the removal of the patterned nitride, the placing and patterning of photoresist, followed by a PWell implant.
  • FIG. 12 is a subsequent cross-sectional view taken from FIG. 11 following the formation of an SDOI transistor gate and a self-aligned source-drain extension implant.
  • FIG. 13 is a subsequent cross-sectional view taken from FIG. 12 following the formation of SDOI transistor gate spacers followed by a source-drain implant to complete transistor formation.
  • FIG. 14 is an overhead plan view of FIG. 13 showing a completed SDOI transistor of an embodiment of the present invention.
  • FIG. 15 is a simplified block diagram of a semiconductor system comprising a processor and memory device to which the present invention may be applied.
    • DETAILED DESCRIPTION OF THE INVENTION
  • The following exemplary implementations are in reference to SDOI transistor structures and the fabrication thereof in a semiconductor assembly. While the concepts of the present invention are conducive to the fabrication of an SDOI transistor for a semiconductor logic device the concepts taught herein may be applied to other semiconductor devices that would likewise benefit from the use of the SDOI transistor structure and processes disclosed herein. Therefore, the depictions of the present invention in reference to a pass SDOI transistor structure or a semiconductor logic device SDOI transistor structure and the manufacture thereof, are not meant to so limit the extent to which one skilled in the art may apply the concepts taught hereinafter.
  • In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.
  • FIG. 1 depicts an example of an embodiment of a completed Source-Drain On Insulator (SDOI) transistor structure of the present invention. Referring now to FIG. 1, a semiconductor substrate 10 has a conductive Well 11 implanted therein. A transistor gate 16, formed from a conductive material overlies gate oxide 15. In channel region 14, an underlying depletion layer or a p-n junction (region 13) spans between the bottom surfaces of the shallow trench isolation material 12. Implanted source-drain regions (electrodes) 18 are formed from amorphous silicon and epitaxial silicon and transistor gate spacers 17 isolate the vertical sidewalls of transistor gate 16. The fabrication methods to form variations of the Source-Drain On Insulator (SDOI) transistor structure of the present invention now follow.
  • A first exemplary fabrication of an embodiment the present invention is depicted in FIGS. 2-9. Referring now to FIG. 2, oxide layer 21 is formed over semiconductive substrate 20, such as a p-type silicon substrate. Oxide layer 21 acts as a buffer from subsequent p or n-type conductive Well implants. Mask layer 22, such as a photoresist, is placed to define a subsequently formed conductive Well. In this example, a p-type implant is performed, such as a Boron implant, to form PWell 23. For example, with an oxide 21 thickness of approximately 90 Angstroms, an effective PWell implant comprises a series of Boron implants, including a first Boron implant dose of approximately 5×1012 Atoms/cm2, with an implant energy of approximately 25 KeV, a second Boron implant dose of approximately 1×1012 Atoms/cm2, with an implant energy of approximately 100 KeV and a third Boron implant dose of approximately 3×1012 Atoms/cm2, with an implant energy of approximately 180 KeV.
  • Referring now to FIG. 3, oxide layer 21 has been stripped and a quality gate oxide layer 30 is grown on semiconductive substrate 20, followed by the deposition of nitride layer 31, having a thickness of anywhere from 500-900 Angstroms. Next, photoresist 32 is placed, patterned and then etched along with exposed portions of nitride 31 to define the active area of a SDOI transistor structure. During this etch, shallow trenches 33 are formed into semiconductor substrate 20. A preferred depth of trenches 33 is approximately 3000 Angstroms and an etch using CF4, at flow rate of 40 sccm and temperature of 70° C., for a time duration of approximately 10 seconds, is sufficient to obtain the desired trench depth.
  • Referring now to FIG. 4, an insulation material 40, such as oxide, is deposited and planarized down to the surface of nitride 31 to form the insulation component (i.e., trench isolation material) of the SDOI transistor structure.
  • Referring now to FIG. 5, photoresist 51 is placed and patterned, which is followed by oxide 40 being etched selective to nitride 31 in order to recess oxide 40 below the lower level of nitride 31 to expose the silicon of PWell 23. For example, an etch using C4F6, at flow rate of 8 sccm and temperature of 70° C. for a time period of approximately 20 seconds will recess oxide 40 to leave approximately 2000 Angstroms of oxide 40. Photoresist 51 is then stripped.
  • Referring now to FIG. 6, selective epitaxial silicon (epi) is deposited to form epi silicon structures 60. A silicon epi deposition to form silicon structures 60 may be accomplished by decomposing DCS (Si2H2Cl2) in an H2 and HCl environment at 800 to 1000° C. A preferred silicon epi thickness is 500 to 1500 Angstroms.
  • After selective epi silicon deposition, amorphous silicon 61 is deposited to cover exposed oxide regions 40, epi silicon structures 60 and exposed nitride 31. An amorphous silicon deposition to form amorphous silicon layer 61 may be accomplished by decomposing SiH4 at approximately 500° C. A preferred amorphous silicon thickness is 2000 to 3000 Angstroms.
  • Referring now to FIG. 7, amorphous silicon 61 and epi silicon structures 60 are preferably planarized back to nitride 31 (seen in FIG. 5), such as using chemical mechanical Planarization (CMP). Planarized amorphous silicon 61 and planarized epi silicon structures 60 will become the source drain regions of the SDOI transistor structure following a subsequent source-drain implant. Next, nitride 31 is removed, such as by using a 125-150° C. phosphorus acid etch to remove the nitride selective to silicon and oxide, to expose the underlying silicon of PWell 23.
  • Next, photoresist 70 is placed and patterned to allow for a following n-depletion layer implant to form n-depletion layer 71 at the base of and extending between oxide regions 40. N-depletion layer 71 serves an important function in this exemplary embodiment of the present invention as it provides electrical isolation between the transistor body (resident in PWell 23) and p-region 72. P-region 72 will function as the channel for the SDOI transistor structure.
  • N-depletion layer 71 functions properly when the depth of the n-depletion is such that it completely spans between laterally spaced oxide regions 40 and yet is sufficiently deep to avoid hindering proper operation of an overlying channel region. As an example of a preferred implementation of the present invention, performing an n-depletion implant into PWell 23, with oxide regions 40 having a thickness of approximately 2800 Angstroms, a Phosphorus implant dose of approximately 5×1011 to 1×1012 Atoms/cm2, with an implant energy of approximately 180 KeV, will obtain the desired implant depth for the n-type depletion layer 71. In order to maintain an effective n-depletion layer 71, the thickness of oxide regions 40 should be in the order of 2500 Angstroms or greater.
  • The body to channel isolation provided by n-type depletion layer 71 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient. The improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the depletion layer. The method is not dependent on channel length or the desired threshold voltage (VT) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust VT although if so desired, one may be performed without altering the effectiveness of n-depletion 71 spanning between the bottoms of the shallow trench isolation 40.
  • Referring now to FIG. 8, a conductive material, such as metal, conductive polysilicon or metal silicide, is formed, patterned and etched to form transistor gate 81 and an underlying gate oxide 80, by means known to those skilled in the art. Once gate 81 is formed and source-drain extension implant, such as an Arsenic (As) implant, to form an n-channel transistor, is performed to form source-drain extension regions 82 that are self-aligned to gate 81. One implant example is an As implant dose of approximately 2×1014 Atoms/cm2, with an implant energy of approximately 8 KeV. Because the As implant is very shallow, it will not connect to or alter the functionality of underlying n-depletion region 71.
  • Referring now to FIG. 9, transistor gate spacers 90 are formed followed by a source-drain implant, such as an Arsenic (As) implant dose of approximately 2×1015 Atoms/cm2, with an implant energy of approximately 15 KeV, to form source-drain regions (electrodes) 91 to complete the formation of a Source-Drain On Insulator (SDOI) transistor structure of the present invention. Fabrication methods known to those skilled in the art are then used to complete the processing of the semiconductor device.
  • FIG. 10 depicts an overhead view of a completed Source-Drain On Insulator (SDOI) transistor structure as described in the process steps taken in FIG. 2-9. As shown in FIG. 10, underlying substrate 20 (not seen) has been implanted with conductive dopants to form PWell 23. Source/drain regions 91 are implanted into PWell 23 and the underlying channel region 72 is shown with dashed lines and underlies SDOI transistor gate 81. The sidewalls of SDOI transistor gate 81 are isolated by insulation spacers 90.
  • A second exemplary fabrication of an embodiment of the present invention is depicted in FIGS. 2-6 and FIGS. 11-13. This embodiment covers the case for selecting a p-type silicon substrate 20. In FIG. 2, an NWell implant is performed, such as an Arsenic or Phosphorus implant, to form NWell 23 into silicon substrate 20. An example of the NWell implant comprises a phosphorous implant of approximately 3×1012 Atoms/cm2; with an implant energy of approximately 150 KeV followed by a phosphorous implant of approximately 5×1012 Atoms/cm2, with an implant energy of approximately 360 KeV. In the case for selecting an n-type substrate the NWell implant does not need to be performed as will be discussed further in this embodiment.
  • The process steps depicted in FIGS. 3-6 for the first exemplary implementation of the present invention are repeated in this second exemplary implementation of the present invention to develop the structure as depicted in FIG. 6. The process then continues with the process steps depicted in FIGS. 11-13 as follows.
  • Referring now to FIG. 11, amorphous silicon 61 and epi silicon structures 60 are preferably planarized back to nitride 30 (seen in FIG. 6), such as using chemical mechanical Planarization (CMP). Planarized amorphous silicon 61 and planarized epi silicon structures 60 will become the source drain regions of the SDOI transistor structure following a subsequent source-drain implant. Next, nitride 30 is removed, such as by using a 125-150° C. phosphorus acid etch to remove the nitride selective to silicon and oxide, to expose the underlying silicon of NWell 23. Next, photoresist 110 is placed and patterned to allow for a following PWell implant that forms p-n junction 111 at the base of and extending between laterally spaced oxide regions 40. P-n junction 111 serves an important function in this exemplary embodiment of the present invention as it provides electrical isolation between the transistor body (resident in NWell 23) and PWell region 112. PWell region 112 will function as a channel for the SDOI transistor structure.
  • The p-n junction functions properly when the depth of p-n junction 111 is such that it completely spans between laterally spaced oxide regions 40 and is also sufficiently deep to avoid hindering proper operation of an overlying channel region. For example, with oxide regions 40 having a thickness of approximately 2800 Angstroms, performing a PWell implant into NWell 23 requires a Boron implant dose of approximately 5×1012 Atoms/cm2, with an implant energy of approximately 30 KeV.
  • In the case of an n-type silicon substrate being selected (the NWell implant is not preformed), once the PWell implant is performed a p-n junction will be formed at the base of and extending between laterally spaced oxide regions 40. The desired effect of the p-n junction is attained and the NWell implant is not necessary (though it may be implemented if so desired).
  • The body to channel isolation provided by p-n junction 111 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient. The improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the p-n junction. The method is not dependent on channel length or the desired threshold voltage (VT) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust VT, although if so desired, one may be performed without altering the effectiveness of p-n junction 111 spanning between the bottoms of the laterally spaced shallow trench isolation regions (oxide regions 40).
  • Referring now to FIG. 12, a conductive material, such as metal, conductive polysilicon and metal silicide, is formed, patterned and etched to form transistor gate 121 and underlying gate oxide 120, by means known to those skilled in the art. Once gate 121 is formed and source-drain extension implant, such as an Arsenic (As) implant to form an n-channel transistor, is performed to form source-drain extension regions 122 that are self-aligned to gate 121. One implant example is an As implant dose of approximately 2×1014 Atoms/cm2, with an implant energy of approximately 10 KeV. Because the As implant is very shallow it will not connect to or alter the functionality of underlying p-n junction 111 spanning between the bottom of the shallow trench isolation regions (oxide regions 40).
  • Referring now to FIG. 13, transistor gate spacers 130 are formed followed by a source-drain implant, such as an Arsenic (As) implant dose of approximately 2×1015 Atoms/cm2, with an implant energy of approximately 15 KeV, to form source-drain regions (electrodes) 131 to complete the formation of a Source-Drain On Insulator (SDOI) transistor structure of the present invention. Fabrication methods known to those skilled in the art are then used to complete the processing of the semiconductor device.
  • FIG. 14 depicts an overhead view of a completed Source-Drain On Insulator (SDOI) transistor structure as described in the process steps taken in FIG. 2-6 and 11-13. As shown in FIG. 14, underlying substrate 20 (not seen) has been implanted with conductive dopants to form PWell 23. Source/drain regions 131 are implanted into PWell 23 and the underlying channel region 112 is shown with dashed lines and underlies SDOI transistor gate 121. The sidewalls of SDOI transistor gate 121 are isolated by insulation spacers 130.
  • The exemplary embodiments have been discussed in reference to forming n-channel SDOI transistor structures. However, these concepts, taught in the exemplary embodiments, may be utilized by one of ordinary skill in the art to form p-channel SDOI transistor structures as well, by simply replacing the implants with the proper type of doping implant. For example, in exemplary embodiment of FIGS. 2-6 and 11-13, the NWell implant demonstrated for FIG. 2 would be replaced with a PWell implant, the PWell implant demonstrated for FIG. 11 would be replaced with an NWell implant and the n-type source-drain implant demonstrated for FIG. 12 would be replaced with a p-type source-drain implant.
  • The completed SDOI transistor structure and the fabrication method used therefor may be for various types of devices, such as embedded memory devices, and may be used in numerous semiconductor applications and particularly in, but not limited to, DRAMs. For example, the present invention may be applied to a semiconductor system, such as the one depicted in FIG. 15, the general operation of which is known to one skilled in the art.
  • FIG. 15 represents a general block diagram of a semiconductor system comprising a processor 150 and a memory device 151 showing the basic sections of a memory integrated circuit, such as row and column address buffers, 153 and 154, row and column decoders, 155 and 156, sense amplifiers 157, memory array 158 and data input/output 159, which are manipulated by control/timing signals from the processor through control 152.
  • It is to be understood that, although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the disclosed structure and process herein without departing from the invention as recited in the several claims appended hereto.

Claims (14)

1. A transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
2. The transistor structure of claim 1, wherein the transistor structure comprises a p-channel transistor with the conductive depletion region having a p-type conductivity.
3. The transistor structure of claim 1, wherein the transistor structure comprises an n-channel transistor with the conductive depletion region having an n-type conductivity.
4. A transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
5. The transistor structure of claim 4, wherein the transistor structure comprises a p-channel transistor.
6. The transistor structure of claim 4, wherein the transistor structure comprises an n-channel transistor.
7. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
8. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising an n-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
9. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
10. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
11. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that an transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
a boron doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
12. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
an arsenic or phosphorus doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
13. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
14. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
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