GB2365214A - CMOS integrated circuit devices and substrates having buried silicon germanium layers - Google Patents
CMOS integrated circuit devices and substrates having buried silicon germanium layers Download PDFInfo
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- GB2365214A GB2365214A GB0100209A GB0100209A GB2365214A GB 2365214 A GB2365214 A GB 2365214A GB 0100209 A GB0100209 A GB 0100209A GB 0100209 A GB0100209 A GB 0100209A GB 2365214 A GB2365214 A GB 2365214A
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- sil
- silicon
- active layer
- silicon active
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- 239000000758 substrate Substances 0.000 title claims abstract description 133
- 229910000577 Silicon-germanium Inorganic materials 0.000 title description 16
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 190
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 188
- 239000010703 silicon Substances 0.000 claims abstract description 188
- 238000000034 method Methods 0.000 claims abstract description 65
- 230000005669 field effect Effects 0.000 claims abstract description 20
- 239000012212 insulator Substances 0.000 claims abstract description 20
- 230000007423 decrease Effects 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 453
- 239000002019 doping agent Substances 0.000 claims description 89
- 239000007943 implant Substances 0.000 claims description 45
- 229910052739 hydrogen Inorganic materials 0.000 claims description 24
- 239000001257 hydrogen Substances 0.000 claims description 24
- 229910052785 arsenic Inorganic materials 0.000 claims description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 17
- 229910021426 porous silicon Inorganic materials 0.000 claims description 17
- 239000002131 composite material Substances 0.000 claims description 16
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 15
- -1 hydrogen ions Chemical class 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 210000000746 body region Anatomy 0.000 description 8
- 101000767534 Arabidopsis thaliana Chorismate mutase 2 Proteins 0.000 description 7
- 101000986989 Naja kaouthia Acidic phospholipase A2 CM-II Proteins 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000012407 engineering method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008521 reorganization Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66916—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
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- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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Abstract
A semiconductor-on-insulator (SOI) field effect transistor (FET) includes an electrically insulating layer (30), a Si<SB>1-x</SB>Ge<SB>x</SB> layer (34) and an unstrained silicon active layer (36) with an insulated gate electrode (40,42) on the surface of the unstrained silicon active layer (36). The Si<SB>1-x</SB>Ge<SB>x</SB> layer (34) forms a junction with the unstrained active layer (36) and has a graded concentration of Ge which decreases monotonically in a direction extending towards the surface of the unstrained silicon active layer (36). The peak Ge concentration may be in the range 0.2 & x & 0.4, with x=0 at the junction with the unstrained active layer (36). The unstrained active layer (36) may have thickness greater than 600Ñ and the Si<SB>1-x</SB>Ge<SB>x</SB> layer (34) may have thickness less than 800Ñ. The FET may be an NMOS or PMOS structure with lightly doped source (44a) and drain (44b) regions. A method of forming a semiconductor substrate is also disclosed where a handling substrate (10, Fig. 3A) is formed having silicon epilayer and Si<SB>1-x</SB>Ge<SB>x</SB> layer (16,18, Fig. 3B), and then the handling substrate is bonded to a supporting substrate (20, Fig. 3C) before the handling substrate is removed (Fig. 3E).
Description
2365214 CMOS INTEGRATED CIRCUIT DEVICES AND SUBSTRATES HAVING BURIED
SILICON GERMANIUM LAYERS THEREIN AND METHODS OF FORMING SAME The present invention relates to semiconductor devices and fabrication methods, and more particularly, to MOS-based semiconductor devices and substrates and methods of forming sarne.
Partial ly-depleted silicon-on-insulator (PDSOI) MOSFETs offer high speed and low power performance, but typically remain susceptible to parasitic floating body effects (FBE) which can seriously degrade device performance. Various techniques have been proposed for reducing FBE in SOI MOSFETs. One such technique includes using a narrow bandgap SiGe layer adjacent a source of an SOI NMOS field effect transistor. As will be understood by those skilled in the art, the use of a SiGe layer reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the body region by impact ionization can more readily flow into the source region through the path of the p-Si(body)/n+SiGe(source)ln+Si(source). This and other related techniques are disclosed in articles by J. Sim et al. entitled "Elimination of Parasitic BipolarInduced Breakdown Effects in Ultra-Thin SOI MOSFETs Using Narrow-BandgapSource (NBS) Structure," IEEE Trans. Elec. Dev., Vol. 42, No. 8, pp. 1495-1502, August (1995) and M. Yoshimi et al. entitled "Suppression of the Floating-Body Effect in SO[ MOSFETs by the Bandgap Engineering Method Using a Sil-XGex Source Structure," IEEE Trans. Elec. Dev., Vol. 44, No. 3, pp. 423-429, March (1997). U.S. Patent No. 5, 698,869 to Yoshimi et al. entitled 1nsulated-Gate Transistor Having Narrow-Bandgap-Source" also discloses the use of a narrow bandgap material within a source region of a MOSFET.
Techniques to reduce FBE and improve channel characteristics in MOSFETs are also described in U.S. Patent No. 5,891,769 to Liaw et al. entitled Vethod for Forming a Semiconductor Device Having a Heteroepitaxial Layer. " In particular, the '769 patent discloses the use of a strained channel region to enhance carrier mobility within MOSFETs. This strained channel region may be formed by growing a silicon layer on an as-grown relaxed or unstrained SiGe layer. U.S. Patent No. 5,963,817 to Chu et al. entitled "Bulk and Strained Silicon on Insulator Using Selective Oxidation," also discloses the use of SiGe layers, which selectively oxidize at faster rates relative to silicon, to improve FBE. Furthermore, U.S. Patent Nos. 5,906,951 and 6,059,895 to Chu et al. disclose wafer bonding techniques and strained SiGe layers to provide SO1 substrates. The use of wafer bonding techniques and SiGe layers to provide SOI substrates are also described in U.S. Patent Nos. 5,218,213 and 5,240,876 to Gaul et al. Conventional techniques for forming SOI substrates are also illustrated by FIGS. 1 A-1 D and 2A-2D. In particular, FIG. 1A illustrates the formation of a handling substrate having a porous silicon layer therein and an epitaxial silicon layer thereon and FIG. 1 B illustrates the bonding of a supporting substrate to a surface of the epitaxial silicon layer. The supporting substrate may include an oxide layer thereon which is bonded directly to the epitaxial silicon layer using conventional techniques. As illustrated by FIG. 1 C, a portion of the handling substrate is then removed to expose the porous silicon layer. This removal step may be performed by grinding or etching away a portion of the handling substrate or splitting the porous silicon layer. As illustrated by FIG. 1 D, a conventional planarization technique may then be performed to remove the porous silicon layer and provide an SOI substrate having a polished silicon layer thereon and a buried oxide layer therein. The conventional technique illustrated by FIGS. 1AAD is commonly referred to as an epi-layer transfer (ELTRAN) technique. FIG. 2A illustrates a step of forming a handling substrate having a silicon layer thereon by implanting hydrogen ions into a surface of the substrate to define a buried hydrogen implant layer therein. Then, as illustrated by FIG. 2B, a supporting substrate is bonded to the handling substrate. A portion of the handling substrate is then removed by splitting the bonded substrate along the hydrogen implant layer, as illustrated by FIG. 2C. A conventional planarization technique may then be performed to remove the hydrogen implant layer, as illustrated by FIG. 21). The conventional technique illustrated by FIGS. 2A-21D is commonly referred to as a "smart-cut" technique.
Unfortunately, although the use of strained silicon channel regions may enhance carrier mobility in both NMOS and PMOS devices, such strained regions typically degrade short channel device characteristics. Thus, notwithstanding the above-described techniques for forming MOSFETs and SOl substrates, there continues to be a need for improved methods of forming these structures that do not require the use of strained channel regions to obtain enhanced channel mobility characteristics, and structures formed thereby.
Summary of the Invention
Embodiments of the present invention include semiconductor-on-insulator (S01) substrates having buried Si,,Ge, layers therein. A SOI substrate according to one embodiment of the present invention comprises a silicon wafer having an electrically insulating layer thereon and a Sil_.Ge,, layer having a graded concentration of Ge therein extending on the electrically insulating layer. An unstrained silicon active layer is also provided in the SOI substrate. This unstrained silicon active layer extends on the Sil-xGex layer and forms a junction therewith. The unstrained silicon active layer also preferably extends to a surface of the SOI substrate, so that integrated circuit devices may be formed at the surface of the silicon active layer. To facilitate the use of relatively thin silicon active layers, the Si,. XGex layer is preferably epitaxially grown from the unstrained silicon active layer. This epitaxial growth step may include providing an unstrained silicon active layer (or initially epitaxially growing an unstrained silicon active layer on a substrate) and then continuing growth of a Sil-xGex layer on the active layer by increasing the concentration of Ge in a graded manner until a maximum desired Ge concentration is obtained. Further growth may then occur by reducing the concentration of Ge in a graded manner back to x=0. The grading of Ge in the Sil,Gex layer may constitute a linear grading.
The preferred SOI substrates may be fabricated by initially forming a handling substrate having an unstrained silicon layer therein and a Sil, Ge,' layer extending on the silicon layer. A supporting substrate is then bonded to the handing substrate so that the Sil-,Gex layer is disposed between the supporting substrate and the unstrained silicon layer. A portion of the handling substrate is then preferably removed from the supporting substrate to expose a surface of the silicon layer and define a semiconductor-on-insulator substrate having a buried Sil,,Gex layer therein. Here, the buried Sil,Gex layer preferably has a graded concentration of Ge therein with a profile that decreases in a direction that extends from the supporting substrate to the surface of the silicon layer.
These methods may also include forming a handling substrate having an unstrained first silicon layer therein, a Sil,Gex layer extending on the first silicon layer and an unstrained or strained second silicon layer extending on the Sil,Gex layer. The bonding step may also be preceded by the step of thermally oxidizing the second silicon layer to define a thermal oxide layer on the Sil,Ge, The supporting substrate may also comprise an oxide surface layer thereon and the bonding step may comprise bonding the oxide surface layer to the thermal oxide layer. Alternatively, the bonding step may be preceded by the step of depositing an electrically insulating layer on the Sil-xGe., layer and the bonding step may comprise bonding the oxide surface layer to the electrically insulating layer.
According to still another preferred method of forming a SO] substrate, the handling substrate may comprise a porous silicon layer therein and the removing step may comprise removing a portion of the handling substrate from the supporting substrate by splitting the porous silicon layer and then planarizing the porous silicon layer and the silicon layer in sequence. Preferred methods of forming handling substrates may also comprise epitaxially growing a Sil,Gex layer on a silicon layer and then implanting hydrogen ions through the Sil,Gex layer and the silicon layer to define a hydrogen implant layer in the handling substrate. The removing step may then be performed by splitting the hydrogen implant layer and then planarizing the hydrogen implant layer to expose a surface of the silicon layer. Semiconductor devices, including field effect transistors, may then be formed at this surface of the silicon layer.
An additional embodiment of the present invention includes semiconductoron-insulator field effect transistors. Such transistors may comprise an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si,,,Ge,, layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Sil,,Ge.' layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. According to one aspect of this embodiment, the peak Ge concentration level is greater than x=0. 15 and the concentration of Ge in the Sil-,Ge, layer varies from the peak level to a level less than about x=0. 1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Sil-,,Gex layer varies from the peak level where 0.2<x<0.4 to a level where x=0 at the first junction.
The Sil,Ge, layer may also define an interface with the underlying electrically insulating layer and the graded concentration of Ge in the Sil-xGex layer may increase from a level less than about x=0.1 at the interface with the electrically insulating layer to the peak level. The unstrained silicon active layer may also have a thickness of greater than about 600A and the Sil-xGex layer may have a thickness of less than about 800A.
Higher drive current capability in PMOS transistors may also be achieved by reorganizing the dopant profiles in the channel region and in the body region. In particular, the different solubility of certain dopants in Si and Sil-xGex can be used advantageously to improve PMOS device characteristics. In a preferred PMOS transistor, the Sil-xGex layer is doped with an N-type dopant and the concentration of the N-type dopant in the Sil,,Gex layer has a profile that decreases in the first direction towards the surface of the unstrained silicon active layer. This profile preferably has a peak level within the Sil-xGe,, layer and may decrease in the first direction and in a monotonic manner so that a continuously retrograded N- type dopant profile extends across the unstrained silicon active layer. This N-type dopant is preferably used to suppress punch-through in the body region, but may also be used to influence the threshold voltage of the PMOS transistor.
Additional semiconductor-on-insulator field effect transistors may also comprise an electrically insulating layer and a composite semiconductor active region on the electrically insulating layer. This composite semiconductor active region comprises a silicon active layer having a thickness greater than about 600 A0 and a single Sil-xGex layer disposed between the electrically insulating layer and the silicon active layer. The Sil,Gex layer forms a first junction with the silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards a surface of the silicon active layer. An insulated gate electrode is also provided on the surface. The peak level of Ge in the Sil-xGex layer is preferably greater than x=0. 15 and the concentration of Ge in the Si,,Ge. layer varies from the peak level to a level less than about x=0. 1 at the first junction. More preferably, the concentration of Ge in the Sil-xGex layer varies from the peak level where 0.2<x<0.4 to a level where x=0 at the first junction. The Sil-xGe,, layer may also define an interface with the electrically insulating layer and the graded concentration of Ge in the Sil,Gex layer also increases from a level less than about x=0. 1 at the interface to the peak level.
A further embodiment of the present invention comprises a PMOS field effect transistor having a composite semiconductor active region therein that extends on an electrically insulating layer. This composite semiconductor active region comprises a single Sil,Gex layer having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level within the single Sil-xGex layer towards a surface thereof. An unstrained silicon active layer is also provided that extends from a first junction with the single Sil,Gex layer to the surface. The composite semiconductor active region also has an at least substantially retrograded N-type dopant profile therein that extends to the surface and has a peak level in the single Sil,Gex layer. The total charge provided by this N-type dopant influences the threshold voltage of the PMOS transistor. The N-type dopant in the single Sil,Ge, layer also significantly inhibits punch- through caused by depletion layers that may extend between the source and drain regions. Lightly doped P-type source and drain regions are also preferably provided. These regions extend in the silicon active layer and opposite the insulated gate electrode. A source-side pocket implant region of N-type conductivity is also provided and this pocket implant region extends between the lightly doped P-type source region and the single Sil-,,Gex layer. This pocket implant region forms rectifying and nonrectifying junctions with the source region and the single Sil-xGex layer, respectively, and operates to suppress junction leakage.
A still further embodiment of a semiconductor-on-insulator field effect transistor comprises a bulk silicon region and an electrically insulating layer on the bulk silicon region. An unstrained silicon active layer having a first thickness is also provided on the electrically insulating layer and an insulated gate electrode with sidewall insulating spacers is formed on a surface of the unstrained silicon active layer. A Sil,Ge, layer of first conductivity type is disposed between the electrically insulating layer and the unstrained silicon active layer. In particular, the Sil-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface. Lightly doped source and drain regions of second conductivity type are also provided. These lightly doped regions extend in the unstrained silicon active layer, but to a depth less than the thickness of the unstrained silicon active layer. In addition, a source- side pocket implant region of first conductivity type is provided in the unstrained silicon active layer, and this source-side pocket implant region extends between the lightly doped source region and the Sil,Ge,, layer. According to a preferred aspect of this embodiment, the SilXGex layer has a retrograded first conductivity type doping profile therein relative to the surface. This retrograded first conductivity type doping profile may be a retrograded arsenic (or arsenic/phosphorus) doping profile and may result in the SilXGex layer having a greater concentration of first conductivity type dopants therein relative to the maximum concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. In particular, the retrograded dopant profile has a peak in the Sil,Ge. layer and a minimum underneath the gate electrode. This retrograded profile preferably decreases monotonically from the peak level to the minimum level, however, other retrograded profiles may also be achieved. The thickness of the unstrained silicon active layer and the total amount of dopants in the channel region and underlying Sil_.Ge, layer can also be carefully controlled to achieve a desired threshold voltage and inhibit punch-through.
Embodiments of the present invention also include methods of forming field effect transistors by forming an insulated gate electrode on a surface of a semiconductor-on-insulator substrate. This substrate includes an electrically insulating layer, an unstrained silicon active layer on the electrically insulating layer and a Sil-,Ge, epitaxial layer having a graded concentration of Ge therein disposed between the electrically insulating layer and the unstrained silicon active layer. Steps are also performed to form source and drain regions of first conductivity type in the unstrained silicon active layer and also form source-side and drain-side pocket implant regions of second conductivity type that extend in the unstrained silicon active layer and in the Sil, Gex epitaxial layer. These pocket implant regions form respective P-N junctions with the source and drain regions. The step of forming an insulated gate electrode is preferably preceded by the step of implanting threshold voltage control dopants of first conductivity type into the unstrained silicon active layer. These threshold voltage control dopants may then be annealed and redistributed as a result of different dopant solubility in Si and Si,,Ge, after the insulated gate electrode has been formed, to establish a retrograded profile of threshold voltage control dopants in the Sil,Gex epitaxial layer and silicon active layer. The dopants in the Sil,Ge, epitaxial layer also inhibit punch-through in PMOS devices and reduce floating body effects in NMOS devices.
The substrates and forming methods of the present invention can be utilized to form NMOS transistors having reduced floating body effects (FBE). The reduction in FBE occurs because the buried SiGe layer, having a graded Ge concentration therein, reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the body region by impact ionization can more readily flow into the source region through the path of the p-Si(body)1p- S i Ge(body)1n+S i Ge(so urce)ln +S i (source). NMOS transistors having well controlled kink effect characteristics and ld v. Vg curves having evenly distributed subthreshold slope with respect to Vds can also be formed. The substrates and forming methods of the present invention can also be utilized to provide PMOS transistors having excellent drive capability resulting from higher inversion-layer carrier mobility in the channel regions. This improved drive capability is achieved by reorganizing the channel region dopants through annealing so that a retrograded dopant profile and a desired threshold voltage are simultaneously achieved. This reorganization of the channel region dopants can also be used to enhance pocket ion implantation efficiency. The threshold voltage roll-off characteristics of these NMOS and PMOS devices can also demonstrate reduced short channel effects (RSCE), and the suppressed parasitic bipolar action (PBA) in the devices can be used to reduce offleakage current.
Brief Description of the Drawings
The above objectives and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
FIGS. 1 A-1 D are cross-sectional views of intermediate structures that illustrate conventional methods of forming semi conductor-on-ins ulator (S01) substrates.
FIGS. 2A-21) are cross-sectional views of intermediate structures that illustrate conventional methods of forming SO1 substrates.
FIGS. M-31E are cross-sectional views of intermediate structures that illustrate methods of forming SO1 substrates having SiGe layers therein according to an embodiment of the present invention.
FIGS. 4AA1E are cross-sectional views of intermediate structures that illustrate methods of forming SOI substrates having SiGe layers therein according to an embodiment of the present invention.
FIG. 5 is a flow-diagram of process steps that illustrates preferred methods of forming S01-based field effect transistors according to an embodiment of the present invention.
FIGS. 6A-61E are cross-sectional views of intermediate structures that illustrate methods of forming SOl-based MOS transistors according to an embodiment of the present invention.
FIG. 7A is a graph of N-type dopant concentration versus substrate depth for a conventional SO] substrate prior to anneal. The illustrated phosphorus and arsenic dopants were implanted at energies of 30 KeV and 200 KeV, respectively.
FIG. 713 is a graph of N-type dopant concentration versus substrate depth for a conventional SOI substrate after anneal. The pre-anneal dopant profiles are illustrated by FIG. 7A.
FIG. 7C is a graph of N-type dopant concentration versus substrate depth for a preferred SOI substrate having a SiGe layer inserted therein. The illustrated phosphorus and arsenic dopants were implanted at energies of 30 KeV and 200 KeV, respectively.
FIG. 7D is a graph of N-type dopant concentration versus substrate depth for a preferred SOI substrate having a SiGe layer inserted therein, after anneal. The pre-anneal dopant profiles are illustrated by FIG. 7C.
Description of Preferred Embodiments
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Moreover, the terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types such as N or P-type, however, each embodiment described and illustrated herein includes its complementary embodiment as well. Like numbers refer to like elements throughout.
Referring now to FIGS. 3A-31E, preferred methods of forming semiconductoron-insulator (S01) substrates having Si,,Ge, layers therein will be described. As illustrated by FIG. 3A, an illustrated method includes forming a handling substrate 10 having a porous silicon layer 12 therein and a first epitaxial silicon layer 14 (Si-epi) extending on the porous silicon layer 12. This first epitaxial silicon layer 14 may have a thickness of greater than about 600A. As illustrated by FIG. 3B, a Sil, Gex layer 16 is then formed on the first epitaxial silicon layer 14. This Sil,Gex layer 16 may have a thickness of less than about 800 A and may be formed using a low pressure chemical vapor deposition technique (I-PCVD) that is performed at a temperature in a range between about 7000C and 13000C. This deposition step may be performed by exposing a surface of the first epitaxial silicon layer 14 to a deposition gas comprising a mixture of GeH4and SH2C12source gases. In particular, the deposition step is preferably performed by varying the relative concentration of the germanium source gas (e.g., GeH4) in-situ. For example, the flow rate of the germanium source gas is preferably varied so that the concentration of Ge within the Sil,Gex layer 16 is increased from a value of x=0.0 at the junction with the underlying first epitaxial silicon layer 14 to a maximum value of 0.2:5x:!0.4 therein. After the maximum concentration level is reached, the flow rate of the germanium source gas may be gradually reduced until the concentration of Ge in the Sil,Ge, layer 16 is reduced to zero.
Referring still to FIG. 313, a second epitaxial silicon layer 18 may then be formed on the Sil-xGex layer 16 by continuing the deposition step using a source gas of Sil-12C12at a temperature of about 850"C. This step of forming a second epitaxial silicon layer 18 is optional.
Referring now to FIG. 3C, a supporting substrate 20 is then preferably bonded to the second epitaxial silicon layer 18. As illustrated, this bonding step is preferably performed between an oxide layer 22 residing on the supporting substrate 20 and a polished surface of the second epitaxial silicon layer 18. The oxide layer 22 may have a thickness in a range between about 800-3000A. Then, as illustrated by FIG. 3D, the handling substrate 10 is removed from the composite substrate by splitting the composite substrate along the porous silicon layer 12. Conventional techniques may then be used to remove remaining portions of the porous silicon layer 12 from the composite substrate. As illustrated by FIG. 3E, this removal step may comprise removing the porous silicon layer 12 using a planarization or polishing technique that exposes a primary surface 14a of the first epitaxial silicon layer 14. As described more fully hereinbelow, active devices (e.g., CMOS devices) having preferred electrical characteristics may be formed in the first "unstrained" epitaxial silicon layer 14.
FIGS. 4A-41E illustrate alternative methods of forming semi conductoroninsulator (S01) substrates having Sil,Gex layers therein. As illustrated by FIG. 4A, an illustrated method includes forming a handling substrate 10' having a Sil,Gex layer 16'thereon and a second epitaxial silicon layer 18' on the Sil,Gex layer 1V. The Sil,Gex layer 16' may be formed as described above with respect to FIG. 3B. A blanket implantation step is then performed, as illustrated by FIG. 4B. This implantation step may include implanting hydrogen ions through the second epitaxial silicon layer 18' and into the handling substrate 10', to define a hydrogen implant layer 15. The hydrogen ions are preferably implanted at a sufficient energy level to define a first silicon layer 14' between the hydrogen implant layer 15 and the Sil,Gex layer 1C. For example, the hydrogen ions may be implanted at a dose level of 1X1016_1X1017 cm-2and at an energy level of about 150-400 KeV. Referring now to FIG. 4C, a supporting substrate 20 is then preferably bonded to the second epitaxial silicon layer 18'. As illustrated, this bonding step is preferably performed between an oxide layer 22 residing on the supporting substrate 20 and a polished surface of the second epitaxial silicon layer 18'. Then, as illustrated by FIG. 4D, the handling substrate 10' is removed from the composite substrate by splitting the composite substrate along the hydrogen implant layer 15. Conventional techniques may then be used to remove remaining portions of the hydrogen implant layer 15 from the composite substrate.
As illustrated by FIG. 4E, this removal step may comprise removing the hydrogen implant layer 15 using a planarization or polishing technique that exposes a primary surface of the first silicon layer W. According to still further embodiments of the present invention, the second epitaxial silicon layer 18 of FIG. 3C and the second epitaxial silicon layer 18' of FIG. 4C may be thermally oxidized before the bonding step is performed. Alternatively, prior to the bonding step, an electrically insulating layer may be deposited on the second epitaxial silicon layers 18 and 18', or on the Sil_.Gex layers 16 and 16' in the event the second epitaxial silicon layers 18 and 18'are not present. The thickness of the Sil,Ge, layers16'and 16' may also be increased in the event these layers are partially thermally oxidized in preparation for the bonding step. The thicknesses of the second epitaxial silicon layers 18 and 18' may be set at levels in a range between about 200-400A.
Alternatively, the Sil,Ge, layers 16 and 16' may be formed as, layers having a graded concentration of Ge therein that reaches a maximum level of about 30 percent. These layers may be formed at a temperature in a range between 700OC8000C and at a pressure of about 20 Torr. The source gases may include Gel-14, (0_ 60 sccm), DCS (SiH2C'2) at 200 sccm and HCI at 50-100 sccm. 19 Referring now to FIG. 5, preferred methods 100 of forming field effect transistors (e.g., MOSFETs) in SOI substrates will be described. As described above with respect to FIGS. 3A-31E and 4A-41E, these methods include forming an SO] substrate having an unstrained silicon active layer and a buried Si,,Ge, layer therein, Block 102. The buried Sil,Ge. layer is preferably epitaxially grown from the unstrained silicon active layer while the concentration of Ge therein is increased from a level where initially x=0 to a peak level where 0.2:5x:50.4. Thus, the concentration of Ge in the buried Sil,,Gex layer has a profile that preferably decreases in a direction extending from a peak level therein towards a primary surface of the unstrained silicon active layer (i.e., upper surface of the SOI substrate). Dopants for adjusting threshold voltage are then implanted into the substrate, Block 104. The 1hreshold voltage" dopants used in NMOS and PMOS transistors may be separately implanted into the substrate using respective NMOS and PMOS implant masks. For NMOS transistors, the threshold voltage dopants typically comprise Ptype dopants such as boron (B) and indium (in). However, for PMOS transistors, the threshold voltage dopants typically comprise N-type dopants such as arsenic (As) and phosphorus (P).
The steps of implanting threshold voltage dopants may include implanting multiple different dopants of same conductivity type. For example, in PMOS devices, both As and P dopants may be implanted as threshold voltage dopants at respective energy levels and dose levels. These multiple dopants may have different dopant solubilities within silicon and silicon germanium and these different solubilities may be used advantageously to achieve a preferred redistribution of the threshold voltage dopants when subsequent thermal annealing steps are performed. This preferred redistribution may result in a retrograded profile of the threshold voltage dopants. In particular, the preferred redistribution of dopants may improve the inversion-layer channel characteristics of the resulting transistors by inhibiting a reduction in channel mobility that typically occurs when threshold voltage dopants are introduced into the channel regions of the transistors. This is particularly advantageous for PMOS devices which typically suffer from relatively low hole mobility in the inversion-layer channel. The thickness of the silicon active layer and underlying Sil_.,Ge, layer may also be designed to enhance the degree of preferred redistribution of the threshold voltage dopants while simultaneously insuring that the total dopant charge influences the resulting threshold voltage. The dopants used to influence threshold voltage in PMOS devices may also be used advantageously to inhibit punchthrough.
Referring now to Block 106, an insulated gate electrode may then be formed on the substrate using conventional techniques. As illustrated by Block 108, this insulated gate electrode is then used as a mask during the implantation of lightly doped source (LDS) and lightly doped drain (LDD) dopants into the unstrained silicon active layer. Pocket implant regions may then be formed by implanting pocket region dopants into the unstrained silicon active layer and underlying Si,_.Ge,' layer, Block 110. These pocket region dopants are preferably implanted at a sufficient dose level and energy level to result in the formation of pocket implant regions that extend between the LDS and I-DD regions and the underlying Sil-xGex layer. As illustrated by Block 112, conventional techniques may then be used to define electrically insulating spacers on the sidewalls of the gate electrode. Highly doped source and drain region dopants may then be implanted into and through the LDS and I-DD regions, using the gate electrode and sidewall insulating spacers as an implant mask, Block 114. As illustrated by Block 116, a rapid thermal annealing (RTA) step may then be performed to drive-in the source and drain region dopants. During this annealing step, previously implanted dopants may also be diffused and redistributed within the silicon active layer and underlying Sil,,Ge,' layer.
Referring now to FIGS. 6A-61E, preferred methods of forming SOI field effect transistors include forming a substrate having an unstrained silicon active layer 36 thereon and a buried Sil,Ge, layer 34 therein. As illustrated by FIG. 6A, the unstrained silicon active layer 36 may have a thickness of greater than about 600A and the buried Sil,Ge, layer 34 may have a thickness of less than about 800A. Preferably, the unstrained silicon active layer 36 may have a thickness in a range between about 800A and 1200A and the buried Sil,Ge, layer 34 may have a thickness in a range between about 200A and 600 A. More preferably, the unstrained silicon active layer 36 may have a thickness of 1000A and the buried Si,_ XGex layer 34 may have a thickness of 400A. A relatively thin underlying layer 32 of strained or unstrained silicon having a thickness of about 300A may also be provided between the buried Sil,Gex layer 34 and a buried oxide layer 30. This underlying layer 32 may be omitted. The concentration of Ge in the buried Sil-,Gex layer 34 may be set to zero at the junction with the silicon active layer 36 and the underlying layer 32. The concentration of Ge in the buried Sil,Ge,, layer 34 may also be set at a peak level in a range between 0.2 and 0.4 and may be linearly graded relative to the peak level. The buried oxide layer 30 may be provided on a semiconductor substrate or wafer (not shown).
Referring now to FIG. 6B, threshold voltage control dopants 38 are then implanted into the unstrained silicon active layer 36. In the event both NMOS and PMOS devices are to be formed at adjacent locations within the silicon active layer 36, then separate NMOS and PMOS implantation masks (not shown) may be formed on the unstrained silicon active layer 36. These masks may be used when N-type dopants are implanted as threshold voltage control dopants for PMOS devices and when P-type dopants are implanted as threshold voltage control dopants for NMOS devices. The implanted dopants 38 may include boron (B) and indium (in) when forming NMOS devices and arsenic (As) and phosphorus (P) when forming PMOS devices. Other dopants may also be used. In particular, the illustrated implanting step may comprise two separate implant steps, First, threshold voltage control dopants such as 13F2 ions may be implanted at an energy level in a range between about 30-60 KeV, at a dose level in a range between about 8xl C cm-2 and 5xl 013 cm' and at a tilt angle of 00. Second, threshold voltage control dopants such as indium ions may also be implanted at a higher energy level in a range between about 150-250 KeV and at a dose level in a range between about 8xl C CM-2 and 5xl 013 CM-2. When forming PMOS devices, the illustrated implanting step may comprise separately implanting arsenic and phosphorous ions at sufficient dose and energy levels to achieve a desired retrograded dopant profile within the channel region and body region within the silicon active layer 36 and the underlying Sil.,Ge, layer 34. In particular, the first implant step may comprise implanting P ions at an energy level in a range between about 20-40 KeV, at a dose level in a range between about 8xl 01' CM-2 and 5xl 013 cm-2 and at a tilt angle of 70. Arsenic ions may then be implanted at a higher energy level in a range between about 150-250 KeV and at a dose level in a range between about 8xl 011 CM-2 and 5xl 011 cm-2. The arsenic ions may influence threshold voltage, but typically have a much stronger influence on device characteristics by inhibiting punch-through in the body region of the PMOS device.
Referring now to FIG. 6C, conventional techniques may then be used to define an insulated gate electrode on the primary surface of the silicon active layer 36. These techniques may include forming a thermal oxide layer 42 on the primary surface and depositing a doped or undoped polysilicon layer 40 on the thermal oxide layer 42. Conventional techniques may then be used to pattern the polysilicon layer and thermal oxide layer into an insulated gate electrode having exposed sidewalls. Techniques for forming insulated gate electrodes are more fully described in commonly assigned U.S. Patent Nos. 6,6064,092 to Park, entitled "SemiconductorOn-insulator Substrates Containing Electrically.. Insulating Mesas"; 5,998,840 to Kim, entitled "Semiconductor-On-lnsulator Field Effect Transistors With Reduced Floating Body Parasitics"; and 5, 877,046 to Yu et al., entitled 'Wethods of Forming
Semiconductor-on-lnsulator Substrates", the disclosures of which are hereby incorporated herein by reference. First source and drain region dopants 39 may then be implanted into the silicon active layer 36 to define lightly doped source (LDS) and drain (LDD) regions 44a and 44b. As illustrated, these dopants may implanted in a self-aligned manner using the insulated gate electrode as an implant mask. For a PMOS device, boron dopants (e.g., 13F2 ions) may be implanted at an energy level in a range between about 3-30 KeV and at a dose level in a range between about 1 xl 0" cm and 1 Xl 016 CM-2. Alternatively, for an NMOS device, arsenic dopants may be implanted at an energy level in a range between about 2050 KeV and at a dose level in a range between about 1 Xl 012 cm-2 and 1 Xl 016 CM-2. A relatively short duration annealing step may then be performed to laterally and vertically diffuse the I-DD and LDS dopants. Other dopants may also be used when forming the LDS and I-DD regions.
Referring now to FIG. 6D, pocket implant region dopants 46 may then be implanted at a tilt angle in a range between about 7 and 35 degrees, to define Ptype pocket implant regions 48a-b within an NMOS device or N-type pocket implant regions 48a-b within a PMOS device. This implant step is preferably performed at a sufficient energy level and dose level to penetrate beneath the I-DD and LDS regions 44a and 44b and into the buried Si,,Ge,, layer 34. In particular, the N-type pocket implant regions 48a-b may be formed by implanting arsenic ions at an energy level in a range between about 100 and 300 KeV and at a dose level in a range between about 1 Xl 012 cm' and 1 Xl 015 CM ' -2. The P-type pocket implant regions 48ab may also be formed by implanting boron ions at an energy level in a range between about 20 and 60 KeV and at a dose level in a range between about 1X1012 CM'2 and 1 xl 0' cm'.
Highly doped N-type source and drain regions 50a and 50b may then be formed by implanting arsenic ions 52 at an energy level in a range between about 20-60 KeV and at a dose level in a range between about 5xl 014 CM-2 and 1X1017 CM2. Alternatively, for a PMOS device, the highly doped P-type source and drain regions 50a and 50b may be formed by implanting 13F2 ions 52 at an energy level in a range between about 25-40 KeV and at a dose level in a range between about 1 Xl 014 CM-1 and 5xl 016 cm. A drive-in and activation step may then be performed by annealing the substrate using a rapid thermal annealing technique. The annealing step may be performed at a temperature in a range between 9000C and 10500C, for a duration in a range between 10-200 seconds.
Referring now to FIGS. 7A-71D, pre-anneal and post-anneal profiles of Ntype dopants in conventional SO1 substrates and SOI substrates having SiGe layers inserted therein will be described. In particular, FIG. 7A illustrates doping profiles for phosphorus (P) and arsenic (As) in a conventional SOI substrate having a buried oxide layer (BOX) extending therein between a silicon active layer (top-Si) and a silicon wafer (not shown). The illustrated phosphorus and arsenic dopants were implanted at energies of 30 KeV and 200 KeV, respectively. As illustrated by FIG. 7B, after performing a rapid thermal anneal (RTA) at a temperature of about 1 00M and a duration of about 30 seconds, the original gaussian- shaped doping profiles spread out and give rise to substantially uniform profiles. In contrast, the doping profiles illustrated by FIGS. 7C and 7C show that a retrograded As profile can be achieved in a SOI substrate having a buried Si,,Ge, layer therein formed in accordance with methods of the present invention. This retrograded profile is achieved, in part, by doping the buried Sil_.,Ge,, layer with a sufficient concentration of Ge to substantially increase the dopant solubility of arsenic in the Si,, Ge, layer relative to the silicon active layer. In particular, FIG. 7C illustrates pre-anneal phosphorus and arsenic profiles (phosphorus and arsenic dopants were implanted at energies of 30 KeV and 200 KeV, respectively) and FIG. 7D illustrates post-anneal profiles. As with FIG. 713, the rapid thermal annealing step was performed at a temperature of about 100M and a duration of about 30 seconds. As illustrated by FIG. 7D, the arsenic profile decreases monotonically from a peak concentration level of 1xl 019cm' within the buried Sil,Ge, layer to a minimum concentration level of 1X1017 cm-3at the surface of the substrate. Depending on the profile and concentration of the phosphorus dopants in the silicon active layer, the combined profile of the P and As dopants may also be retrograded across the silicon active layer.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (58)
1. A semiconductor-on-insulator field effect transistor, comprising: an electrically insulating layer; an unstrained silicon active layer on said electrically insulating' layer; an insulated gate electrode on a surface of said unstrained silicon active layer; and a Sil-XGex layer disposed between said electrically insulating layer and said unstrained silicon active layer, said Sil-Aex layer forming a first junction with said unstrained silicon active layer and having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface.
2. The transistor of Claim 1, wherein the peak level is greater than x=0. 15; and wherein the concentration of Ge in said Sil-XGex layer varies from the peak level to a level less than about x=0.1 at the first junction.
3. The transistor of Claim 2, wherein the concentration of Ge in said SilAex layer varies from the peak level where 0.2<x<0.4 to a level where x=0 at the first junction.
4. The transistor of Claim 3, wherein said Sil-XGex layer defines an interface with said electrically insulating layer; and wherein the graded concentration of Ge in said Sil-xGex layer also increases from a level less than about x=0.1 at the interface to the peak level.
5. The transistor according to any of Claims 1 to 4, wherein said unstrained silicon active layer has a thickness greater than about 600A..
6. The transistor according to any of Claims 1 to 5, wherein said SilXGex layer has a thickness of less than about 8ooA..
7. The transistor according to Claims 1 to 6, wherein said Sil-XGex layer is doped with an N-type dopant; and wherein a concentration of the N-type dopant in said Sil-XGex layer has a profile that decreases in the first direction.
8. A semiconductor-on-insulator field effect transistor, comprising: an electrically insulating layer; a composite semiconductor active region on said electrically insulating layer, said composite semiconductor active region comprising an unstrained silicon active layer having a thickness greater than about 600 A0 and a single Sil-XG ex layer disposed between said electrically insulating layer and said silicon active layer, said Sil-XGex layer forming a first junction with said silicon active layer and having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards a surface of said silicon active layer; and an insulated gate electrode on the surface.
9. The transistor of Claim 8, wherein the peak level is greater than x=0. 15; and wherein the concentration of Ge in said Sil-XGex layer varies from the peak level to a level less than about x=0. 1 at the first junction.
10. The transistor of Claim 9, wherein the concentration of Ge in said SilXGex layer varies from the peak level where 0.2<x<0.4 to a level where x=0 at the first junction.
11. The transistor of Claim 10, wherein said Sil -XGex layer defines an interface with said electrically insulating layer; and wherein the graded concentration of Ge in said Sil-Aex layer also increases from a level less than about x=0.1 at the interface to the peak level.
12. The transistor according to any of Claims 8 to 11, wherein said SilAex layer has a thickness of less than about 800A.
21
13. A PMOS field effect transistor, comprising: an electrically insulating layer; a composite semiconductor active region on said electrically insulating layer, said composite semiconductor active region comprising a single Sil-XGex layer having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level within the single Sil-XGex layer towards a surface thereof and a silicon active layer that extends from a first junction with the single Sil-xGex layer to the surface, said composite semiconductor active region having a retrograded N-type dopant profile therein with a minimum level adjacent the surface and a peak level in the single Sil-XGex layer; and an insulated gate electrode on the surface.
14. The transistor of Claim 13, wherein the silicon active layer has a thickness greater than about 600A and has an unstrained region therein adjacent the surface.
15. The transistor of Claim 13 or 14, further comprising: lightly doped Ptype source and drain regions that extend in the silicon active layer and opposite the insulated gate electrode; and a source-side pocket implant region of N-type conductivity that extends between said lightly doped Ptype source region and the single Sil-XGex layer and forms rectifying and nonrectifying junctions therewith, respectively.
22
16. An enhancement-mode field effect transistor, comprising: an electrically insulating layer; a silicon active layer on said electrically insulating layer; an insulated gate electrode on a surface of said silicon active layer; a Sil-XGex epitaxial layer disposed between said electrically insulating layer and said silicon active layer, said Sil-xGex epitaxial layer forming a first junction with said silicon active layer; lightly doped source and drain regions of first conductivity type in said silicon active layer; and a source-side pocket implant region of second conductivity type that extends between said lightly doped source region and said Sil-xGex epitaxial layer and forms rectifying and non-rectifying junctions therewith.
17. The transistor of Claim 16, wherein said Sil-xGex epitaxial layer has a graded concentration of Ge therein that decreases in a direction from said electrically insulating layer to said insulated gate electrode.
18. The transistor of Claim 17, wherein said Sil-XGex epitaxial layer has a retrograded N-ype dopant profile therein.
19. The transistor according to any of Claims 16 to 18, wherein said silicon active layer has a thickness greater than about 600A.
23
20. A method of forming a semiconductor substrate, comprising the steps of: forming a handling substrate having a silicon layer therein and a SilXGex layer extending on the silicon layer; bonding a supporting substrate to the handing substrate so that the SilXGex layer is disposed between the supporting substrate and the silicon layer; and removing a portion of the handling substrate from the supporting substrate to expose the silicon layer and define a semiconductor-on-insulator substrate having a buried Sil-xGex layer therein.
21. The method of Claim 20, wherein the buried Sil-XGex layer has a graded concentration of Ge therein that decreases in a direction from the supporting substrate to the silicon layer; and wherein the silicon layer is an unstrained silicon layer.
22. The method of Claim 20 or 21, wherein said step of forming a handling substrate comprises forming a handling substrate having a first silicon layer therein, a Sil-Aex layer extending on the first silicon layer and a second silicon layer extending on the Sil-Aex layer.
23. The method of Claim 22, wherein said bonding step is preceded by the step of thermally oxidizing the second silicon layer to define a thermal oxide layer; wherein the supporting substrate comprises an oxide surface layer thereon; and wherein said bonding step comprises bonding the oxide surface layer to the thermal oxide layer.
24 24. The method of Claim 20, wherein said bonding step is preceded by the step of depositing an electrically insulating layer on the Sil,Ge. layer; wherein the supporting substrate comprises an oxide surface layer thereon; and wherein said bonding step comprises bonding the oxide surface layer to the electrically insulating layer.
25. The method according to any of Claims 20 to 24, wherein the handling substrate comprises a porous silicon layer therein;..and wherein said removing step comprises removing a portion of the handling substrate from the supporting substrate by splitting the porous silicon layer.
26. The method of Claim 25, wherein said removing step comprises planarizing the porous silicon layer and the silicon layer in sequence.
27. The method of Claim 20, wherein the handling substrate comprises a porous silicon layer therein; and wherein said removing step comprises planarizing the porous silicon layer and the silicon layer in sequence.
28. The method of Claim 20, wherein said step of forming a handling substrate comprises the steps of. epitaxially growing a Si,,Ge. layer on the silicon layer; and implanting hydrogen ions through the Sil,Gex layer and the silicon layer to define a hydrogen implant layer in the handling substrate.
29. The method of Claim 28, wherein said removing step comprises splitting the hydrogen implant layer.
30. The method of Claim 29, wherein said removing step comprises planarizing the hydrogen implant layer.
31. The method of Claim 21, wherein said step of forming a handling substrate comprises the steps of: epitaxially growing a Sil.xGex layer on the silicon layer; and implanting hydrogen ions through the Sil,Gex layer and the silicon layer to define a hydrogen implant layer in the handling substrate.
32. The method of Claim 31, wherein said removing step comprises splitting the hydrogen implant layer.
33. The method of Claim 32, wherein said removing step comprises planarizing the hydrogen implant layer.
34. A method of forming a semiconductor substrate, comprising the steps of:
forming a handling substrate having an unstrained silicon layer therein and an epitaxial Sil-xGe. layer having a graded concentration of Ge therein extending on the unstrained silicon layer; bonding a supporting substrate to the handing substrate so that the Sil, Gex layer is disposed between the supporting substrate and the unstrained silicon layer; and removing a portion of the handling substrate from the supporting substrate to expose the unstrained silicon layer and define a semiconductor-oninsulator substrate having a buried Sil,Ge, layer therein.
35. The method of Claim 34, wherein said forming step comprises forming a handling substrate having an unstrained silicon layer therein with a thickness greater than about 600 A.
36. The method of Claim 35, wherein the Si,,,Ge, layer has a thickness of less than about 800A.
37. A semiconductor-on-insulator substrate, comprising:
a silicon wafer having an electrically insulating layer thereon; a Sil-,Ge, layer having a graded concentration of Ge therein extending on the electrically insulating layer; and an unstrained silicon active layer extending on and forming a non- rectifying junction with the Sil,Ge, layer and extending to a surface of the semiconductor-on insulator substrate.
38. The substrate of Claim 37, wherein said Sil-xGex layer is epitaxially grown from said unstrained silicon active layer.
39. The substrate of Claim 38, wherein said unstrained silicon active layer has a thickness greater than about 600A.
40. A method of forming a field effect transistor, comprising the steps of:
forming an insulated gate electrode on a surface of a semiconductor-on insulator substrate that comprises an electrically insulating layer, an unstrained silicon active layer on the electrically insulating layer and a Sil-xGe, epitaxial layer having a graded concentration of Ge therein disposed between the electrically insulating layer and the unstrained silicon active layer; forming source and drain regions of first conductivity type in the unstrained silicon active layer; and forming source-side and drain-side pocket implant regions of second conductivity type that extend in the unstrained silicon active layer and in the Sil-xGe', epitaxial layer and form respective P-N junctions with the source and drain regions.
41. The method of Claim 40, wherein the unstrained silicon active layer has a thickness greater than about 600A.
42. The method of Claim 40, wherein said step of forming an insulated gate electrode is preceded by the step of implanting threshold voltage control dopants of first conductivity type into the unstrained silicon active layer; and wherein said step of forming an insulated gate electrode is followed by the step of annealing the semiconductor-on-insulator substrate to establish a retrograded profile of threshold voltage control dopants in the Sil,,Gex epitaxial layer.
43. The method of Claim 42, wherein said step of forming source-side and drain-side pocket implant regions is followed by the step of forming sidewall insulating spacers on the insulated gate electrode; and wherein said step of forming source and drain regions comprises the steps of:
implanting first source and drain region dopants of first conductivity type into the unstrained silicon active layer, using the insulated gate electrode as an implant mask; and implanting second source and drain region dopants of first conductivity type into the unstrained silicon active layer, using the insulated gate electrode and the sidewall insulating spacers as an implant mask.
44. A semiconductor-on-insulator field effect transistor, comprising: a bulk silicon region; an electrically insulating layer on said bulk silicon region; an unstrained silicon active layer having a first thickness on said electrically insulating layer, an insulated gate electrode on a surface of said unstrained silicon active layer; sidewall insulating spacers on said insulated gate electrode; a Si,,Ge, layer of first conductivity type disposed between said electrically insulating layer and said unstrained silicon active layer, said Sil,,Ge,' layer forming a first junction with said unstrained silicon active layer and having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface; lightly doped source and drain regions of second conductivity type extending in said unstrained silicon active layer and having a thickness less than the first thickness; and a source-side pocket implant region of first conductivity type in said unstrained silicon active layer, said source- side pocket implant region extending between said lightly doped source region and said Sil-xGex layer.
45. The transistor of Claim 44, wherein said Sil-xGe, layer has a retrograded first conductivity type doping profile therein relative to the surface.
46. The transistor of Claim 45, wherein said Sil,Gex layer has a retrograded arsenic doping profile therein relative to the surface.
47. The transistor of Claim 45, further comprising a channel region of first conductivity type in said unstrained silicon active layer; and wherein a peak concentration of first conductivity type dopants in said Sil,Ge. layer is greater than a peak concentration of first conductivity type dopants in said channel region.
48. The transistor of Claim 46, further comprising a channel region of first conductivity type in said unstrained silicon active layer; and wherein a peak concentration of first conductivity type dopants in said Si,,Ge. layer is greater than a peak concentration of first conductivity type dopants in said channel. region.
49. The transistor of Claim 48, wherein said unstrained silicon active layer has a thickness greater than about 600k
50. The transistor of Claim 45, wherein said unstrained silicon active layer has a thickness greater than about 600A.
51. A field effect transistor, comprising:
an electrically insulating layer; a silicon active layer of first conductivity type on said electrically insulating layer; an insulated gate electrode on a surface of said silicon active layer; a source region and a drain region of second conductivity type in said silicon active layer; lightly doped source and drain regions of second conductivity type extending between said source region and said drain region and defining a channel region underneath said insulated gate electrode; and a Sil,Gex epitaxial layer disposed between said lightly doped source and drain regions and said electrically insulating layer-
52. The transistor of Claim 51, wherein said lightly doped source an drain regions do not contact said Sil,Ge, epitaxial layer; and wherein said source region and said drain region contact said Sil,Gex epitaxial layer.
53. The transistor of Claim 51, further comprising an epitaxial silicon layer disposed between said Sil,Gex epitaxial layer and said electrically insulating layer.
54. The transistor of Claim 51, wherein a total thickness of said Sil,Gex epitaxial layer and said silicon active layer is less than about 1500A.
55. A method of forming a field effect transistor, comprising the steps of:
forming an electrically insulating layer, forming a silicon active layer of first conductivity type on said electrically insulating layer; forming an insulated gate electrode on a surface of said silicon active layer; forming a source region and a drain region of second conductivity type in said silicon active layer; forming lightly doped source and drain regions of second conductivity type extending between said source region and said drain region and defining a channel region underneath said insulated gateelectrode; and forming a Sil,Ge, epitaxial layer disposed between said lightly doped source and drain regions and said electrically insulating layer.
56. The method of Claim 55, wherein said lightly doped source an drain regions do not contact said Sil,Ge, epitaxial layer; and wherein said source region and said drain region contact said Sil,Gex epitaxial layer.
57. The method of Claim 55, further comprising the step of forming an epitaxial silicon layer disposed between said Sil,Gex epitaxial layer and said electrically insulating layer.
58. The transistor of Claim 55, wherein a total thickness of said Sil,Ge, epitaxial layer and said silicon active layer is less than about 1500A.
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| GB0415353A GB2400731B (en) | 2000-01-07 | 2001-01-04 | Substrates having buried silicon germanium layers therein and methods of forming same |
| GB0415351A GB2400730B (en) | 2000-01-07 | 2001-01-04 | CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same |
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| US09/711,706 US6633066B1 (en) | 2000-01-07 | 2000-11-13 | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
| KR10-2000-0075482A KR100429869B1 (en) | 2000-01-07 | 2000-12-12 | CMOS Integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same |
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| GB0415350A Expired - Fee Related GB2400729B (en) | 2000-01-07 | 2001-01-04 | CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same |
| GB0100209A Expired - Fee Related GB2365214B (en) | 2000-01-07 | 2001-01-04 | CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same |
| GB0415351A Expired - Fee Related GB2400730B (en) | 2000-01-07 | 2001-01-04 | CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same |
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| KR (1) | KR100429869B1 (en) |
| CN (1) | CN1165085C (en) |
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| WO2004006327A3 (en) * | 2002-07-09 | 2004-03-04 | Soitec Silicon On Insulator | Transfer of a thin layer from a wafer comprising a buffer layer |
| US6953736B2 (en) | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
| WO2004006311A2 (en) * | 2002-07-09 | 2004-01-15 | S.O.I.Tec Silicon On Insulator Technologies | Transfer of a thin layer from a wafer comprising a buffer layer |
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| GB2400731B (en) | 2004-12-08 |
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| GB2400729B (en) | 2004-12-08 |
| GB2400730B (en) | 2004-12-08 |
| GB2365214B (en) | 2004-09-15 |
| CN1165085C (en) | 2004-09-01 |
| KR100429869B1 (en) | 2004-05-03 |
| KR20010070298A (en) | 2001-07-25 |
| GB2400731A (en) | 2004-10-20 |
| GB0415351D0 (en) | 2004-08-11 |
| GB2400729A (en) | 2004-10-20 |
| DE10100194A1 (en) | 2001-07-19 |
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