CN111952186A - Field effect transistor based on cavity surrounding structure and preparation method - Google Patents
Field effect transistor based on cavity surrounding structure and preparation method Download PDFInfo
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- CN111952186A CN111952186A CN202010850598.9A CN202010850598A CN111952186A CN 111952186 A CN111952186 A CN 111952186A CN 202010850598 A CN202010850598 A CN 202010850598A CN 111952186 A CN111952186 A CN 111952186A
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- 238000000034 method Methods 0.000 claims description 23
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
Abstract
The invention provides a field effect transistor based on a cavity surrounding structure and a preparation method thereof, wherein the field effect transistor comprises a substrate, an insulating layer and a semiconductor top layer which are sequentially stacked, a strip-shaped grid is formed on the semiconductor top layer, a first pole and a second pole are respectively formed on two sides of the strip-shaped grid, the first pole is one of a source electrode and a drain electrode, the second pole is the other of the source electrode and the drain electrode, an annular cavity is formed in the insulating layer, the annular cavity surrounds the first pole in the vertical projection direction, the strip-shaped grid is positioned above one side cavity of the annular cavity, the width of the side cavity is larger than, equal to or smaller than that of the strip-shaped grid, and the side cavity completely covers the strip-shaped grid in the. According to the invention, the annular cavity is introduced below the source region or/and the drain region, and the strip-shaped grid electrode is completely covered by one side cavity of the annular cavity in the vertical projection direction, so that a side edge structure formed by overlapping of the conducting channels of the insulating layer can be thoroughly eliminated, a leakage channel is eliminated, and the total dose irradiation resistance can be greatly improved.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a field effect transistor based on a cavity surrounding structure and a preparation method thereof.
Background
The transistor based on the SOI substrate has good single-particle effect resistance, but in the SOI structure, when high-energy particles enter the insulating layer (BOX layer), more positive charges are easy to accumulate, and the positive charges cause a parasitic conductive channel in SOI top layer silicon, so that leakage current is introduced, and the electrical performance of the device is drifted.
The total dose effect can be effectively prevented by removing the insulating layer (BOX layer) below the channel of the SOI transistor, and the transistor structure based on the patterned SOI substrate is shown in figure 1, and the total dose effect can be effectively reduced by removing the insulating layer formed groove 101 below the channel of the transistor, however, the insulating layer (BOX layer) in the structure still has an overlapped contact part 102 with the conducting channel, and when the total dose effect occurs, the electric leakage in the direction of a broken line shear head can be caused.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a field effect transistor based on a cavity-enclosed structure and a method for manufacturing the same, which are used to solve the problem of current leakage caused by the total dose effect when the insulating layer and the conductive channel of the transistor structure of the patterned SOI substrate have overlapping contact portions in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a field effect transistor based on a cavity-enclosed structure, the method comprising the steps of: 1) providing a substrate, an insulating layer and a semiconductor top layer which are sequentially stacked, wherein the insulating layer is provided with an annular cavity; 2) forming a strip-shaped grid electrode on the top semiconductor layer, wherein the strip-shaped grid electrode is positioned above one side cavity of the annular cavity, the width of the side cavity is greater than, equal to or smaller than that of the strip-shaped grid electrode, and the side cavity completely covers or partially covers the strip-shaped grid electrode in the vertical projection direction; 3) and respectively forming a first pole and a second pole in the top semiconductor layers at two sides of the strip-shaped grid, wherein the annular cavity surrounds the first pole in the vertical projection direction, the first pole is one of a source electrode and a drain electrode, and the second pole is the other of the source electrode and the drain electrode.
Optionally, step 1) comprises: 1-1) providing a semiconductor layer, performing ion implantation on the semiconductor layer to form an exfoliation layer in the semiconductor layer, wherein a preset distance is formed between the exfoliation layer and a cavity structure to be formed, the preset distance is set according to the cavity structure, and the setting mode comprises that the preset distance is greater than 1/8 of the characteristic size of a cavity of the cavity structure; 1-2) providing a substrate, wherein the surface of the substrate comprises an insulating layer with a cavity structure, and bonding the semiconductor layer with the substrate; 1-3) peeling off the semiconductor layer along the peeling layer to transfer a part of the semiconductor layer onto the patterned dielectric layer so as to form a transfer substrate film layer on the patterned dielectric layer; 1-4) oxidizing the transfer substrate film layer to form an oxide layer on the surface of the transfer substrate film layer, removing the oxide layer to thin the transfer substrate film layer, or thinning the transfer substrate layer by adopting a mechanical chemical polishing process to form the semiconductor top layer; wherein, the definition mode of the characteristic size of the cavity comprises the following steps: defining a two-dimensional plane above the cavity structure parallel to the surface of the cavity structure; in the two-dimensional plane, a plurality of selected points are arranged above the cavity structure; for each said selected point, there are a number of straight lines passing through said selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are respectively adjacent to the selected point in two directions of the straight line extending through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum size of the cavity based on a number of the straight lines passing through each of the selected points; and selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the characteristic size of the cavity.
Optionally, the optical module further comprises another annular cavity, the another annular cavity surrounds the second pole in the vertical projection direction, and the another annular cavity and the annular cavity share one side cavity.
Optionally, an annular heavily doped isolation region is further formed in the top semiconductor layer at the periphery of the annular cavity, a conductivity type of the annular heavily doped isolation region is opposite to conductivity types of the first pole and the second pole, and a lightly doped region or a non-doped region is further formed between the annular heavily doped isolation region and the first pole or/and the second pole.
Optionally, the first pole is located inside the annular cavity in the vertical projection direction, the lightly doped region or the undoped region covers the annular cavity in the vertical projection direction and exceeds the edge of the annular cavity, and the annular heavily doped isolation region surrounds the lightly doped region or the undoped region in the vertical projection direction and has a distance from the edge of the annular cavity.
Optionally, one or more annular support structures are provided in the annular cavity, and the annular support structures are retained by the insulating layer.
Optionally, the annular cavity is shaped as a rectangular ring.
The invention also provides a field effect transistor based on the cavity surrounding structure, the field effect transistor comprises a substrate, an insulating layer and a semiconductor top layer which are sequentially stacked, a strip-shaped grid is formed on the semiconductor top layer, a first pole and a second pole are respectively formed in the semiconductor top layer on two sides of the strip-shaped grid, the first pole is one of a source electrode and a drain electrode, the second pole is the other of the source electrode and the drain electrode, an annular cavity is formed in the insulating layer, the annular cavity surrounds the first pole in the vertical projection direction, the strip-shaped grid is positioned above one side cavity of the annular cavity, the width of the side cavity is larger than, equal to or smaller than that of the strip-shaped grid, and the side cavity completely covers the strip-shaped grid in the vertical projection direction.
Optionally, the optical module further comprises another annular cavity, the another annular cavity surrounds the second pole in the vertical projection direction, and the another annular cavity and the annular cavity share one side cavity.
Optionally, an annular heavily doped isolation region is further formed in the top semiconductor layer at the periphery of the annular cavity, a conductivity type of the annular heavily doped isolation region is opposite to conductivity types of the first pole and the second pole, and a lightly doped region or a non-doped region is further formed between the annular heavily doped isolation region and the first pole or/and the second pole.
Optionally, the first pole is located inside the annular cavity in the vertical projection direction, the lightly doped region or the undoped region covers the annular cavity in the vertical projection direction and exceeds the edge of the annular cavity, and the annular heavily doped isolation region surrounds the lightly doped region or the undoped region in the vertical projection direction and has a distance from the edge of the annular cavity.
Optionally, one or more annular support structures are provided in the annular cavity, and the annular support structures are retained by the insulating layer.
Optionally, the annular cavity is shaped as a rectangular ring.
As described above, the field effect transistor based on the cavity surrounding structure and the manufacturing method of the field effect transistor based on the cavity surrounding structure of the invention have the following beneficial effects:
according to the invention, the annular cavity is introduced below the source region or/and the drain region, and one side cavity of the annular cavity completely covers or partially covers the strip-shaped grid electrode in the vertical projection direction, so that a side structure formed by overlapping of conducting channels of the insulating layer can be completely eliminated, a leakage channel is eliminated, and the total dose irradiation resistance can be greatly improved.
According to the invention, when ion implantation is carried out to form a stripping interface, the stripping layer is prefabricated according to a cavity structure to be formed, so that the preset distance between the stripping layer and the cavity structure to be formed is larger than 1/8 of the characteristic dimension of the cavity structure, and then the semiconductor top layer with the required thickness is formed by oxidation thinning and polishing thinning, so that the material layer above the cavity structure is prevented from being damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and the performance of a device are improved.
Drawings
Fig. 1 shows a schematic diagram of a transistor structure based on a patterned SOI substrate.
Fig. 2 to 12 are schematic structural diagrams showing steps of a method for manufacturing a field effect transistor based on a cavity-enclosed structure according to embodiment 1 of the present invention.
Fig. 13 to 15 are schematic structural views of a field effect transistor based on a cavity-enclosed structure according to embodiment 2 of the present invention.
Fig. 16 is a schematic structural view of a field effect transistor based on a cavity-enclosed structure according to embodiment 3 of the present invention.
Description of the element reference numerals
201 substrate
202 insulating layer
203 semiconductor top layer
204 annular cavity
2041 side Cavity
2042 Another annular cavity
2043 Ring shaped supporting Structure
205 bar grid
2051 Gate oxide layer
2052 gate electrode
2053 Gate sidewall spacer
206 first pole
207 second pole
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example 1
As shown in fig. 2 to fig. 12, wherein fig. 3, 5, 7, 9 and 11 are respectively shown as schematic cross-sectional structural diagrams at a-a' in fig. 2, 4, 6, 8 and 10, the present embodiment provides a method for manufacturing a field effect transistor based on a cavity-enclosed structure, the method comprising the steps of:
as shown in fig. 2 to fig. 3, step 1) is first performed to provide a substrate 201, an insulating layer 202 and a top semiconductor layer 203 stacked in sequence, where the insulating layer 202 has a ring-shaped cavity 204 therein.
In this embodiment, the annular cavity 204 is shaped as a rectangular ring.
Specifically, step 1) includes:
as shown in fig. 3, first, 1-1) of providing a semiconductor layer, and performing ion implantation on the semiconductor layer to form an exfoliation layer in the semiconductor layer, where the exfoliation layer has a predetermined distance from a cavity structure to be formed, the predetermined distance is set according to the cavity structure, and the setting manner includes 1/8 where the predetermined distance is greater than a characteristic size of a cavity of the cavity structure.
For example, the semiconductor layer may be Si, although Si may be replaced by Ge, GaN, SiC, GaAs, AlGaN, Ga2O3, InP, or other crystalline semiconductors.
In this embodiment, the defining manner of the characteristic dimension of the cavity includes: defining a two-dimensional plane above the cavity structure parallel to the surface of the cavity structure; in the two-dimensional plane, a plurality of selected points are arranged above the cavity structure; for each said selected point, there are a number of straight lines passing through said selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are respectively adjacent to the selected point in two directions of the straight line extending through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum size of the cavity based on a number of the straight lines passing through each of the selected points; and selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the characteristic size of the cavity. For example, in the present embodiment, the cavity characteristic dimension is the width of the annular cavity 204.
As shown in fig. 3, step 1-2) is then performed to provide a substrate 201, a surface of the substrate 201 includes an insulating layer 202 having a cavity structure, and a side of the semiconductor layer on which the ion implantation is performed is bonded to the substrate 201.
For example, the substrate 201 may be Si or the like, and the insulating layer 202 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium aluminum oxide, zirconium oxide, hafnium zirconium oxide, lanthanum lutetium oxide, or other insulating medium. The cavity structure may be formed in the insulating layer 202 by, for example, a photolithography-etching process, and a portion of the insulating layer 202 may be left at the bottom of the cavity structure, or the insulating layer 202 may be completely removed, or the cavity structure may penetrate through the insulating layer 202 and extend to a certain depth of the substrate 201.
As shown in fig. 3, step 1-3) is performed, the semiconductor layer is peeled along the peeling layer, so that a part of the semiconductor layer is transferred onto the patterned medium layer, and a transfer substrate film layer is formed on the patterned medium layer;
as shown in fig. 3, step 1-4) is finally performed to oxidize the transfer substrate film layer to form an oxide layer on the surface of the transfer substrate film layer, and the oxide layer is removed to thin the transfer substrate film layer, or the transfer substrate layer is thinned by adopting a mechanochemical polishing process to form the semiconductor top layer 203.
According to the invention, when ion implantation is carried out to form a stripping interface, the stripping layer is prefabricated according to a cavity structure to be formed, the preset distance between the stripping layer and the cavity structure to be formed is larger than 1/8 of the characteristic dimension of the cavity structure, and the semiconductor top layer 203 with the required thickness is formed by oxidation thinning and polishing thinning, so that the material layer above the cavity structure is prevented from being damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and the performance of a device are improved.
As shown in fig. 4 to fig. 7, step 2) is then performed to form a stripe-shaped gate 205 on the top semiconductor layer 203, where the stripe-shaped gate is located above one side cavity of the ring-shaped cavity, the width of the side cavity is greater than, equal to, or less than the width of the stripe-shaped gate, and the side cavity completely covers or partially covers the stripe-shaped gate in the vertical projection direction.
Specifically, the method comprises the following steps:
as shown in fig. 4 to fig. 7, step 2-1) is first performed, a gate oxide layer 2051 is formed on the surface of the top semiconductor layer 203 by using a thermal oxidation method or a deposition method, where the gate oxide layer 2051 may be prepared by thermal oxidation, atomic layer deposition, or the like, and the gate oxide layer 2051 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium aluminum oxide, zirconium oxide, hafnium zirconium oxide, lutetium lanthanum oxide, or other medium with good insulating property.
As shown in fig. 4 to fig. 7, step 2-2) is performed, a gate electrode material is formed on the gate oxide layer 2051 by a deposition method, and a gate electrode 2052 is formed by etching, where the gate electrode material may be a conductive material or an alloy such as polysilicon, Ti, Cu, Al, W, Ni, Cr, Ta, Mo, TiN, TaN, or the like.
As shown in fig. 4 to 7, step 2-3) is then performed to form gate spacers 2053 on both sides of the gate electrode 2052.
In this embodiment, the method further includes a step of lightly doping the source region and the drain region to reduce the on-resistance.
In this embodiment, the stripe-shaped gate 205 is located above one side cavity 2041 of the annular cavity, the width of the side cavity is greater than or equal to the width of the stripe-shaped gate 205, and the side cavity 2041 completely covers the stripe-shaped gate 205 in the vertical projection direction, the width of the side cavity 2041 of the annular cavity 204 of this embodiment is greater than or equal to the width of the stripe-shaped gate 205, and the side cavity 2041 completely covers the stripe-shaped gate 205 in the vertical projection direction, so that the total dose irradiation resistance of the device can be further improved.
As shown in fig. 8 to 11, step 3) is finally performed, a first pole 206 and a second pole 207 are respectively formed in the top semiconductor layer 203 on both sides of the stripe-shaped gate 205 through ion implantation and annealing processes, and the annular cavity 204 surrounds the first pole 206 in a vertical projection direction, wherein the first pole 206 is one of a source and a drain, and the second pole 207 is the other of the source and the drain.
In order to further improve the total dose radiation resistance and reduce the leakage current of the fet, as shown in fig. 10, in the present embodiment, the fet further includes another annular cavity 2042, the another annular cavity 2042 surrounds the second pole 207 in the vertical projection direction, and the another annular cavity 2042 and the annular cavity share one side cavity 2041.
Furthermore, Halo implantation can be performed on the source region and the drain region to form Halo implantation regions.
The field effect transistor can be an NMOS, the source electrode and the drain electrode are doped in an N type mode, the field effect transistor can also be a PMOS, and the source electrode and the drain electrode are doped in a P type mode.
As shown in fig. 12, in the present embodiment, a ring-shaped heavily doped isolation region 302 is further formed in the top semiconductor layer at the periphery of the ring-shaped cavity, and the conductivity type of the ring-shaped heavily doped isolation region 302 is opposite to the conductivity type of the first pole 206 and the second pole 206, and a lightly doped region or an undoped region 301 is further formed between the ring-shaped heavily doped isolation region 302 and the first pole or/and the second pole. The first pole 206 is located in the annular cavity 204 in the vertical projection direction, the lightly doped region or the undoped region 301 covers the annular cavity 204 in the vertical projection direction and exceeds the edge of the annular cavity 204, and the annular heavily doped isolation region 302 surrounds the lightly doped region or the undoped region 301 in the vertical projection direction and has a distance with the edge of the annular cavity. The design can ensure the isolation between field effect transistors on one hand, and the lightly doped region or the undoped region can ensure that the annular heavily doped isolation region can not interfere with the first pole and the second pole on the other hand, thereby improving the stability of the device.
According to the invention, the annular cavity is introduced below the source region or/and the drain region, and one side cavity of the annular cavity completely covers or partially covers the strip-shaped grid electrode in the vertical projection direction, so that a side structure formed by overlapping of conducting channels of the insulating layer can be completely eliminated, a leakage channel is eliminated, and the total dose irradiation resistance can be greatly improved.
As shown in fig. 10 to 12, the present embodiment also provides a field effect transistor based on a cavity-enclosed structure, the field effect transistor includes a substrate 201, an insulating layer 202 and a top semiconductor layer 203 stacked in this order, a stripe-shaped gate 205 is formed on the top semiconductor layer 203, a first pole 206 and a second pole 207 are respectively formed in the top semiconductor layer on both sides of the stripe-shaped gate 205, the first pole 206 is one of a source and a drain, the second pole 207 is the other of the source and the drain, an annular cavity 204 is formed in the insulating layer 202, the annular cavity 204 surrounding the first pole 206 in a perpendicular projection direction, the stripe-shaped gate 205 is located above one of the side cavities 2041 of the toroidal cavity 204, the width of the side cavity 2041 is greater than or equal to the width of the stripe-shaped gate 205, and the side cavity 2041 completely covers the stripe-shaped gate in the vertical projection direction.
As shown in fig. 12, in the present embodiment, a ring-shaped heavily doped isolation region 302 is further formed in the top semiconductor layer at the periphery of the ring-shaped cavity, and the conductivity type of the ring-shaped heavily doped isolation region 302 is opposite to the conductivity type of the first pole 206 and the second pole 206, and a lightly doped region or an undoped region 301 is further formed between the ring-shaped heavily doped isolation region 302 and the first pole or/and the second pole. The first pole 206 is located in the annular cavity 204 in the vertical projection direction, the lightly doped region or the undoped region 301 covers the annular cavity 204 in the vertical projection direction and exceeds the edge of the annular cavity 204, and the annular heavily doped isolation region 302 surrounds the lightly doped region or the undoped region 301 in the vertical projection direction and has a distance with the edge of the annular cavity. The design can ensure the isolation between field effect transistors on one hand, and the lightly doped region or the undoped region can ensure that the annular heavily doped isolation region can not interfere with the first pole and the second pole on the other hand, thereby improving the stability of the device.
In this embodiment, the annular cavity is shaped as a rectangular ring.
In order to further improve the total dose radiation resistance and reduce the leakage current of the fet, as shown in fig. 10, in the present embodiment, the fet further includes another annular cavity 2042, the another annular cavity 2042 surrounds the second pole 207 in the vertical projection direction, and the another annular cavity 2042 and the annular cavity share one side cavity 2041.
Furthermore, Halo implantation can be performed on the source region and the drain region to form Halo implantation regions.
The field effect transistor can be an NMOS, the source electrode and the drain electrode are doped in an N type mode, the field effect transistor can also be a PMOS, and the source electrode and the drain electrode are doped in a P type mode.
Example 2
As shown in fig. 13 to fig. 15, the present embodiment further provides a field effect transistor based on a cavity-enclosed structure and a method for manufacturing the same, wherein the basic structure of the field effect transistor is as in embodiment 1, and the difference from embodiment 1 is that: the field effect transistor is provided with only one annular cavity 204 which surrounds the first pole 206 in the vertical projection direction, and no annular cavity is arranged below the second pole 207.
Example 3
As shown in fig. 16, the present embodiment further provides a field effect transistor based on a cavity-enclosed structure and a manufacturing method thereof, wherein the basic structure is as in embodiment 1, and the difference from embodiment 1 is as follows: the annular cavity 204 has one or more annular support structures 2043 therein, which are retained by the insulating layer 202. The annular cavity 204 is internally provided with the annular supporting structure 2043, so that the cavity characteristic size of the annular cavity 204 can be effectively reduced, the required thickness of a stripped semiconductor layer is reduced, and the subsequent thinning process time is saved. Meanwhile, the annular supporting structure can effectively enhance the mechanical strength of the annular cavity 204 and improve the stability of the device in the subsequent use of the device.
As described above, the method for manufacturing a field effect transistor based on a cavity surrounding structure according to the present invention has the following advantages:
according to the invention, the annular cavity is introduced below the source region or/and the drain region, and one side cavity of the annular cavity completely covers the strip-shaped grid electrode in the vertical projection direction, so that a side edge structure formed by overlapping of conducting channels of the insulating layer can be thoroughly eliminated, a leakage channel is eliminated, and the total dose irradiation resistance can be greatly improved.
According to the invention, when ion implantation is carried out to form a stripping interface, the stripping layer is prefabricated according to a cavity structure to be formed, so that the preset distance between the stripping layer and the cavity structure to be formed is larger than 1/8 of the characteristic dimension of the cavity structure, and then the semiconductor top layer with the required thickness is formed by oxidation thinning and polishing thinning, so that the material layer above the cavity structure is prevented from being damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and the performance of a device are improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A preparation method of a field effect transistor based on a cavity surrounding structure is characterized by comprising the following steps:
1) providing a substrate, an insulating layer and a semiconductor top layer which are sequentially stacked, wherein the insulating layer is provided with an annular cavity;
2) forming a strip-shaped grid electrode on the top semiconductor layer, wherein the strip-shaped grid electrode is positioned above one side cavity of the annular cavity, the width of the side cavity is greater than, equal to or smaller than that of the strip-shaped grid electrode, and the side cavity completely covers or partially covers the strip-shaped grid electrode in the vertical projection direction;
3) and respectively forming a first pole and a second pole in the top semiconductor layers at two sides of the strip-shaped grid, wherein the annular cavity surrounds the first pole in the vertical projection direction, the first pole is one of a source electrode and a drain electrode, and the second pole is the other of the source electrode and the drain electrode.
2. The method for preparing a field effect transistor based on a cavity-enclosing structure according to claim 1, wherein the step 1) comprises:
1-1) providing a semiconductor layer, performing ion implantation on the semiconductor layer to form an exfoliation layer in the semiconductor layer, wherein a preset distance is formed between the exfoliation layer and a cavity structure to be formed, the preset distance is set according to the cavity structure, and the setting mode comprises that the preset distance is greater than 1/8 of the characteristic size of a cavity of the cavity structure;
1-2) providing a substrate, wherein the surface of the substrate comprises an insulating layer with a cavity structure, and bonding the semiconductor layer with the substrate;
1-3) peeling off the semiconductor layer along the peeling layer to transfer a part of the semiconductor layer onto the patterned dielectric layer so as to form a transfer substrate film layer on the patterned dielectric layer;
1-4) oxidizing the transfer substrate film layer to form an oxide layer on the surface of the transfer substrate film layer, removing the oxide layer to thin the transfer substrate film layer, or thinning the transfer substrate layer by adopting a mechanical chemical polishing process to form the semiconductor top layer;
wherein, the definition mode of the characteristic size of the cavity comprises the following steps: defining a two-dimensional plane above the cavity structure parallel to the surface of the cavity structure; in the two-dimensional plane, a plurality of selected points are arranged above the cavity structure; for each said selected point, there are a number of straight lines passing through said selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are respectively adjacent to the selected point in two directions of the straight line extending through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum size of the cavity based on a number of the straight lines passing through each of the selected points; and selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the characteristic size of the cavity.
3. The method of claim 1, wherein the step of forming the cavity-surrounding structure-based field effect transistor comprises: the second pole is surrounded by another annular cavity in the vertical projection direction, and the other annular cavity and the annular cavity share one side cavity.
4. The method for manufacturing a field effect transistor based on a cavity-surrounding structure according to claim 1 or 3, wherein: an annular heavily doped isolation region is also formed in the top semiconductor layer at the periphery of the annular cavity, the conductivity type of the annular heavily doped isolation region is opposite to that of the first pole and the second pole, and a lightly doped region or an undoped region is also formed between the annular heavily doped isolation region and the first pole or/and the second pole.
5. The method of claim 4, wherein the step of forming the cavity-surrounding structure-based field effect transistor comprises: the first pole is located in the annular cavity in the vertical projection direction, the lightly doped region or the undoped region covers the annular cavity in the vertical projection direction and exceeds the edge of the annular cavity, and the annular heavily doped isolation region surrounds the lightly doped region or the undoped region in the vertical projection direction and has a distance with the edge of the annular cavity.
6. The method of claim 1, wherein the step of forming the cavity-surrounding structure-based field effect transistor comprises: one or more annular support structures are arranged in the annular cavity, and the annular support structures are reserved by the insulating layer.
7. The method of claim 1, wherein the step of forming the cavity-surrounding structure-based field effect transistor comprises: the annular cavity is in the shape of a rectangular ring.
8. The utility model provides a field effect transistor based on cavity surrounds structure, its characterized in that, field effect transistor is including the base, insulating layer and the semiconductor top layer that stack gradually, be formed with the bar grid on the semiconductor top layer, be formed with first utmost point and second pole respectively in the semiconductor top layer of bar grid both sides, first one in source and drain electrode, the second pole is another in source and the drain electrode, be formed with annular cavity in the insulating layer, annular cavity surrounds first utmost point on the vertical projection direction, the bar grid is located an edge cavity top of annular cavity, the width in edge cavity is greater than, equals or is less than the width of bar grid, just the edge cavity covers completely on the vertical projection direction the bar grid.
9. The cavity-enclosing-structure-based field effect transistor according to claim 8, wherein: the second pole is surrounded by another annular cavity in the vertical projection direction, and the other annular cavity and the annular cavity share one side cavity.
10. The cavity-enclosing-structure-based field effect transistor according to claim 8 or 9, wherein: an annular heavily doped isolation region is also formed in the top semiconductor layer at the periphery of the annular cavity, the conductivity type of the annular heavily doped isolation region is opposite to that of the first pole and the second pole, and a lightly doped region or an undoped region is also formed between the annular heavily doped isolation region and the first pole or/and the second pole.
11. The cavity-enclosing-structure-based field effect transistor according to claim 10, wherein: the first pole is located in the annular cavity in the vertical projection direction, the lightly doped region or the undoped region covers the annular cavity in the vertical projection direction and exceeds the edge of the annular cavity, and the annular heavily doped isolation region surrounds the lightly doped region or the undoped region in the vertical projection direction and has a distance with the edge of the annular cavity.
12. The cavity-enclosing-structure-based field effect transistor according to claim 8, wherein: one or more annular support structures are arranged in the annular cavity, and the annular support structures are reserved by the insulating layer.
13. The cavity-enclosing-structure-based field effect transistor according to claim 8, wherein: the annular cavity is in the shape of a rectangular ring.
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