CN113871451A - DMOS device and forming method thereof - Google Patents
DMOS device and forming method thereof Download PDFInfo
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- CN113871451A CN113871451A CN202111119225.5A CN202111119225A CN113871451A CN 113871451 A CN113871451 A CN 113871451A CN 202111119225 A CN202111119225 A CN 202111119225A CN 113871451 A CN113871451 A CN 113871451A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002347 injection Methods 0.000 claims abstract description 27
- 239000007924 injection Substances 0.000 claims abstract description 27
- 238000009413 insulation Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 238000002513 implantation Methods 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 22
- 125000001475 halogen functional group Chemical group 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Abstract
The application discloses DMOS device and forming method thereof, the device includes: a substrate on which a gate insulating dielectric layer is formed; the grid electrode is formed on the grid insulation dielectric layer; a lightly doped drain region is formed in the substrate on two sides of the grid electrode, a heavily doped region is formed in the lightly doped drain region, a pocket injection region is formed in the substrate between the lightly doped drain regions, the pocket injection region is in contact with the lightly doped drain region, and the transverse width of the pocket injection region is gradually wider from top to bottom along the thickness direction of the substrate. This application is through forming the pocket injection region in the substrate between the lightly doped drain region of DMOS device, and this pocket injection region is along the direction of the thickness of substrate, and its horizontal width is from last to wider and wider down to form a more gradual knot on the substrate surface, thereby can weaken the impact ionization intensity in the device, improved the breakdown voltage of this device, reduced the off-state leakage current of device simultaneously, improved the electrical property of device.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a DMOS device and a forming method thereof.
Background
A double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) is widely used in a power management circuit because of its characteristics of high voltage resistance, large current driving capability, and extremely low power consumption.
There are two main types of DMOS: a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS, which may be referred to as "VDMOS") and a lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET, which may be referred to as "LDMOS"). For LDMOS devices, the on-resistance (R)sp) Breakdown Voltage (BV) and off-state leakage current (I)off) Is an important parameter for measuring the electrical performance.
Referring to fig. 1, which illustrates a cross-sectional view of an LDMOS device provided in the related art, as shown in fig. 1, a buried oxide layer 102 is formed on a back substrate 101, a top silicon layer 103 is formed on the buried oxide layer 102, a gate insulating dielectric layer 105 is formed on the top silicon layer 103, a gate polysilicon 106 is formed on the gate insulating dielectric layer 105, side walls 109 are grown on two sides of the gate polysilicon 106, a Shallow Trench Isolation (STI) structure 104 is formed in the top silicon layer 103 around an Active Area (AA) of the device, a Lightly Doped Drain (LDD) region 107 is formed in the top silicon layer 103 on two sides of the gate polysilicon 106, a heavily doped region 110 is formed in the lightly doped drain region 107, and a pocket (pocket) implantation region 108 is formed at each facing edge of the lightly doped drain region 107.
In the LDMOS device provided in the related art, the width from the edge of the lightly doped drain region to the edge of the pocket implantation region is substantially the same, and the shape of the pocket implantation region can be regarded as translation of the lightly doped drain region, and when a higher voltage is applied, impact ionization in the device easily occurs at the interface between the lightly doped drain region and the pocket implantation region on the top silicon surface (as shown by a dotted line in fig. 1), so that the ion concentration of the top silicon surface is too high, and the too wide surface region of the pocket implantation region is not favorable for improving the breakdown voltage of the device, reducing off-state leakage current, and further reducing the electrical performance of the device.
Disclosure of Invention
The application provides a DMOS device and a forming method thereof, which can solve the problem that the electrical property of the DMOS device provided in the related technology is poor.
In one aspect, an embodiment of the present application provides a DMOS device, including:
the device comprises a substrate, a grid insulation medium layer and a grid electrode, wherein the grid insulation medium layer is formed on the substrate;
the grid electrode is formed on the grid insulation dielectric layer;
the substrate on two sides of the grid is provided with a lightly doped drain region, a heavily doped region is formed in the lightly doped drain region, a pocket injection region is formed in the substrate between the lightly doped drain regions, the pocket injection region is in contact with the lightly doped drain region, and the transverse width of the pocket injection region is gradually wider from top to bottom along the thickness direction of the substrate.
Optionally, the substrate sequentially includes a back substrate, a buried oxide layer and a top silicon layer from bottom to top;
the lightly doped drain region, the heavily doped region and the pocket injection region are formed in the top silicon.
Optionally, the pocket injection region wraps the surface of the lightly doped drain region between the upper surface of the top silicon and the upper surface of the buried oxide layer.
Optionally, the pocket implantation region is formed by pocket ion implantation or halo ion implantation.
Optionally, the DMOS device is a switching tube DMOS device.
On the other hand, the embodiment of the application provides a method for forming a DMOS device, which includes:
providing a substrate, wherein a gate insulating medium layer is formed on the substrate, a gate electrode is formed on the gate insulating medium layer, and lightly doped drain regions are formed in the substrate on two sides of the gate electrode;
carrying out first ion implantation, forming a pocket implantation region in the substrate between the lightly doped drain regions, wherein the pocket implantation region is in contact with the lightly doped drain regions, and the transverse width of the pocket implantation region is gradually wider from top to bottom along the thickness direction of the substrate;
and carrying out second ion implantation to form a heavily doped region in the lightly doped drain region.
Optionally, the performing of the first ion implantation includes:
the first ion implantation is performed by pocket ion implantation or halo ion implantation.
Optionally, the method may be characterized in that,
optionally, the substrate sequentially includes a back substrate, a buried oxide layer and a top silicon layer from bottom to top;
the lightly doped drain region, the heavily doped region and the pocket injection region are formed in the top silicon.
Optionally, the pocket injection region wraps the surface of the lightly doped drain region between the upper surface of the top silicon and the upper surface of the buried oxide layer.
Optionally, the DMOS device is a switching tube DMOS device.
The technical scheme at least comprises the following advantages:
the pocket injection region is formed in the substrate between the lightly doped drain regions of the DMOS device, the transverse width of the pocket injection region along the thickness direction of the substrate is gradually wider from top to bottom, so that a more gradual junction is formed on the surface of the substrate, the impact ionization strength in the device can be weakened, the breakdown voltage of the device is improved, the off-state leakage current of the device is reduced, and the electrical performance of the device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of an LDMOS device provided in the related art;
fig. 2 is a schematic cross-sectional view of a DMOS device provided by an exemplary embodiment of the present application;
fig. 3 is a flow chart of a method for forming a DMOS device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, which shows a schematic cross-sectional view of a DMOS device according to an exemplary embodiment of the present application, as shown in fig. 2, in an embodiment of the present application, a gate of the DMOS device is rectangular when viewed from a top view, a direction defining a length of the rectangle is an X axis, a direction defining a width of the rectangle is a Y axis, and a direction defining a thickness of a substrate is a Z axis, the DMOS device may be a switching tube DMOS device, which includes:
a substrate having a gate insulating dielectric layer 205 formed thereon.
The substrate may be a silicon substrate, a silicon substrate with an epitaxial layer, or a silicon-on-insulator (SOI) substrate. As shown in fig. 2, the following description will be made taking an insulating silicon substrate as an example: the substrate includes a backside substrate 201, a buried oxide layer 202 and a top silicon 203 in sequence from bottom to top (in the embodiment of the present application, the top is a direction toward a gate 206, and the bottom is a direction toward the backside substrate 201), a gate insulating dielectric layer 205 is formed on a surface of the top silicon 203, and the gate insulating dielectric layer 205 may include silicon oxide (e.g., silicon dioxide (SiO) (silicon dioxide, etc.) (2) Layer(s).
And a gate electrode 206 formed on the gate insulating dielectric layer 205.
A lightly doped drain region 207 is formed in the substrate on both sides of the gate 206, a heavily doped region 210 is formed in the lightly doped drain region 207, a pocket injection region 208 is formed in the substrate between the lightly doped drain regions 207, the pocket injection region 208 is in contact with the lightly doped drain region 207, the pocket injection regions 208 are not in contact with each other, and the lateral width of the pocket injection region 208 (i.e., the wide pier in the X-axis direction) is gradually wider from top to bottom in the Z-axis direction.
Illustratively, as shown in fig. 2, the lightly doped drain region 207, the heavily doped region 210 and the pocket implantation region 208 are formed in the top layer silicon 203, the lateral width of the pocket implantation region 208 is gradually wider from top to bottom along the Z-axis direction, and the pocket implantation region 208 covers the surface of the lightly doped drain region 207 between the upper surface of the top layer silicon 203 and the upper surface of the buried oxide layer 202, so that the pocket implantation region 208 has a narrower width (as shown by the oval dotted line in fig. 2) on the upper surface of the top layer silicon 203, thereby forming a more gradual junction on the surface of the top layer silicon 203, and thus reducing the impact ionization strength in the device.
Wherein, the pocket implantation region 208 is formed by pocket ion implantation or halo ion implantation; the impurity type in the pocket injection region 208 is the same as that in the top layer silicon 203, the impurity type in the lightly doped drain region 207 is different from that in the top layer silicon 203, and the impurity type in the heavily doped region 210 is different from that in the top layer silicon 203; the impurity concentration in the heavily doped region 210 is greater than the impurity concentration in the lightly doped drain region 207 and the impurity concentration in the pocket implant region 208.
When the impurity type in the top silicon 203 is P (positive), the impurity type in the pocket injection region 208 is P, the impurity type in the lightly doped drain region 207 is N (negative), and the impurity type in the heavily doped region 210 is N; when the impurity type in the top silicon 203 is N type, the impurity type in the pocket implantation region 208 is N type, the impurity type in the lightly doped drain region 207 is P type, and the impurity type in the heavily doped region 210 is P type.
Optionally, a Shallow Trench Isolation (STI) structure 204 is formed in the top silicon 203 around an Active Area (AA) of the DMOS device; optionally, spacers 209 are formed on two sides of the gate 206 and the gate insulating dielectric layer 205.
In summary, in the embodiment of the present application, a pocket injection region is formed in a substrate between lightly doped drain regions of a DMOS device, and the pocket injection region is wider and wider from top to bottom along the thickness direction of the substrate, so that a more gradual junction is formed on the surface of the substrate, thereby weakening the impact ionization strength in the device, improving the breakdown voltage of the device, reducing the off-state leakage current of the device, and improving the electrical performance of the device.
Referring to fig. 3, a method for forming a DMOS device provided in an exemplary embodiment of the present application is shown, and the method may be applied to the manufacture of the DMOS device provided in the embodiment of fig. 2, and includes:
And 302, performing first ion implantation to form a pocket implantation region in the substrate between the lightly doped drain regions, wherein the pocket implantation region is in contact with the lightly doped drain regions, and the transverse width of the pocket implantation region is gradually wider from top to bottom along the thickness direction of the substrate.
Wherein the impurity of the first ion implantation comprises Boron Fluoride (BF)2) And boron (B) for controlling the implantation energy of boron fluoride to 30 kilo-electron-volts (KeV) to 100 kilo-electron-volts (keV), the implantation energy of boron to 10 kilo-electron-volts (keV) to 40 keV, and the implantation dose of impurities to 5X 1012To 1X 1014The tilt angle of the ion implantation is controlled to be 10 degrees (°) to 45 degrees per square centimeter to form the topography of the pocket implant region 208 in the embodiment of the present application.
The DMOS device obtained by formation may refer to the embodiment of fig. 2, and details thereof are not described herein.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (11)
1. A DMOS device, comprising:
the device comprises a substrate, a grid insulation medium layer and a grid electrode, wherein the grid insulation medium layer is formed on the substrate;
the grid electrode is formed on the grid insulation dielectric layer;
the substrate on two sides of the grid is provided with a lightly doped drain region, a heavily doped region is formed in the lightly doped drain region, a pocket injection region is formed in the substrate between the lightly doped drain regions, the pocket injection region is in contact with the lightly doped drain region, and the transverse width of the pocket injection region is gradually wider from top to bottom along the thickness direction of the substrate.
2. The device of claim 1, wherein the substrate comprises a back substrate, a buried oxide layer and a top silicon layer from bottom to top.
The lightly doped drain region, the heavily doped region and the pocket injection region are formed in the top silicon.
3. The device of claim 2, wherein the pocket implant region wraps a surface of the lightly doped drain region between an upper surface of the top silicon and an upper surface of the buried oxide layer.
4. The device of claim 3, wherein the pocket implant region is formed by pocket ion implantation or halo ion implantation.
5. The device of any of claims 1 to 4, wherein said DMOS device is a switch-transistor DMOS device.
6. A method of forming a DMOS device, comprising:
providing a substrate, wherein a gate insulating medium layer is formed on the substrate, a gate electrode is formed on the gate insulating medium layer, and lightly doped drain regions are formed in the substrate on two sides of the gate electrode;
carrying out first ion implantation, forming a pocket implantation region in the substrate between the lightly doped drain regions, wherein the pocket implantation region is in contact with the lightly doped drain regions, and the transverse width of the pocket implantation region is gradually wider from top to bottom along the thickness direction of the substrate;
and carrying out second ion implantation to form a heavily doped region in the lightly doped drain region.
7. The method of claim 6, wherein said performing a first ion implantation comprises:
the first ion implantation is performed by pocket ion implantation or halo ion implantation.
8. The method of claim 7,
9. the method of claim 8, wherein the substrate comprises a back substrate, a buried oxide layer and a top silicon layer from bottom to top;
the lightly doped drain region, the heavily doped region and the pocket injection region are formed in the top silicon.
10. The method of claim 9, wherein the pocket implant region wraps around a surface of the lightly doped drain region between an upper surface of the top silicon and an upper surface of the buried oxide layer.
11. The method of any of claims 6 to 10, wherein said DMOS device is a switching tube DMOS device.
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| CN202111119225.5A CN113871451A (en) | 2021-09-24 | 2021-09-24 | DMOS device and forming method thereof |
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| CN202111119225.5A CN113871451A (en) | 2021-09-24 | 2021-09-24 | DMOS device and forming method thereof |
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| CN113380870A (en) * | 2020-02-25 | 2021-09-10 | 长鑫存储技术有限公司 | Semiconductor device manufacturing method |
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