CN215731731U - Super junction power MOSFET - Google Patents
Super junction power MOSFET Download PDFInfo
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- CN215731731U CN215731731U CN202120976676.XU CN202120976676U CN215731731U CN 215731731 U CN215731731 U CN 215731731U CN 202120976676 U CN202120976676 U CN 202120976676U CN 215731731 U CN215731731 U CN 215731731U
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Abstract
The application discloses super junction power MOSFET, on MOSFET's cross-section, it includes: a semiconductor substrate having a first main surface and a second main surface disposed oppositely; a drain electrode provided on the first main surface; the first conductive type region is arranged on the second main surface and comprises n second conductive type regions and n grooves, n is a positive integer, the second conductive type regions are arranged at intervals along the horizontal direction, the first conductive type regions and the second conductive type regions between the second conductive type regions form a super junction structure, the grooves are correspondingly arranged on the second conductive type regions, and the bottoms of the grooves are in contact with the second conductive type regions; a grid electrode oxidation layer is arranged along the groove and the plane between the grooves, the plane and the groove opening are positioned on the same horizontal plane, the groove is filled with a groove grid electrode, and the grid electrode oxidation layer on the plane is provided with a plane grid electrode; and a source electrode is arranged on the trench gate electrode. The MOSFET has ultra-low capacitance and more optimized FOM.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a super junction power MOSFET and a preparation method thereof.
Background
The power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a multi-sub conductive device and has the advantages of high switching speed, high input impedance, easiness in driving, no secondary breakdown phenomenon and the like. An ideal power MOSFET should have low on-resistance, switching losses and high blocking voltage; the development of power MOSFETs is limited due to the pinning between their on-resistance and breakdown voltage. The main current implementations for improving the performance (e.g., power, frequency) of power MOSFETs include: the MOSFET with optimized performance by improving the device structure mainly comprises a trench gate VDMOS (Vertical Double-diffused metal-oxide-semiconductor field effect transistor) and a DMOS (Double-diffused metal-oxide-semiconductor field effect transistor). However, in the field of high-voltage application, the thickness of an epitaxial layer of the power VDMOS is continuously increased and the doping concentration is gradually reduced with the increase of the breakdown voltage, so that the on-resistance is sharply increased to the power of 2.5 with the increase of the breakdown voltage, and the on-state power consumption is increased.
With the proposal of the theory of a new structure of a longitudinal voltage-resisting layer (namely, a voltage-resisting structure of a super junction), the silicon limit theory is broken through, and the theory of charge compensation is utilized. As shown in fig. 1, the drift region of the conventional super junction power MOSFET generally consists of a series of P-type regions and N-type regions arranged alternately in the lateral direction; when reverse bias voltage is applied, a longitudinal electric field and a transverse electric field exist in the device between the two well regions; although the P-type region and the N-type region can be completely depleted before breakdown, the on-resistance can be reduced without reducing the breakdown voltage; it still fails to meet the performance requirements for power MOSFETs in high voltage applications.
Therefore, a super junction power MOSFET with better performance is urgently needed to be developed.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides a super junction power MOSFET to improve the performance of existing super junction power MOSFETs.
The application provides a super junction power MOSFET, on the cross section of MOSFET, the MOSFET includes: a semiconductor substrate having first and second oppositely disposed major surfaces; a drain electrode provided on the first main surface; the first conduction type region is arranged on the second main surface and comprises n second conduction type regions and n grooves, n is a positive integer, the second conduction type regions are arranged at intervals along the horizontal direction, the first conduction type regions and the second conduction type regions between the second conduction type regions form a super junction structure, the grooves are correspondingly arranged on the second conduction type regions, and the bottoms of the grooves are in contact with the second conduction type regions; a grid electrode oxidation layer is arranged along the groove and a plane between the grooves, the plane and the groove opening are positioned on the same horizontal plane, the groove is filled with a groove grid electrode, and the grid electrode oxidation layer on the plane is provided with a plane grid electrode; and a source electrode is arranged on the trench gate electrode.
In some embodiments, the second conductive type region is formed of a plurality of sub second conductive type regions arranged consecutively in a vertical direction.
In some embodiments, the groove is a U-shaped groove.
In some embodiments, a passivation layer is disposed on the gate oxide layer on the plane to cover the plane gate; and a source electrode is arranged on the passivation layer and is connected with the groove grid electrode through a contact hole.
In some embodiments, the first conductive type region is provided with 2n second conductive type body regions, and the second conductive type body regions are arranged on two sides of the trench and connected with the gate oxide layer.
In some embodiments, the first conductive type region is provided with 2n first conductive type source regions, and the first conductive type source regions are provided at two sides of the trench and filled in a region surrounded by the second conductive type body region and the gate oxide layer.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
In some embodiments, the drain is a metal electrode; and/or the source electrode is an aluminum electrode or a copper electrode; and/or the groove grid and the plane grid are both polysilicon grids.
In some embodiments, the first conductive type region is a phosphorus doped first conductive type region; and/or the second conductive type region is a phosphorus-doped first conductive type region implanted with boron; and/or the grid oxide layer is a silicon dioxide layer.
In some embodiments, the passivation layer is a boron phosphorus silicate glass and silicon dioxide mixed material layer.
In some embodiments, the body region of the second conductivity type is a phosphorus doped first conductivity type region implanted with boron; and/or the first conduction type source region is a phosphorus-doped first conduction type region implanted with arsenic and/or phosphorus.
By arranging a trench gate (i.e., a source gate) connected to the source electrode on the second conductivity type region of the super junction structure, in combination with the arranged planar gate (i.e., a common gate), the advantageous effects are produced: (1) the trench gate and the super junction structure can generate a charge compensation effect simultaneously, so that the resistivity of the super junction structure under the required withstand voltage is greatly reduced, and the on-resistance (rds (on)) can be reduced; (2) when the super-junction structure is prepared by epitaxial growth, the number of layers of the super-junction epitaxial layer can be reduced, and the required voltage resistance can be achieved by using fewer epitaxial layers under the same voltage resistance requirement; (3) based on the fact that capacitance is determined by a gate oxide layer, a trench gate structure can increase the charge amount Of the gate oxide layer, and the provided trench gate connected with a source can greatly reduce gate-drain capacitance (Cgd) and gate-source capacitance (Cgs), so that gate-drain charge (Qgd) can be reduced, switching speed is increased, and a super-junction power MOSFET has a more optimized quality Factor (FOM) (Rds (on)) Of FOM. Therefore, the super-junction power MOSFET provided with the groove grid connected with the source electrode in the second conductive type area of the super-junction structure can reduce the number of epitaxial layers for preparing the super-junction structure through epitaxial growth, reduce the on-resistance of a device, optimize the FOM of the device and have ultralow capacitance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure diagram of a super junction power MOSFET in the prior art;
fig. 2 is a schematic cross-sectional structure diagram of a super junction power MOSFET of the first embodiment of the present application;
fig. 3 is a schematic cross-sectional structure diagram of a super junction power MOSFET according to a second embodiment of the present application.
Each reference numeral represents: 1. a drain electrode; 2. a semiconductor substrate; 3. a first conductive type region; 4. a second conductive type region; 5. a trench; 6. a gate oxide layer; 7. a trench gate; 8. a planar gate; 9. a source electrode; 10. a body region of a second conductivity type; 11. a source region of a first conductivity type; 12. a contact hole; 13. a passivation layer; 21. a first major surface; 22. a second major surface; 41. and a sub second conductive type region.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Referring to fig. 2, the present application provides a super junction power MOSFET comprising, in cross-section of the MOSFET: a semiconductor substrate 2, the semiconductor substrate 2 having a first main surface 21 and a second main surface 22 disposed oppositely; a Drain (Drain, D)1 provided on the first major surface 21; a first conductive type region 3 disposed on the second main surface 22, where the first conductive type region 3 includes n second conductive type regions 4 and n trenches 5, where n is a positive integer, the second conductive type regions 4 are disposed at intervals along a horizontal direction, the first conductive type region 3 between the second conductive type regions 4 and the second conductive type region 4 form a super junction structure, the trenches 5 are correspondingly disposed on the second conductive type regions 4, and bottoms of the trenches 5 are in contact with the second conductive type regions 4; a Gate (Gate, G) oxide layer 6 is arranged along the plane between the trench 4 and the trench, the plane and the opening of the trench 5 are positioned on the same horizontal plane, the trench 5 is filled with a trench Gate 7, and a planar Gate 8 is arranged on the Gate oxide layer on the plane; and a source electrode 9 is arranged on the trench gate 7.
Specifically, a super junction structure is formed by arranging n second conductivity type regions 4 at intervals in the horizontal direction in the first conductivity type region 3 so that the first conductivity type regions between the second conductivity type regions 4 and the second conductivity type regions are alternately arranged; it should be understood that the shapes of the first conductive type region 3 and the second conductive type region 4 are not limited herein, and the second conductive type region 4 may be a pillar shape or a shape matching a shape of a candied gourd, for example, and the first conductive type region 3 between two adjacent second conductive type regions 4 may be a pillar shape or a shape matching a shape of a candied gourd. By providing trench gate 7 (i.e., source gate) connected to source 9 on second conductivity type region 3 of the super junction structure, the method is such that: (1) the trench gate 7 and the super junction structure (composed of the first conductive type region 3 and the second conductive type region 4 which are alternately arranged) can simultaneously generate a charge compensation effect, so that the resistivity of the super junction structure required to withstand voltage is greatly reduced, and the on-resistance (rds (on)) can be reduced. (2) When the super-junction structure is prepared by epitaxial growth, the number of layers of the super-junction epitaxial layer can be reduced, and the required voltage resistance can be achieved by using fewer epitaxial layers under the same voltage resistance requirement. (3) Based on the capacitance determined by the gate oxide, the trench gate 7 can increase the charge amount Of the gate oxide 6, and the trench gate 7 connected to the source 9 can greatly reduce the gate-drain capacitance (Cgd) and the gate-source capacitance (Cgs), thereby reducing the gate-drain charge (Qgd) and increasing the switching speed, so that the super-junction power MOSFET has a better quality Factor (FOM) (FOM ═ rds (on)) Of the net-write (FOM). Therefore, the super junction power MOSFET provided with the trench gate 7 of the present embodiment can reduce the number of epitaxial layers for preparing a super junction structure by epitaxial growth, reduce the on-resistance of the device, optimize the FOM of the device, and have an ultra-low capacitance.
In some embodiments, the first conductive type region 3 may be, but is not limited to, a first conductive type epitaxial layer, and in this case, the super junction power MOSFET can reduce the number of epitaxial layers; illustratively, the first conductive type region 3 may be a first conductive type epitaxial layer doped with phosphorus.
In some embodiments, the second conductive type region 4 is composed of a plurality of sub second conductive type regions 41 arranged in series in the vertical direction. Illustratively, the sub second conductive type region 41 may be an ellipsoid type, and the second conductive type region 4 has a structure similar to a shape of a sugar gourd.
In some embodiments, the groove 5 is a U-shaped groove. Set up slot 5 into U type groove, for V type groove or bar groove, can prevent the electric leakage of slot bottom to prevent that the device from becoming invalid, be favorable to prolonging the life of device.
Referring also to fig. 3, in some embodiments, a passivation layer 13 is disposed on the planar gate oxide 6 to cover the planar gate 8; the passivation layer 13 is provided with a source electrode 9, and the source electrode 9 is connected with the trench gate 7 through a contact hole 12. By arranging the passivation layer 13, the surface planarization of the semiconductor substrate 2 can be improved, and a larger process range is provided for photoetching arrangement of contact holes; in addition, the passivation layer 13 can provide reliable protection for the entire device when the device is subjected to various environmental stresses.
In some embodiments, the first conductive type region 3 is provided with 2n second conductive type body regions 10, and the second conductive type body regions 10 are provided on two sides of the trench 5 and connected to the gate oxide layer 6.
In some embodiments, the first conductive type region 3 is provided with 2n first conductive type source regions 11, and the first conductive type source regions 11 are disposed on two sides of the trench 5 and filled in a region surrounded by the second conductive type body region 10 and the gate oxide layer 6.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
In some embodiments, the semiconductor substrate 2 may be, but is not limited to, a silicon-based semiconductor substrate, and the semiconductor substrate 2 is, for example, a silicon wafer.
In some embodiments, the drain (D)1 may be, but is not limited to, a metal electrode; and/or, the Source (S) 9 may be, but is not limited to, an aluminum electrode or a copper electrode; and/or the trench gate 7 and the planar gate 8 are both polysilicon gates.
In some embodiments, the first conductive type region 3 may be, but is not limited to, a phosphorus doped first conductive type region; and/or, the second conductive type region 4 may be, but is not limited to, a phosphorus-doped first conductive type region implanted with Boron (Boron, B); and/or, the gate oxide layer 6 may be, but is not limited to, a silicon dioxide layer.
In some embodiments, the passivation layer 13 may be borophosphosilicate Glass (BPSG) and silicon dioxide (SiO)2) Mixing the material layers.
In some embodiments, the body region 10 of the second conductivity type may be a phosphorus-doped first conductivity type region implanted with boron (B); and/or, the source region 11 of the first conductive type may be a phosphorus-doped first conductive type region implanted with arsenic (As) and/or phosphorus (P).
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "top", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (11)
1. A super junction power MOSFET, characterized in that, in a cross section of the MOSFET, the MOSFET comprises:
a semiconductor substrate having first and second oppositely disposed major surfaces;
a drain electrode provided on the first main surface;
the first conduction type region is arranged on the second main surface and comprises n second conduction type regions and n grooves, n is a positive integer, the second conduction type regions are arranged at intervals along the horizontal direction, the first conduction type regions and the second conduction type regions between the second conduction type regions form a super junction structure, the grooves are correspondingly arranged on the second conduction type regions, and the bottoms of the grooves are in contact with the second conduction type regions;
a grid electrode oxidation layer is arranged along the groove and a plane between the grooves, the plane and the groove opening are positioned on the same horizontal plane, the groove is filled with a groove grid electrode, and the grid electrode oxidation layer on the plane is provided with a plane grid electrode;
and a source electrode is arranged on the trench gate electrode.
2. The super-junction power MOSFET of claim 1 wherein the second conductivity type region is comprised of a plurality of sub-second conductivity type regions arranged contiguously in a vertical direction.
3. The super junction power MOSFET of claim 1 wherein the trench is a U-shaped trench.
4. The super junction power MOSFET of claim 1 wherein a passivation layer is provided on the gate oxide layer on the plane overlying the planar gate; and a source electrode is arranged on the passivation layer and is connected with the groove grid electrode through a contact hole.
5. The super-junction power MOSFET of claim 1 wherein the first conductivity type region is provided with 2n body regions of the second conductivity type, the body regions of the second conductivity type being provided on both sides of the trench and connected to the gate oxide layer.
6. The super junction power MOSFET of claim 5, wherein the first conductivity type region is provided with 2n first conductivity type source regions, the first conductivity type source regions are provided at two sides of the trench, and filled in a region surrounded by the second conductivity type body region and the gate oxide layer.
7. The super junction power MOSFET of claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first and second electrodes may be,
the first conductive type is a P type, and the second conductive type is an N type.
8. The super junction power MOSFET of claim 1 wherein the drain is a metal electrode; and/or the presence of a gas in the gas,
the source electrode is an aluminum electrode or a copper electrode; and/or the presence of a gas in the gas,
the groove grid and the plane grid are both polysilicon grids.
9. The super junction power MOSFET of claim 1 wherein the first conductivity type region is phosphorus doped; and/or the presence of a gas in the gas,
the second conductive type region is a phosphorus-doped first conductive type region implanted with boron; and/or the presence of a gas in the gas,
the grid oxide layer is a silicon dioxide layer.
10. The super junction power MOSFET of claim 4, wherein the passivation layer is a mixed material layer of borophosphosilicate glass and silicon dioxide.
11. The super junction power MOSFET of claim 6 wherein the body region of the second conductivity type is a phosphorus doped first conductivity type region implanted with boron; and/or the presence of a gas in the gas,
the source region of the first conduction type is a phosphorus-doped first conduction type region implanted with arsenic and/or phosphorus.
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| CN115148791A (en) * | 2022-09-05 | 2022-10-04 | 深圳市威兆半导体股份有限公司 | Super junction MOSFET |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115148791A (en) * | 2022-09-05 | 2022-10-04 | 深圳市威兆半导体股份有限公司 | Super junction MOSFET |
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Address after: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee after: Shenzhen Weizhao Semiconductor Co.,Ltd. Address before: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee before: VANGUARD SEMICONDUCTOR CO.,LTD. |