KR20030097344A - Method for fabrication of cmos transistor - Google Patents

Abstract

PURPOSE: A method for fabricating complementary metal oxide semiconductor(CMOS) transistor is provided to maximize a current flow by arbitrarily controlling the junction depth of a source/drain. CONSTITUTION: N-type impurities are selectively injected into a PMOS transistor formation portion of a p-type semiconductor substrate(10) to form an N-well(11). After a silicon oxide layer(12) is deposited on the semiconductor substrate, the silicon oxide layer in a channel formation region is patterned. A single crystal silicon layer(13) is grown on the channel formation region by an epitaxial growth process. The first polysilicon layer(14) that is not doped is grown on the silicon oxide layer. A thick field oxide layer(15) is formed on an interface between the silicon substrate and the N-well. A gate oxide layer(16) and the second polysilicon layer(17) are formed on the resultant structure having the field oxide layer and are patterned to form a gate. A low density impurity ion implantation process is performed. After a spacer(18) is formed on the side surface of the gate, a high density impurity ion implantation process is performed. An interlayer dielectric(19) is deposited on the resultant structure. After an etch process is performed until the silicon oxide layer is sufficiently exposed to form a contact hole, a metal barrier layer(20) is deposited. Tungsten is deposited on the metal barrier layer and is etched back to form a tungsten plug(21). After all of the tungsten on the interlayer dielectric is eliminated by an etch-back process, a metal interconnection(22) is formed.

Description

CMOS transistor manufacturing method {METHOD FOR FABRICATION OF CMOS TRANSISTOR}

The present invention relates to a method of manufacturing a CMOS transistor, and more particularly, to a method of manufacturing a CMOS transistor, which is intended to maximize the efficiency of current flow and to minimize junction capacitance by easily adjusting the junction depth and uniformly doping the source / drain regions. It relates to a manufacturing method.

In general, a CMOS transistor is doped with n-type impurities so as to exhibit conductivity in a polysilicon film as gate electrodes of NMOS and PMOS. As a result, the NMOS transistor operates in a surface channel mode in which a channel is formed near the substrate surface, and in the case of a PMOS transistor, in a buried channel mode in which a channel is formed at a portion deeper than the substrate surface. It will work.

However, as the degree of integration of semiconductor devices increases, the gate length of MOS transistors also decreases. Recently, a device design has been made to have a gate length of about 0.2 μm or less for a 1 Giga-class dynamic random access memory (DRAM) device. The reduced channel length also shortens the effective channel length, so that the channel region is strongly influenced by the depletion layer charge, electric field, and potential distribution of the source / drain regions as well as the gate voltage. effect occurs, and the short-channel effect is accompanied by a decrease in threshold voltage, a decrease in source / drain breakdown voltage, and a decrease in sub-threshold characteristics.

Therefore, in the case of a PMOS transistor having a gate doped with n-type impurities, the characteristics of the short-channel effect are deteriorated, so that the implementation of a shallow junction is inevitable.

Conventionally, a method of reducing ion implantation energy has been used to form such a shallow junction, but the source and drain regions thus formed are not doped uniformly, so that the area through which current can effectively pass through the entire depth is reduced, resulting in inefficient efficiency. there was.

In addition, a certain degree of transient etching is inevitable for reliable contact with the shallow junction, which damages the substrate, and the current density is concentrated toward the gate of the formed metal junction area, resulting in parasitic capacitance at the junction, thereby degrading device characteristics. There was a problem.

In order to solve the above problems, the present invention grows a silicon oxide film in a predetermined region of a semiconductor substrate on which a well is formed, forms a single crystal silicon film on an exposed semiconductor substrate, and then converts ions from the well into a single crystal silicon film during field oxide film growth. Diffusion and source / drain are formed in the polysilicon film, contact holes are formed through the source / drain region to the silicon oxide film at the bottom, and metal wiring is formed to easily control the junction depth and the oxide film is used as a diffusion barrier. To provide a method of fabricating a CMOS transistor that can be uniformly doped source / drain region to maximize the current flow and to minimize the junction capacitance.

1A to 1H are cross-sectional views illustrating a process of fabricating a CMOS transistor according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10 semiconductor substrate 11 N-well

12 silicon oxide film 13 single crystal silicon film

14 first polysilicon film 15 field oxide film

16 gate oxide film 17 second polysilicon film

18 spacer 19 interlayer insulating film

20 metal barrier layer 21 tungsten plug

22: metal wiring

In order to achieve the above object, the present invention provides a method of forming an N-well by selectively injecting n-type impurities into a portion where a PMOS transistor is to be formed on a p-type semiconductor substrate, and depositing a silicon oxide film on the semiconductor substrate. Patterning a silicon oxide film in a region where a channel is to be formed later, growing a single crystal silicon film in an epitaxial growth process in the region where the channel is to be formed, and growing a undoped first polysilicon film on the silicon oxide film; Forming a thick field oxide film on the silicon substrate and the N-well boundary region, forming a gate oxide film and a second polysilicon film on the resultant field on which the field oxide film is formed, patterning the gate, and implanting a low concentration of impurity ions; And a spacer is formed on the side of the gate, and then a high concentration of impurities are removed. Implanting, depositing an interlayer insulating film on the resultant of the high concentration ion implantation, etching until the silicon oxide film is sufficiently exposed to form a contact hole, and then depositing a metal barrier layer; Depositing tungsten on the metal barrier layer and etching back to form a tungsten plug; and removing all the tungsten on the interlayer insulating film by an etch back process to form a metal wiring. It is about.

The field oxide film is formed by using an STI process of forming a trench at a depth of 2000 to 3000 kW using a chlorine-based gas.

In the low and high concentration impurity ion implantation process, an N-type low concentration impurity ion is implanted in the NMOS region on the first polysilicon layer, and the PMOS region is implanted with a P-type impurity ion using a mask.

The interlayer insulating film is characterized by depositing a TEOS film and a BPSG film, the TEOS film is characterized in that the BPSG film is deposited in a thickness of 8000 ~ 9000 Å with a thickness of 1000 ~ 15001.

The Ti / TiN film is deposited to a thickness of 500 mW / 1000 mW as the metal barrier.

The tungsten may be formed to a thickness of 5000 to 6000 kPa by a gap peeling process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

1A to 1H are cross-sectional views illustrating a process of fabricating a CMOS transistor according to the present invention.

First, as shown in FIG. 1A, an N-well 11 is formed by selectively implanting n-type impurities into a portion where a PMOS transistor is to be formed in the p-type semiconductor substrate 10, and then depositing a silicon oxide film 12. Subsequently, as shown in FIG. 1B, the silicon oxide film 12 in the region A in which the channel is to be formed is patterned using a gate mask (not shown).

Subsequently, as shown in FIG. 1C, the single crystal silicon film 13 is grown in the region A where the channel is to be formed by the epitaxial growth process, and the undoped first polysilicon film 14 is formed on the silicon oxide film 12. Grow).

Then, as shown in FIG. 1D, a trench is formed at a depth of 2000 to 3000 kW using a chlorine-based gas through a shallow trench isolation (STI) process in the silicon substrate and the N-well boundary region to isolate the active region. Afterwards, the field oxide film 15 is formed thick.

At this time, the field oxide film 15 allows the ions of the silicon substrate 10 and the N-well to be externally diffused and doped with a single crystal silicon film to be used as a channel.

Subsequently, as shown in FIG. 1E, the gate oxide film 16 and the second polysilicon film 17 are formed and patterned to form a gate, and then a low concentration of impurity ions are implanted.

At this time, N-type low concentration impurity ions are implanted into the NMOS region on the first polysilicon film 14, and P-type impurity ions are implanted into the PMOS region using a mask.

Subsequently, after the spacer 18 is formed on the side of the gate, a high concentration of impurities are implanted by an ion implantation process using the same method as the low concentration impurity implantation process.

Subsequently, as shown in FIG. 1F, a TEOS film is deposited with an interlayer insulating film 19 to a thickness of 1000 to 1500 kPa, a BPSG film is deposited to a thickness of 8000 to 9000 kPa, and the contact hole is formed by etching until the silicon oxide film 12 is sufficiently exposed. Then, as shown in FIG. 1G, a Ti / TiN film is deposited to a thickness of 500 mW / 1000 mW with the metal barrier layer 20.

Subsequently, as shown in FIG. 1H, the tungsten 22 having excellent step coverage is deposited on the metal barrier layer 20 so as to have a thickness of 5000 to 6000 GPa, and all the tungsten on the interlayer insulating film 19 is etched through an etch back process. After removal, the wiring 22 is formed through a metal wiring process.

As described above, the present invention can arbitrarily adjust the source / drain junction depth to maximize the efficiency of current flow by uniform doping, and the low concentration impurity region completely separates the high concentration impurity region and the channel, thereby providing a hot carrier effect and There is an advantage that can improve the problems of latch-up and punch-through.

In addition, since the metal contacts exist in the depth direction of the source / drain regions, parasitic resistances can be suppressed to the maximum in the flow of current, thereby improving current driving capability without current concentration, and improving parasitic capacitance in the source / drain regions. It is possible to prevent the speed drop caused by the RC delay to improve the operation speed of the device.

Claims (7)

selectively implanting n-type impurities into a portion where the PMOS transistor is to be formed on the p-type semiconductor substrate to form an N-well; Depositing a silicon oxide film on the semiconductor substrate at all times and patterning the silicon oxide film in a region where a channel is to be formed; Growing a single crystal silicon film in an epitaxial growth process in the region where the channel is to be formed, and growing a undoped first polysilicon film on the silicon oxide film; Forming a thick field oxide film on the silicon substrate and the N-well boundary region; Forming a gate by forming and patterning a gate oxide film and a second polysilicon film on the resultant on which the field oxide film is formed, and performing impurity ion implantation at a low concentration; Forming a spacer on a side of the gate and ion implanting a high concentration of impurities; Depositing an interlayer insulating film on the resultant of the high concentration ion implantation; Etching until the silicon oxide film is sufficiently exposed to form contact holes, and then depositing a metal barrier layer; Depositing tungsten on the metal barrier layer and etching back to form a tungsten plug; After removing all the tungsten on the interlayer insulating film by an etch back process to form a metal wiring CMOS transistor manufacturing method comprising a. 2. The method of claim 1, wherein the field oxide film is formed using an STI process that forms a trench at a depth of 2000-3000 kW using a chlorine-based gas. The method of claim 1, wherein the low concentration and high concentration impurity ion implantation is performed by implanting N-type low concentration impurity ions onto the first polysilicon film in an NMOS region, and P-type impurity ion implantation using a mask in a PMOS region. A CMOS transistor manufacturing method characterized by the above-mentioned. The method of claim 1, wherein the interlayer insulating film is deposited with a TEOS film and a BPSG film. The method of claim 4, wherein the TEOS film is deposited at a thickness of 1000-1500 kV and the BPSG film is deposited at a thickness of 8000-9000 kPa. A method of manufacturing a CMOS transistor according to claim 1, wherein a Ti / TiN film is deposited to a thickness of 500 mW / 1000 mW with the metal barrier. The method of claim 1, wherein the tungsten is formed to a thickness of 5000 to 6000 kV by a gap peeling process.