CN101027948A - 电子模块及其制造方法 - Google Patents

电子模块及其制造方法 Download PDF

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Publication number
CN101027948A
CN101027948A CNA2005800133303A CN200580013330A CN101027948A CN 101027948 A CN101027948 A CN 101027948A CN A2005800133303 A CNA2005800133303 A CN A2005800133303A CN 200580013330 A CN200580013330 A CN 200580013330A CN 101027948 A CN101027948 A CN 101027948A
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China
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contact
material layer
insulation material
electronic module
conductor
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CN101027948B (zh
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R·托米南
A·伊霍拉
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Imberatec Co., Ltd
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Imbera Electronics Oy
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49218—Contact or terminal manufacturing by assembling plural parts with deforming

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Abstract

本发明公开了一种电子模块及其制造方法。该电子模块包括嵌入在绝缘材料层(1)中的至少一个元件(6)，该元件具有第一接触表面，在该第一接触表面上具有第一接触端子(7)，该元件(6)从该接触端子与包含在该电子模块内的导体结构电连接。另外，该元件(6)具有与第一接触表面相对的第二接触表面，该第二接触表面上具有至少一个第二接触端子(7’)，该元件(6)从该第二接触端子与包含在该电子模块内的导体结构电连接。借由本发明，可获得一种相对于现有技术更节省空间的电子模块结构。

Description

电子模块及其制造方法
技术领域
本发明涉及一种如权利要求1所述的电子模块，该电子模块包含嵌入元件。
这种电子模块可以是如电路板的模块，其中所包含的元件之间通过在电子模块中制造的导电结构互相电连接。本发明特别涉及一种包含微电路的电子模块，几个接触端子与其连接。也可以采用其他元件，比如无源元件，与微电路组合或代替微电路，嵌入到电子模块的安装基底内。
除此之外，本发明涉及一种如权利要求12的前序部分所述的用于制造这种电子模块的方法。
背景技术
在安装基底生产的过程中将元件嵌入到安装基底的公知方法已经在专利申请WO 03/065778和WO 03/065779以及专利公开US 6038133和US 6489685中披露。在已经披露的方法的帮助下，可以制造诸如内部嵌入了集成式微电路的多层电路板，该微电路例如为微处理器和存储电路。元件与安装基底表面上的导电结构借由通孔电连接。专利公开US 6292366披露了一种包括刚性层的电路板，该电路板由互相叠置的两个铝片制成，相邻放置的微电路贴附于刚性层，这样他们的接触点就在相对的方向。由于这种结构，微电路能够被设置成2层并且在作为安装基底的金属片的两侧上直接连接。
在上述公开的文件披露的技术中，使用了元件，该元件具有一个接触表面，也就是他们的接触端基本上位于元件的一侧。这些接触端只能够与基底的一个表面的导电结构和接触表面直接连接，来产生元件之间的电连接和到外部模块的电连接。如果想要这种元件与基底的另外一个表面也电连接，就必须通过单独的通孔实现。为防止损坏元件，通孔不能够制造在板上的元件位置，因而通孔会占据电路板的空间。如果元件设置为双层，为了优化电路板表面区域的使用，电子模块结构可能会不利地变厚且复杂以致难于制造。因此，在许多以最小化电子产品的尺寸为目的的应用中，包含嵌入元件的电路板并不是最理想的。
因此，工业上急需通过将置于其中的元件所占空间减小来减小电路板尺寸。
发明内容
本发明意在制造一种电子模块结构，相比现有技术节省更多空间。
本发明是基于这样的构思，在绝缘材料层内嵌入具有第一接触表面和与第一接触表面相对的第二接触表面的元件，该第一接触表面上具有第一接触端，该第二接触表面上具有至少一个第二接触端。另外，该元件从其接触端电连接到包含在该电子模块内的导电结构。
优选的，该元件第一接触表面上的接触端与基底的第一表面的导体结构直接接触，并且该元件第二接触表面上的接触端与基底的第二表面上的导体结构直接接触。
首先，一元件可被放置在形成基底的第一表面的第一导体层上，之后绝缘材料和用于形成基底第二表面的导体层放置到基底的第一表面上，使得绝缘材料围绕所述元件。可以穿过位于该绝缘层的两个面上的导体层制造孔，直到元件的接触端表面的水平面，并且可以将另外的绝缘材料放置到这些孔中，以便将元件与导体层电连接。最后，可以将所需的电路图案制造在该基底的两个面上的导体层中。
更具体地，根据本发明所述的电子模块的特征在于权利要求1特征部分所阐述的内容。
另外，根据本发明的电子模块制造方法的特征在于权利要求12所阐述的内容。
在本发明的帮助之下可以获得很大的优点。
诸如微处理器或者存储电路的待嵌入的元件可以包括，例如几十或者几百个接触端，因此考虑到电路的尺寸，在元件的两侧都制造接触端通常是有利的。依据本发明的电子模块中，利用这种双面元件，可使得模块变薄，同时元件和电子模块的表面区域都能够得到有效利用。
根据一个实施例，所述元件可以粘贴在该第一导体层上。该粘合剂可以是绝缘的，也可以是各向同性或者各向异性导电的。
根据一个实施例，可能在接触区中的粘合剂中包含的颗粒被用于在元件和电子模块之间建立电接触，而通常情况下这些接触借助于热压形成。通常根据应用，电接触不仅仅可以借助于导电粘合剂实现，也可以借助冶金结合(例如超声结合或者热压)，或者甚至焊料来实现。也可以在产生电接触后，将可用的粘合剂放置在元件和导体层之间。
根据一些实施例，在附着元件之前，在形成基底的第一和/或第二表面的导体层中，在元件接触端的位置形成通孔。这是可能的，因为已经非常精确的知道了元件两侧的接触端的位置。同时这使得元件的接触端和导体层之间能更可靠的接触。
在一些实施例中，在被嵌入元件的两个表面上具有类似的接触端图形，因而相似的接触端图形可以在基底的两个表面上制造。若干这种电子模块还可以进一步彼此叠置连接，以形成一个可操作的整体，这带来了对于电子模块进行有效设计的新机会。即使互相贴附的导体层的接触图形不同，模块也仍可以叠置连接。
本发明的其他优点将结合各种实施例更详细的在下文描述。
在上下文中术语“孔”不仅可以指贯穿结构的孔，也可以指凹槽(recess)，其例如通过钻孔或者激光的作用形成，并且不必贯穿所述结构(基底或者其他的层)。
元件的接触端可以是例如凸起的凸块，也可以是其他种类，例如元件表面的平面接触区域。从另一方面来说，术语“元件的接触表面”指包括至少一个接触端的元件表面，或者指可以用例如本申请披露的方法，在它的该表面方向上，至少一个接触端子可以被接近以产生电接触。
术语上表面指模块、模块坯或者元件的一个表面，并且术语下表面指与上表面相对的表面。通常，术语“上”和“下”指根据附图示出的方向或者从中可以明显看出的方向。以下，本发明将参照实施例以及相应的附图说明。
附图说明
附图1-10示出一系列与一个制造方法有关的本发明申请的一些实例的横截面图。
具体实施方式
阶段A(附图1)
在阶段A，选择适当的导体层14作为该过程的起始材料。其中导体层4位于支撑基底12表面上的分层薄片，也可以被选择作为起始材料。该分层薄片可以使用例如如下步骤制造：选取一适于处理的支撑基底12，并将合适的导体膜贴附于该支撑基底12的表面，以产生导体层4。
该支撑基底12可以是由诸如铝(Al)的导电材料、或者诸如聚合物的绝缘材料形成的。该导体层4可以通过例如将薄金属箔附着到该支撑基底12的一个表面，例如通过层压铜(Cu)，来制造。该金属箔可以例如通过使用粘性层贴附于该支撑基底，该粘性层在金属层层压前，涂敷在该支撑基底12或者金属箔的表面上。在这个阶段中，需金属箔上无图案。
在图1的实例中，在基底中制造穿透支撑基底12和导体层4的孔3，用于元件6在安装和连接过程中的对准。例如，可以为待安装的每个元件6制造两个通孔3。孔3可以使用一些适合的方法制造，例如，机械地研磨、冲压、钻孔，或者借以激光。然而，并不是必须制造通孔3，作为替代，可采用其他适合的对准标记来对准元件。图1示出的实施例中，用于对准元件的通孔3贯穿支撑基底12和导体膜4。这样做的优点在于，在安装基底的两侧上进行对准时可使用同样的对准标记(通孔3)。
在该优选实施例的阶段A中，用于元件6的接触孔2也被制造在导体层4中，其位于元件6的接触端7的位置。孔2能够贯穿导体层4，或者可以是凹槽，该凹槽位于在后面的阶段元件将粘合到的导体层的那侧上。如果接触孔在这个阶段已经制造在导体层4中，则将不存在钻孔将破坏元件的危险。例如，当使用激光钻孔时，在典型的钻孔深度下，伴随着钻孔有大约5μm的公差。当用这种方式进行时，或者可能完全避免制造接触孔，或者至少使得与基底的这一侧产生接触变的容易。
阶段A也可以与下述实施例中相同的方式执行，其中使用自支撑导体层4并且因此完全不需支撑层12。
阶段B(附图2)
在阶段B，在将附着元件6的区域中，在导体层4上涂敷粘性层5。这些区域可被称为连接区域。粘性层5可以例如借助于通孔3对准。该粘性层的厚度以这样的方式来选择，即当元件6层压到粘性层5上时，粘合剂完全填满元件6和导体层4之间的空间。如果元件6包括接触突出7，则该粘性层5的厚度应当更大，例如为接触突出高度的1.5-10倍，这样元件6和导体层4之间的空间可以被良好地充满。为元件6形成的粘性层5的表面区域也可以稍大于该元件6相应的表面区域，这同样有助于减少不充分填充的风险。
这些实施例中的粘合剂通常为热固化环氧树脂，例如NCA(不导电粘合剂)。粘合剂的选择必须确保所用的粘合剂充分地粘附于导体膜、电路板以及元件。该粘合剂的一个优选特性是适当的热膨胀系数，以便在该过程中，粘合剂的热膨胀将不会与周围材料的热膨胀差别太大。优选地，所选粘合剂还需要具有最多几秒的短固化时间。在这段时间内，粘合剂应当至少部分硬化到允许粘合剂将该元件保持在适当位置的程度。最后的硬化显然可以时间长一些并且实际上最后的固化化可以安排成与接下来的处理阶段结合发生。该粘合剂还需要能耐受所使用的处理温度，比如，加热到100-265℃到温度几次，以及制作过程中的其它压力，比如，化学和机械压力。优选地该粘合剂的电导率应当与该绝缘材料的量级相同。
步骤B可以以这样的方式改进，粘合剂层5涂敷在该元件6的连接器表面上，而非导体层4的连接器区域上。例如，可以以这种方式进行，即，在元件组装到电子模块内的恰当位置之前，将元件浸入到粘合剂中。也可以通过将粘合剂涂敷在导体层4的连接器区域上和元件6的连接器表面上来进行。
因所使用的粘合剂是电绝缘体，所以在粘合剂层5本身中不会引起元件6的接触端子之间的电接触。
步骤C(图3)
在步骤C中，元件6设置在电子模块中的恰当位置。这例如可以通过借助于组装机械将元件6压入粘合剂层5来完成。在组装步骤中，使用用于对准的通孔3或者其它可利用的对准标记来对准元件6。
元件6可以单个地胶粘，或者以适当的组进行胶粘。通常的过程是：使可以称为安装基底的底部的导体层位于相对于组装机械的适当位置，之后，元件6被对准并压到安装基底的底部上，该安装基底在对准和和粘附过程中保持静止。
元件6优选以这样的方式组装在安装基底上，即其接触端子7的接触表面靠近导电层4的元件6那侧的表面(或者靠近可能已经形成在其中的孔2)。根据尤其优选的实施例，接触端子7基本上与导体层4直接接触地进行组装。在图3示出的实施例中，在接触端子7和导体层4之间留下粘合剂薄层。
步骤D(图4)
在图4中，绝缘材料层1置于导体层4顶上，在该绝缘材料层1中具有用于将元件6胶粘到导体层4的预先形成的孔2或者凹槽。该绝缘材料层1可以由适当的聚合物基底制造，其中利用适当的方法制造根据元件6的尺寸和位置选择的孔或凹槽。该聚合物基底可以是例如电路板工业中已知并广泛使用的半固化片(pre-preg)基底，该半固化片基底由玻璃纤维垫和所谓的b态环氧树脂(b-state epoxy)制成。最好只是在粘合剂层5已经固化或者充分硬化而使元件6保持在恰当位置且绝缘材料层1设置于恰当位置之后，进行步骤D。
步骤E(图5)
根据一个实施例，在步骤E中，未图形化的绝缘材料层11被设置在绝缘材料层1的顶部，然后导体层9被设置在它的顶部。与绝缘材料层1类似，绝缘材料层11可以由例如上述半固化片基底的适当聚合物膜制造。该导体层9可以是例如铜箔或者适合于该目的的某些其它膜。绝缘材料层11优选是薄的，这样接触端子7’和导体层9之间的距离将不会变大，这种情形下有助于在后面的步骤中贯穿该绝缘材料层的孔17的形成和导体材料的布置。
发现下述情形是尤其有利的：接触端子7和导体层4之间以及接触端子7’和导体层9之间剩余的层的厚度小于在其中形成的孔的直径，通常是小于50μm，典型的是小于30μm，甚至小于20μm。如果孔的深度明显大于其直径，则更难形成高品质的孔和通路。
根据一个优选实施例，元件6’的接触端子7’在步骤E基本上与导体层9接触，这样更有助于在接触端子和导体层之间形成良好的电接触。
在一些实施例中，绝缘层11完全可以被省略。
步骤F(图6)
在步骤F中，借助于热和压力来按压层1和9以及可能残留在这两者之间的层11，使得(层1和11中的)该聚合物在导体层4和9之间在元件6周围形成一体的、紧密的和耐用的层，较好地保护元件。这个步骤使得第二导体层9十分均匀和平坦。然而，该方法也可以应用到不平坦的电子模块的制造中。
步骤G(图7)
在步骤G中，从该结构分离或者移除该支撑基底12。例如可以机械地或者通过蚀刻来进行该移除。当然，在不使用支撑基底12的实施例中可以省略步骤G。因此在以下步骤开始时，基底在两侧基本上是相同的。
步骤H(图8)
在步骤H中，形成孔17用于接触通路。在基底的两侧都形成穿过导体层4和9的孔17，并且如果需要，孔17穿过粘合剂层5，使得元件6的接触端子7和7’的材料暴露。如果在步骤A中已经在导体层4中形成接触孔2并且接触端子7的导体材料裸露，则实质上将不在基底的该侧上形成孔17。例如，可以通过借助激光的钻孔来形成孔17。例如可以借助于孔3或2来对准孔17。
如果在之前的步骤中已经在导体层4中形成接触孔2，则在这个步骤中，只需打开孔，使得接触端子7的接触表面暴露。之后，孔2示成与孔17合并。
为了使导体层4和9互相电接触，在步骤H中，也可以形成孔23，用于延伸穿过整个绝缘材料层1的通路。可以在基底内期望的位置形成一个或多个这些孔，这通常取决于将在后面的步骤中进行的导体图形化。孔23优选和孔17一样地形成，借由激光或者通过机械钻孔来形成。
在一些实施例中，通过元件6形成期望的电连接，且无需形成通路23。在这种情况下，期望的电连接也可以表示无电接触并且电子模块的“两侧”独立地工作。例如，如果嵌入的微电路6包括彼此不连接的两个半导体芯片，就是这样的情况。
在下面的步骤中，除对准孔3和孔17以外，孔23也可以用作对准标记。这是有利的，因为孔23贯穿整个基底结构，使得它们确定了基底上、下表面的相对位置且在基底的下表面上也可以和在上表面一样很好地使用。
步骤I(图9)
在步骤I中，在步骤H中形成的孔17以及可能的孔23中生长导体材料18，以形成通路。在示例工艺中，导体材料同时也在基底顶上的别处生长，从而也增加绝缘层4和9的厚度。
将被生长的导体材料18可以是例如铜或者充分导电的某些其它材料。导体材料18的选择考虑了该材料与元件6的接触凸起7和7’的材料形成电接触的能力。在一个实例工艺中，导体材料18主要是铜。铜金属化可以通过在孔17和23中沉积化学铜薄层且之后利用电化学铜生长法继续电镀来进行。例如使用化学铜，因为它也将在粘合剂的顶上形成沉积物并且在电化学镀中用作电导体。因此该金属可以使用湿化学法生长，从而降低生长成本。
在该实例工艺中，首先利用三步去污(desmear)工艺清洁通路17。而后，该孔通过这样的方法进行金属化，首先形成聚合物催化SnPd涂层，之后在该表面上沉积化学铜薄层(大约0.5μm)。通过电化学沉积来增加铜的厚度。
步骤I旨在形成元件6与导体层4和/或9之间的电接触，并且可能直接是导体层4和9之间的电接触。这样，在步骤I没有必要增加导体层4和9的厚度，而是可以同样好地设计该工艺，使得在步骤I仅填充孔17和23。例如，可以通过用导电浆填充孔17，或者利用其它一些适合的微通路金属化的方法，来形成导体层18。
在之后的图中，导体层18示成与导体层4和9合并。
步骤J(图10)
在步骤J中，所需导体图案14和19由基底表面上的导体层4和9形成。导体图案14和19可以通过从导体图案外去除导体层4和9的导体材料来形成。例如，可以使用在电路板工业上广泛使用并且公知的一些图形化和蚀刻方法，比如通过蚀刻，来去除导体材料。
在步骤J之后，该电子模块包含元件6，或者几个元件6，以及导体图案14和19，还有可能包含电通路23。借助于导体图案14和19以及通路23，元件6可以与外部电路连接，或者互相连接。然后存在制造操作整体的前提条件。因此该工艺可以以这样的方式设计，即在步骤J后电子模块已制作完毕，而图12实际上示出了由2个元件层构成的一个可能的电子模块的实例。
如果需要，也可以在步骤J后继续该工艺，例如，用防护剂涂敷该电子模块，或者在该电子模块的第一和/或第二表面上形成另外的导体图案层。例如还可以如相同申请人的早期公开文本WO 03/065778和WO 03/065779中所述，叠加几个这样的电子模块从而形成具有几层的模块。例如利用上述电子模块制造方法之一，可以制造多层电子模块(具有元件6以及导体14和19的基底1)的子模块。当然，同样可以利用适用于此目的的一些其它方法来制造贴附于该分层结构的一些或全部子模块。
根据一个优选实施例，可以在模块的两个表面上形成基本上相同的导体图案，这样2个或者多个模块可以彼此叠置，从而它们的导体图案也相邻地放置。接触图案可以由直接设置在绝缘材料顶上的导体结构14和19构成。本实施例的优点是可以应用本领域的一些已知方法形成接触图案之间的电接触。于是以所述方式，有可能制造电子模块，通过在与基底的表面成直角的方向成层来增加其尺寸，改进了电子模块的可操作性。彼此叠置的该电子模块甚至可能具有完全不同的操作性。它们在外形上不需要完全相似，而是，一个或者多个元件更小的单元可以连接到更大基底顶上，所述元件更小的单元在该大基底的一些特定点与该基底的接触图案一致。
图1-10的实例中示出了一些可能的工艺，借由这些工艺可以利用本发明。然而，本发明不仅限于上述的工艺，而是，考虑到权利要求的全部范围和等效解释，本发明还覆盖了其它的多种工艺和它们的最终产品。本发明也不仅限于实例中示出的结构和方法，相反对于本领域技术人员来说显然本发明的多种应用可以被应用于制造很多不同种类的、甚至与上述实例大相径庭的电子模块和电路板。图中示出的模块和电路只用于说明的目的。因此，可以对上述的实例工艺进行多种变化，但是不脱离根据本发明的基本思路。例如这些变化可以涉及在不同步骤中描述的制造技术或者工艺步骤的相互次序。
因而，本发明也可以结合很多不同种类的已知制造方法来使用。例如，公开文本WO 03/065778和WO 03/065779公开了在基底中嵌入元件的方法，其中在附着元件之前，绝缘材料层被放置在准备好的图形化导体层的顶上。类似地，例如公开文本WO 04/089048中公开的方法的技术特征可以应用于本发明。
另外，本发明还可以结合相同申请人的国际专利申请中公开的方法和电子模块来使用，该国际专利申请在进行本申请时还未公开。可以给出的这种方法的例子是在我们的申请FI 20031341中公开的方法，其中由至少一侧的表面上具有导体层的绝缘片开始制造。在该绝缘片中形成凹槽，该凹槽开子该片的一个表面上，但是不穿透该片相对侧上的导体层。将元件帖附到凹槽，并且在导体层和元件的接触区域或者接触凸块之间形成电接触。
例如，我们的申请FI 20040592中公开的用于从嵌入的元件将热导出的方法及其各种实施例，可以容易并有效地应用于根据本发明的电子模块结构及其制造方法。在解决方案中，在基底的一侧或另一侧上，在元件附近形成通过其从元件导出热量的热通路。在本发明的框架内，例如，热通路可以形成在接触端子7和/或7’之间的区域内，使得它们延伸到元件主体附近，或者甚至在其上。在所参考的申请中，还描述了一种技术，其中这种热通路用于形成例如在元件和导体结构4或9之间的地接触。这样，至少一个热通路被设置在绝缘材料层内(该绝缘材料层可以在基底的任意一侧上)，其可直接在例如具有半导体材料的元件主体材料与绝缘材料层的第一或第二表面的导体结构之间形成电接触，例如，用于形成地接触。于是元件的表面用作一个接触端子。然而，通常这种接触以及地接触，通过元件中的实际接触端子形成。

Claims (21)

1.一种电子模块，具有绝缘材料层(1)，所述绝缘材料层具有两个相对表面，并且所述电子模块包括至少一个嵌入元件(6)，所述嵌入元件具有第一接触端子(7)，所述元件(6)从所述第一接触端子(7)电连接到所述电子模块中包含的导体结构，其特征在于：所述元件(6)具有与第一接触表面相对的第二接触表面，其中具有至少一个第二接触端子(7’)，所述元件(6)从所述第二接触端子(7′)电连接到所述电子模块中包含的导体结构。
2.如权利要求1所述的电子模块，其特征在于所述绝缘材料层(1)为由基本上相同的材料构成的一体层。
3.如权利要求1或2所述的电子模块，其特征在于通过硬化包含至少一种未硬化或者预硬化的聚合物的材料层，形成所述绝缘材料层。
4.如上述权利要求中任一项所述的电子模块，其特征在于所述元件(6)的第一接触端子(7)与位于所述绝缘材料层(1)的第一表面上的导体结构(14)电连接，并且至少一个第二接触端子(7’)与位于所述绝缘材料层(1)的第二表面上的导体结构(19)电连接。
5.如权利要求4所述的电子模块，其特征在于借助于设置在所述绝缘材料层(1)中形成的接角孔(17)内的导体材料，使至少一个第二接触端子(7’)与位于所述绝缘材料层(1)的第二表面上的导体结构(19)电连接。
6.如权利要求5所述的电子模块，其特征在于设置于所述绝缘材料层(1)的第二表面的至少一个通路，在例如是半导体材料的所述元件(6)的主体材料与所述绝缘材料层的第二表面的导体结构(19)之间形成电接触，例如以形成接地接触。
7.如权利要求4-6中任一项所述的电子模块，其特征在于所述导体结构(14、19)通过通路(23)互相电连接，以形成操作整体。
8.如权利要求4-7中任一项所述的电子模块，其特征在于其所包含的第一表面的导体结构(14)包含设置在所述绝缘材料层(1)的第一表面顶上的一个或者多个图形化导体层(4)，并且其所包含的第二表面的导体结构(19)包含设置在所述绝缘材料层(1)的第二表面顶上的一个或者多个图形化导体层(9)。
9.如上述权利要求中任一项所述的电子模块，其特征在于所述第一接触端子(7)的接触表面到位于所述绝缘材料层(1)的第一表面上的导体结构(14)的距离、和/或所述第二接触端子(7’)到位于所述绝缘材料层(1)的第二表面上的图形化导体结构(19)的距离，小于所述接触孔(17)的直径，通常至多为50μm，典型的是至多30μm，并且特别有益的是大约0μm。
10.如上述权利要求中任一项所述的电子模块，其特征在于具有至少2个，优选至少4个所述第二接触端子(7’)。
11.如上述权利要求中任一项所述的电子模块，其特征在于至少一个第二接触端子(7’)用于向元件(6)传导地平面电位、信号电压或者电源电压。
12.一种用于制造电子模块的方法，在所述方法中，至少一个元件(6)被嵌入绝缘材料层(1)，所述元件(6)具有第一接触表面，在所述第一接触表面中具有第一接触端子(7)，所述绝缘材料层(1)包括两个相对表面，并且形成从接触端子(7)将元件(6)电连接到所述电子模块中包含的导体结构的接触，其特征在于，
元件(6)具有与所述第一接触表面相对的接触表面(6)，该接触表面(6)中具有至少一个第二接触端子(7’)，并且形成从接触端子(7’)将元件(6)电连接到所述电子模块中包含的导体结构的接触。
13.如权利要求12所述的方法，其特征在于第一导体层(4)设置在所述绝缘材料层(1)的第一表面上，并且第二导体层(9)设置在第二表面上。
14.如权利要求13所述的方法，其特征在于借助于设置于所述绝缘材料层的第二表面的接触孔(17)中设置的导体材料，将元件(6)的至少一个第二接触端子(7’)与第二导体层(9)电连接。
15.如权利要求13或14所述的方法，其特征在于在将第一导体层(4)设置在所述绝缘材料层(1)的第一表面上之前，在第一导体层(4)内形成接触孔(2)和/或对准孔(3)。
16.如权利要求13-15中任一项所述的方法，其特征在于元件(6)的第一接触表面被粘结到第一导体层(4)。
17.如权利要求15所述的方法，其特征在于在粘结元件(6)之后，将所述绝缘材料层(1、11)的至少一部分放置在该电子模块上。
18.如权利要求12-17中任一项所述的方法，其特征在于绝缘材料层(1、11)由至少两个独立的材料片形成，它们被压在一起从而形成单个一体的绝缘材料层(1)。
19.如权利要求13-18中任一项所述的方法，其特征在于形成通路(23)从而使导体层(4、9)互相电连接。
20.如权利要求12-19中任一项所述的方法，其特征在于具有至少2个，优选至少4个第二接触端子(7’)。
21.如权利要求12-19中任一项所述的方法，其特征在于至少一个第二接触端子(7’)用于向元件(6)传导接地电位、信号电压或者电源电压。
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US8351214B2 (en) 2013-01-08
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GB2429848B (en) 2008-01-30
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