CN101026192A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101026192A
CN101026192A CNA2007100849579A CN200710084957A CN101026192A CN 101026192 A CN101026192 A CN 101026192A CN A2007100849579 A CNA2007100849579 A CN A2007100849579A CN 200710084957 A CN200710084957 A CN 200710084957A CN 101026192 A CN101026192 A CN 101026192A
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田中秀治
菊地修一
中谷清史
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种高耐压MOS晶体管，其具有高的栅极耐压和高的源极－漏极耐压，并且具有低的接通电阻。其在外延硅层(2)上，经由LOCOS膜(4)形成栅极电极(5)。在LOCOS膜(4)的左侧形成P型第一漂移层(6)，在LOCOS膜(4)的右侧的外延硅层(2)表面上，与第一漂移层(6)相向，且在其间夹着栅极电极(5)而配置P+型源极层(7)。形成有比第一漂移层(6)更深地向外延硅层(2)中扩散、并从第一漂移层(6)下方向LOCOS膜(4)的左侧下方延伸的P型第二漂移层(9)。在LOCOS膜(4)的左端下方的第二漂移层(9)的下部形成有凹部R。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，特别是涉及一种高耐压MOS晶体管的构造及其制造方法。
背景技术
高耐压MOS晶体管具有高的源极-漏极耐压或高的栅极耐压，广泛应用于LCD驱动器等各种驱动器或电源电路等。近年来，希望高耐压晶体管同时具备高的源极-漏极耐压和高的栅极耐压。因此，原来将场绝缘膜即LOCOS膜(Local Oxidation of Silicon)作为栅极绝缘膜使用，使栅极耐压提高，并且，通过设置低浓度的漏极层，实现源极-漏极耐压的提高。
关于高耐压MOS晶体管，特许文献1中已有所记载。
特许文献1：日本特开2004-39774号公报
但是，就上述的高耐压MOS晶体管而言，虽然能得到200V左右的栅极耐压，但其存在的问题是，在漏极侧的LOCOS膜的端部发生电场集中，在此处由于产生PN结击穿，所以得不到目标源极-漏极耐压。
发明内容
因此，本发明提供一种半导体装置，其特征在于，具备：经由场绝缘膜形成在第一导电型半导体层上的栅极电极、
第二导电型的第一漂移层、
与所述第一漂移层相向，并将所述栅极电极夹在其间配置的源极层、
比所述第一漂移层更深地向所述半导体层中扩散，并从所述第一漂移层的下方向场绝缘膜的下方延伸的第二导电型第二漂移层，
在所述场绝缘膜端部的下方的所述第二漂移层的下部形成有凹部。
根据本发明，能够提供高耐压MOS晶体管，其具有约200V左右的栅极耐压、约280V左右的高的栅极-漏极耐压，并且具有低的接通电阻。
附图说明
图1是说明本发明实施例的半导体装置的制造方法的剖面图；
图2是说明本发明实施例的半导体装置的制造方法的剖面图；
图3是说明本发明实施例的半导体装置的制造方法的剖面图；
图4是说明本发明实施例的半导体装置的制造方法的剖面图；
图5是说明本发明实施例的半导体装置的制造方法的剖面图；
图6是说明本发明实施例的半导体装置的制造方法的剖面图；
图7是说明本发明实施例的半导体装置的制造方法的剖面图；
图8是说明本发明实施例的半导体装置的制造方法的剖面图；
图9是说明本发明实施例的半导体装置的制造方法的剖面图；
图10是说明本发明实施例的半导体装置的剖面图；
图11是说明本发明实施例的半导体装置的剖面图。
符号说明
1、单晶硅衬底，2、外延硅层，3、埋入硅层，4、LOCOS膜，
5、栅极电极，6、第一漂移层，7、源极层，8、N+层，
9、第二漂移层，10、低浓度源极层。11、沟道杂质层，
12、漏极层，13、第一层间绝缘膜，14、漏极电极，
15、源极电极，16、第二层间绝缘膜，17、场电极，
20、虚设氧化膜，21、23、24、25、26、27、光致抗蚀剂层，
21A、光致抗蚀剂片，22、栅极氧化膜
CH1、CH2、接触孔，
OF、偏移长度，R、凹部，SL、缝隙
具体实施方式
参照图10说明本发明实施例的高耐压MOS晶体管的构造。在P型单晶硅衬底1上外延生长N型外延硅层2，在单晶硅衬底1和外延硅层2的界面上形成有N+型埋入硅层3。在外延硅层2上形成具有约1000nm膜厚的LOCOS膜4，在该LOCOS膜4上形成有栅极电极5。在LOCOS膜4左侧的外延硅层2的表面上形成有P型第一漂移层(P+L)6，在LOCOS膜右侧的外延硅层2的表面上，中间夹着栅极电极5与第一漂移层6相向而配置有P+型源极层(PSD)7。在源极层7的右侧形成有用于将外延硅层2设定为源极电位的N+层(NSD)8。
另外，形成有P型第二漂移层(SP+L)9，其比第一漂移层6更深地向外延硅层2中扩散，并从第一漂移层6的下方向LOCOS膜4的左侧下方延伸。在LOCOS膜4的左端下方的第二漂移层9的下部形成有凹部R。
另外，形成有低浓度的源极层10，其与该第二漂移层9同时形成，并从源极层7的下方向LOCOS膜4的右侧下方延伸。在LOCOS膜4下方的第二漂移层9和低浓度源极层10之间，与LOCOS膜4的下部相接，而形成有比外延硅层2更高浓度的N型沟道杂质层(FN)11。
在第一及第二漂移层6、9的左侧，与它们相接触而形成有P型漏极层12。漏极层12由三个P型层(PSD层、SP+D层、P+D层)构成，其中表面的P+D层浓度最高，其下面的SP+D层的浓度次之，再下面的P+D层浓度最低。这样，通过对漏极层12设置浓度梯度，加大漏极层12的耗尽层扩展，实现高耐压性。
另外，还形成有覆盖栅极电极5、具有约1000nm膜厚的第一层间绝缘膜13，在漏极层12的PSD层上的第一层间绝缘膜13上开设接触孔CH1。形成由通过该接触孔CH1与漏极层12的PSD层接触的、铝等第一层金属层构成的漏极电极14。另外，在源极层7和N+层8上的第一层间绝缘膜13上开设接触孔CH2。形成由通过该接触孔CH2与源极层7和N+层8接触的、铝等第一层金属层构成的源极电极15。
另外，还形成有场电极17，该场电极17从栅极电极5的一部分上，经由第一层间绝缘膜13及具有约1000nm膜厚的第二层间绝缘膜16延伸到第一漂移层6上。场电极17用由铝等金属构成的第二层金属层形成，设定为源极电位。场电极17的作用是，扩大第一及第二漂移层6、9和外延硅层2之间的耗尽层。之所以用第二层金属层形成场电极17，是由于如果用第一层金属层形成，就会在LOCOS膜4的端部产生电场集中，使源极-漏极耐压降低。
上述的高耐压MOS晶体管，因为使用厚的LOCOS膜4作为栅极绝缘膜，所以具有约200V的高的栅极耐压。另外，由于用第一及第二漂移层6、9这两层形成低浓度漏极层，所以能够降低晶体管的接通电阻。
另外，由于在第二漂移层9的下部形成有凹部R，所以在LOCOS膜4的端部下的P型杂质浓度局部地降低，同时，由于第二漂移层9的凹部R和外延硅层2的PN结面积也增大，因此，在施加了漏极电压时，耗尽层扩展变大。在此基础上，还具有场电极17带来的耗尽层扩大的效果。该耗尽层虽然也向外延硅层2中扩展，但由于在单晶硅衬底1和外延硅层2的界面形成有N+型的埋入硅层3，所以防止了耗尽层到达单晶硅衬底1。通过这些相互效果，能够得到约280V这样的高的源极-漏极耐压。通过在第二漂移层9上形成凹部R，虽然使接通电阻少许提高，但其在可以允许的范围，且能够通过提高第二漂移层9的浓度进行补偿。
另外，如图11所示，通过从LOCOS膜4的左端离开偏移长度OF而形成第一漂移层6，能够防止在电场强度高的LOCOS膜4的端部产生PN结击穿，还能够进一步提高源极-漏极耐压。
下面，参照附图说明图10所示的高耐压MOS晶体管的制造方法。如图1所示，在P型单晶硅衬底1的表面高浓度地离子注入N型杂质，在其表面使N型的外延硅层2外延生长。于是，在单晶硅衬底1和外延硅层2的界面上就形成N+型埋入硅层3。在外延硅层2的表面形成热氧化引起的虚设(ダミ一)氧化膜20。
接下来，通过离子注入，在与图10对应的各区域形成第二漂移层9、低浓度源极层10和N型沟道杂质层11。图2中表示通过以光致抗蚀剂层21为掩模进行硼(B+)的离子注入而形成第二漂移层9、低浓度源极层10的工序。在通过离子注入而形成第二漂移层9时，通过事先形成光致抗蚀剂片21A，在该光致抗蚀剂片21A的下方形成与该光致抗蚀剂宽度相对应的缝隙SL。通过在dose量5×1015/cm2的条件下进行磷(P+)离子注入，形成沟道杂质层11。
其后，如图3所示，在去除了光致抗蚀剂层21和虚设氧化膜20之后，通过选择性氧化，形成具有约1000nm膜厚的LOCOS膜4。LOCOS膜4的左端进入第二漂移层9的缝隙SL中。然后，形成具有90nm膜厚的栅极氧化膜22。而且，在该LOCOS膜4上形成具有约400nm膜厚的栅极电极5。栅极电极5由多晶硅、高熔点金属硅化物等形成。
接着，如图4所示，形成具有与图10的漏极层12的形成区域相对应的开口的光致抗蚀剂层23。以该光致抗蚀剂层23为掩模，通过硼(B+)离子注入而形成漏极层12的P+D层。硼(B+)的dose量为约1×1013/cm2。
接着，如图5所示，在去除了光致抗蚀剂层23之后，在1180℃温度、N2气氛中进行四小时的热扩散。由此，第二漂移层9、沟道杂质层11和P+D层向深处扩散。通过该热扩散，引起硼的横向扩散，从而缝隙SL的宽度变窄，最终缝隙SL的上部被硼填埋，在第二漂移层9的下部形成凹部R。
接着，如图6所示，形成光致抗蚀剂层24，以该光致抗蚀剂层24为掩模，通过硼(B+)离子注入，在P+D层中形成SP+D层。然后，去除光致抗蚀剂层24，在1050℃温度下进行五小时的热扩散，或在1100℃温度下进行90分钟的热扩散。然后，如图7所示，形成在漏极侧具有开口部的光致抗蚀剂层25，以该光致抗蚀剂层25为掩模，通过硼(B+)离子注入，在第二漂移层9的表面形成第一漂移层6。
接着，如图8所示，在去除光致抗蚀剂层25之后，形成具有与N+层8的形成区域相对应的开口的光致抗蚀剂层26，以该光致抗蚀剂层26为掩模，通过磷(P+)离子注入，形成N+层8。然后，如图9所示，形成具有与漏极层12的PSD层的形成区域、源极层7的形成区域相对应的开口的光致抗蚀剂层27。以该光致抗蚀剂层27为掩模，通过硼(B+)离子注入，形成漏极层12的PSD层、源极层7。硼(B+)的dose量为约1×1015/cm2。
接着，如图10所示，通过CVD形成覆盖栅极电极5、且具有约1000nm膜厚的第一层间绝缘膜13，在漏极层12的PSD层上的第一层间绝缘膜13、栅极氧化膜22上，通过蚀刻而开设接触孔CH1。形成由通过该接触孔CH1与漏极层12的PSD层接触的、铝等第一层金属层构成的漏极电极14。另外，在源极层7及N+层8上的第一层间绝缘膜13、栅极氧化膜20上，通过蚀刻而形成接触孔CH2。形成由通过该接触孔CH2与漏极层7及N+层8接触的、铝等第一层金属层构成的源极电极15。然后，在整个面上形成具有约1000nm膜厚的第二层间绝缘膜16。进而形成场电极17，该场电极17从栅极电极5的一部分上，经由第一层间绝缘膜13、第二层间绝缘膜16延伸到第一漂移层6的一部分上。

Claims (9)

1、一种半导体装置，其特征在于，具备：
经由场绝缘膜形成在第一导电型半导体层上的栅极电极、
第二导电型的第一漂移层、
与所述第一漂移层相向，并将所述栅极电极夹在其间配置的源极层、
比所述第一漂移层更深地向所述半导体层中扩散，并从所述第一漂移层的下方向场绝缘膜的下方延伸的第二导电型第二漂移层，
在所述场绝缘膜端部的下方的所述第二漂移层的下部形成有凹部。
2、如权利要求1所述的导体装置，其特征在于，具备从所述栅极电极的一部分上向所述第一漂移层一部分上延伸的场电极。
3、如权利要求2所述的半导体装置，其特征在于，所述场电极由第二层金属层构成。
4、如权利要求1所述的半导体装置，其特征在于，第一漂移层离开所述场绝缘膜的端部而配置。
5、如权利要求1、2、3、4中任意一项所述的半导体装置，其特征在于，与所述场绝缘膜的下部相接，形成有比所述半导体层更高浓度的第一导电型沟道杂质层。
6、如权利要求1、2、3、4中任意一项所述的半导体装置，其特征在于，具备与所述第一漂移层及所述第二漂移层相接触的漏极层。
7、如权利要求1、2、3、4中任意一项所述的半导体装置，其特征在于，所述半导体层是在第二导电型单晶半导体衬底上外延生长的外延半导体层，其在所述单晶半导体衬底和所述半导体层的界面上形成有比所述半导体层更高浓度的第一导电型埋入半导体层。
8、一种半导体装置的制造方法，其特征在于，包含：
在第一导电型半导体层上形成具有缝隙的第二导电型的第二漂移层的工序；通过选择氧化法，以使其端部进入上述缝隙的方式在所述半导体层的表面形成场绝缘膜的工序；在所述场绝缘膜上形成栅极绝缘膜的工序；通过将所述第二漂移层热扩散，在所述第二漂移层的下方形成与所述缝隙对应的凹部的工序；在所述第二漂移层的表面形成第一漂移层的工序；形成在其间夹着所述栅极电极而与所述第一漂移层相向的第二导电型源极层的工序。
9、如权利要求8所述的半导体装置的制造方法，其特征在于，具备与所述场绝缘膜的下部相接而形成比所述半导体层具有更高浓度的第一导电型沟道层的工序。
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