CN101000915B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN101000915B CN101000915B CN2007100038920A CN200710003892A CN101000915B CN 101000915 B CN101000915 B CN 101000915B CN 2007100038920 A CN2007100038920 A CN 2007100038920A CN 200710003892 A CN200710003892 A CN 200710003892A CN 101000915 B CN101000915 B CN 101000915B
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- Prior art keywords
- layer
- semiconductor
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- peristome
- conductive layer
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- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 178
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 238000000034 method Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 239000010410 layer Substances 0.000 claims description 245
- 239000011229 interlayer Substances 0.000 claims description 65
- 230000015572 biosynthetic process Effects 0.000 claims description 58
- 229910021332 silicide Inorganic materials 0.000 claims description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 42
- 238000009413 insulation Methods 0.000 claims description 34
- 230000003647 oxidation Effects 0.000 claims description 30
- 238000007254 oxidation reaction Methods 0.000 claims description 30
- 239000003989 dielectric material Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 27
- 238000005516 engineering process Methods 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000003466 welding Methods 0.000 description 7
- 238000009434 installation Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000012447 hatching Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-002222 | 2006-01-10 | ||
JP2006002222A JP2007184449A (ja) | 2006-01-10 | 2006-01-10 | 半導体装置及びその製造方法 |
JP2006002222 | 2006-01-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101000915A CN101000915A (zh) | 2007-07-18 |
CN101000915B true CN101000915B (zh) | 2010-09-08 |
Family
ID=38231958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007100038920A Expired - Fee Related CN101000915B (zh) | 2006-01-10 | 2007-01-10 | 半导体装置及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7535062B2 (zh) |
JP (1) | JP2007184449A (zh) |
KR (1) | KR20070075284A (zh) |
CN (1) | CN101000915B (zh) |
TW (1) | TW200737408A (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8008734B2 (en) * | 2007-01-11 | 2011-08-30 | Fuji Electric Co., Ltd. | Power semiconductor device |
JP2009070966A (ja) | 2007-09-12 | 2009-04-02 | Toshiba Corp | 半導体装置とその製造方法 |
JP5468445B2 (ja) * | 2010-03-31 | 2014-04-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
US8772950B2 (en) * | 2012-11-07 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for flip chip substrate with guard rings outside of a die attach region |
JP6271841B2 (ja) * | 2013-02-13 | 2018-01-31 | ラピスセミコンダクタ株式会社 | 半導体装置、半導体装置の製造方法および半導体装置を搭載したシステム |
JP2014183151A (ja) * | 2013-03-19 | 2014-09-29 | Seiko Epson Corp | モジュール、モジュールの製造方法、電子機器、および移動体 |
JP6231778B2 (ja) * | 2013-06-05 | 2017-11-15 | キヤノン株式会社 | 電気デバイスおよび放射線検査装置 |
JP6180801B2 (ja) * | 2013-06-07 | 2017-08-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6120739B2 (ja) * | 2013-09-17 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6120738B2 (ja) * | 2013-09-17 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US20150206855A1 (en) * | 2014-01-22 | 2015-07-23 | Mediatek Inc. | Semiconductor package |
US9793227B1 (en) * | 2016-04-21 | 2017-10-17 | Peregrine Semiconductor San Diego | Switchable die seal connection |
JP6936027B2 (ja) * | 2017-03-09 | 2021-09-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN117393522A (zh) * | 2023-12-12 | 2024-01-12 | 英诺赛科(苏州)半导体有限公司 | 半导体晶圆、半导体芯片及其加工方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04142036A (ja) * | 1990-10-02 | 1992-05-15 | Toshiba Corp | 半導体装置の製造方法 |
JP3297956B2 (ja) * | 1993-12-07 | 2002-07-02 | ソニー株式会社 | 半導体装置の製造方法 |
US5478762A (en) * | 1995-03-16 | 1995-12-26 | Taiwan Semiconductor Manufacturing Company | Method for producing patterning alignment marks in oxide |
JP2000323660A (ja) * | 1999-05-11 | 2000-11-24 | Mitsubishi Electric Corp | 半導体装置及びその製造方法並びにウェハの製造方法 |
JP2001028438A (ja) | 1999-07-13 | 2001-01-30 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP2001044441A (ja) | 1999-07-29 | 2001-02-16 | Sony Corp | 完全空乏soi型半導体装置及び集積回路 |
JP3236588B2 (ja) * | 1999-10-01 | 2001-12-10 | ローム株式会社 | 半導体装置 |
JP2004207271A (ja) * | 2002-12-20 | 2004-07-22 | Nec Electronics Corp | Soi基板及び半導体集積回路装置 |
JP2005109145A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | 半導体装置 |
US7053453B2 (en) | 2004-04-27 | 2006-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate contact and method of forming the same |
JP3962729B2 (ja) * | 2004-06-03 | 2007-08-22 | 株式会社東芝 | 半導体装置 |
WO2006033875A2 (en) * | 2004-09-09 | 2006-03-30 | Orobridge, Inc. | Thermoelectric devices with controlled current flow and related methods |
US7408206B2 (en) * | 2005-11-21 | 2008-08-05 | International Business Machines Corporation | Method and structure for charge dissipation in integrated circuits |
-
2006
- 2006-01-10 JP JP2006002222A patent/JP2007184449A/ja active Pending
- 2006-12-27 TW TW095149144A patent/TW200737408A/zh unknown
-
2007
- 2007-01-04 US US11/619,874 patent/US7535062B2/en not_active Expired - Fee Related
- 2007-01-05 KR KR1020070001302A patent/KR20070075284A/ko not_active Application Discontinuation
- 2007-01-10 CN CN2007100038920A patent/CN101000915B/zh not_active Expired - Fee Related
-
2009
- 2009-03-06 US US12/399,062 patent/US7786534B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW200737408A (en) | 2007-10-01 |
KR20070075284A (ko) | 2007-07-18 |
JP2007184449A (ja) | 2007-07-19 |
US20070158691A1 (en) | 2007-07-12 |
US7535062B2 (en) | 2009-05-19 |
US7786534B2 (en) | 2010-08-31 |
US20090194877A1 (en) | 2009-08-06 |
CN101000915A (zh) | 2007-07-18 |
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