CN100555599C - 制备和组装基材的方法 - Google Patents
制备和组装基材的方法 Download PDFInfo
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- CN100555599C CN100555599C CNB2004800298693A CN200480029869A CN100555599C CN 100555599 C CN100555599 C CN 100555599C CN B2004800298693 A CNB2004800298693 A CN B2004800298693A CN 200480029869 A CN200480029869 A CN 200480029869A CN 100555599 C CN100555599 C CN 100555599C
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 title description 10
- 235000012431 wafers Nutrition 0.000 claims abstract description 212
- 239000000463 material Substances 0.000 claims abstract description 61
- 241001074085 Scophthalmus aquosus Species 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000001788 irregular Effects 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 230000008439 repair process Effects 0.000 description 25
- 238000007493 shaping process Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 239000010408 film Substances 0.000 description 10
- 238000000227 grinding Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910017214 AsGa Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
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- 239000001257 hydrogen Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Abstract
Description
Claims (32)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0350674A FR2860842B1 (fr) | 2003-10-14 | 2003-10-14 | Procede de preparation et d'assemblage de substrats |
FR03/50674 | 2003-10-14 | ||
US60/568,700 | 2004-05-07 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009100013195A Division CN101494169B (zh) | 2003-10-14 | 2004-10-14 | 制备和组装基材的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1868054A CN1868054A (zh) | 2006-11-22 |
CN100555599C true CN100555599C (zh) | 2009-10-28 |
Family
ID=34355518
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800298693A Active CN100555599C (zh) | 2003-10-14 | 2004-10-14 | 制备和组装基材的方法 |
CN2009100013195A Active CN101494169B (zh) | 2003-10-14 | 2004-10-14 | 制备和组装基材的方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009100013195A Active CN101494169B (zh) | 2003-10-14 | 2004-10-14 | 制备和组装基材的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20070072393A1 (zh) |
EP (3) | EP2375443B1 (zh) |
JP (1) | JP5032119B2 (zh) |
KR (1) | KR101148052B1 (zh) |
CN (2) | CN100555599C (zh) |
FR (1) | FR2860842B1 (zh) |
WO (1) | WO2005038903A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103084950A (zh) * | 2011-11-08 | 2013-05-08 | 株式会社迪思科 | 晶片加工方法 |
CN109712875A (zh) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | 晶圆直接键合方法 |
Families Citing this family (56)
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FR2871291B1 (fr) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | Procede de transfert de plaques |
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
JP4918229B2 (ja) * | 2005-05-31 | 2012-04-18 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
KR101015158B1 (ko) * | 2005-07-08 | 2011-02-16 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 필름의 제조 방법 |
FR2888400B1 (fr) * | 2005-07-08 | 2007-10-19 | Soitec Silicon On Insulator | Procede de prelevement de couche |
JP4839818B2 (ja) * | 2005-12-16 | 2011-12-21 | 信越半導体株式会社 | 貼り合わせ基板の製造方法 |
FR2899594A1 (fr) | 2006-04-10 | 2007-10-12 | Commissariat Energie Atomique | Procede d'assemblage de substrats avec traitements thermiques a basses temperatures |
EP1975998A3 (en) * | 2007-03-26 | 2013-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a plurality of island-shaped SOI structures |
US7846817B2 (en) * | 2007-03-26 | 2010-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
EP1993128A3 (en) | 2007-05-17 | 2010-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
FR2917232B1 (fr) * | 2007-06-06 | 2009-10-09 | Soitec Silicon On Insulator | Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion. |
EP2174343A1 (en) * | 2007-06-28 | 2010-04-14 | Semiconductor Energy Laboratory Co, Ltd. | Manufacturing method of semiconductor device |
JP5507063B2 (ja) * | 2007-07-09 | 2014-05-28 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
DE102007025649B4 (de) * | 2007-07-21 | 2011-03-03 | X-Fab Semiconductor Foundries Ag | Verfahren zum Übertragen einer Epitaxie-Schicht von einer Spender- auf eine Systemscheibe der Mikrosystemtechnik |
CN101620985B (zh) * | 2008-07-02 | 2011-05-11 | 联华电子股份有限公司 | 晶边蚀刻设备及其相关的晶片平坦化方法 |
DE102008035055B3 (de) | 2008-07-26 | 2009-12-17 | X-Fab Semiconductor Foundries Ag | Verfahren zur Ausrichtung einer elektronischen CMOS-Struktur bezogen auf eine vergrabene Struktur bei gebondeten und rückgedünnten Stapeln von Halbleiterscheiben |
FR2935535B1 (fr) * | 2008-09-02 | 2010-12-10 | S O I Tec Silicon On Insulator Tech | Procede de detourage mixte. |
FR2935536B1 (fr) * | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | Procede de detourage progressif |
EP2200077B1 (en) * | 2008-12-22 | 2012-12-05 | Soitec | Method for bonding two substrates |
KR101550433B1 (ko) * | 2009-01-30 | 2015-09-07 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
EP2246882B1 (en) * | 2009-04-29 | 2015-03-04 | Soitec | Method for transferring a layer from a donor substrate onto a handle substrate |
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EP2461359B1 (en) * | 2009-07-10 | 2017-02-08 | Shanghai Simgui Technology Co., Ltd | Method for forming substrate with insulating buried layer |
FR2950734B1 (fr) * | 2009-09-28 | 2011-12-09 | Soitec Silicon On Insulator | Procede de collage et de transfert d'une couche |
FR2953988B1 (fr) | 2009-12-11 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de detourage d'un substrat chanfreine. |
FR2957190B1 (fr) * | 2010-03-02 | 2012-04-27 | Soitec Silicon On Insulator | Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques. |
FR2957189B1 (fr) * | 2010-03-02 | 2012-04-27 | Soitec Silicon On Insulator | Procede de realisation d'une structure multicouche avec detourage post meulage. |
FR2961630B1 (fr) | 2010-06-22 | 2013-03-29 | Soitec Silicon On Insulator Technologies | Appareil de fabrication de dispositifs semi-conducteurs |
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FR2964193A1 (fr) | 2010-08-24 | 2012-03-02 | Soitec Silicon On Insulator | Procede de mesure d'une energie d'adhesion, et substrats associes |
US20120129318A1 (en) * | 2010-11-24 | 2012-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate |
FR2969373B1 (fr) * | 2010-12-20 | 2013-07-19 | St Microelectronics Crolles 2 | Procede d'assemblage de deux plaques et dispositif correspondant |
JP2013008915A (ja) * | 2011-06-27 | 2013-01-10 | Toshiba Corp | 基板加工方法及び基板加工装置 |
FR2980302A1 (fr) | 2011-09-20 | 2013-03-22 | St Microelectronics Crolles 2 | Procede de protection d'une couche d'un empilement vertical et dispositif correspondant |
US8383460B1 (en) * | 2011-09-23 | 2013-02-26 | GlobalFoundries, Inc. | Method for fabricating through substrate vias in semiconductor substrate |
US9064770B2 (en) * | 2012-07-17 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for minimizing edge peeling in the manufacturing of BSI chips |
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FR2995133A1 (fr) * | 2012-08-31 | 2014-03-07 | St Microelectronics Crolles 2 | Procede d'amincissement d'une tranche semiconductrice |
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DE102015118042A1 (de) * | 2015-10-22 | 2017-04-27 | Nexwafe Gmbh | Verfahren und Vorrichtung zum Herstellen einer Halbleiterschicht |
US10867836B2 (en) * | 2016-05-02 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer stack and fabrication method thereof |
KR20180090494A (ko) * | 2017-02-03 | 2018-08-13 | 삼성전자주식회사 | 기판 구조체 제조 방법 |
US10818488B2 (en) * | 2017-11-13 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer structure and trimming method thereof |
US10504716B2 (en) * | 2018-03-15 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing semiconductor device and manufacturing method of the same |
CN109545672A (zh) * | 2018-11-21 | 2019-03-29 | 德淮半导体有限公司 | 晶圆键合方法以及键合晶圆 |
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-
2003
- 2003-10-14 FR FR0350674A patent/FR2860842B1/fr not_active Expired - Lifetime
-
2004
- 2004-10-14 JP JP2006534763A patent/JP5032119B2/ja active Active
- 2004-10-14 KR KR1020067007070A patent/KR101148052B1/ko active IP Right Grant
- 2004-10-14 CN CNB2004800298693A patent/CN100555599C/zh active Active
- 2004-10-14 EP EP11173320.0A patent/EP2375443B1/en active Active
- 2004-10-14 EP EP04791232.4A patent/EP1676310B1/en active Active
- 2004-10-14 EP EP10177601.1A patent/EP2259301B1/en active Active
- 2004-10-14 CN CN2009100013195A patent/CN101494169B/zh active Active
- 2004-10-14 WO PCT/EP2004/052548 patent/WO2005038903A1/en active Application Filing
- 2004-10-14 US US10/574,798 patent/US20070072393A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103084950A (zh) * | 2011-11-08 | 2013-05-08 | 株式会社迪思科 | 晶片加工方法 |
CN109712875A (zh) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | 晶圆直接键合方法 |
CN109712875B (zh) * | 2018-12-29 | 2020-11-20 | 上海华力微电子有限公司 | 晶圆直接键合方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070072393A1 (en) | 2007-03-29 |
CN101494169B (zh) | 2012-05-09 |
KR101148052B1 (ko) | 2012-05-25 |
EP1676310B1 (en) | 2015-03-25 |
EP2375443B1 (en) | 2020-07-29 |
KR20070015497A (ko) | 2007-02-05 |
JP2007508704A (ja) | 2007-04-05 |
EP2375443A1 (en) | 2011-10-12 |
JP5032119B2 (ja) | 2012-09-26 |
EP2259301A3 (en) | 2010-12-22 |
FR2860842B1 (fr) | 2007-11-02 |
CN1868054A (zh) | 2006-11-22 |
EP1676310A1 (en) | 2006-07-05 |
CN101494169A (zh) | 2009-07-29 |
WO2005038903A1 (en) | 2005-04-28 |
EP2259301B1 (en) | 2020-08-19 |
FR2860842A1 (fr) | 2005-04-15 |
EP2259301A2 (en) | 2010-12-08 |
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