CN100543967C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN100543967C CN100543967C CN200710153513.6A CN200710153513A CN100543967C CN 100543967 C CN100543967 C CN 100543967C CN 200710153513 A CN200710153513 A CN 200710153513A CN 100543967 C CN100543967 C CN 100543967C
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006254385A JP2008078298A (ja) | 2006-09-20 | 2006-09-20 | 半導体装置及びその製造方法 |
JP254385/2006 | 2006-09-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101150090A CN101150090A (zh) | 2008-03-26 |
CN100543967C true CN100543967C (zh) | 2009-09-23 |
Family
ID=39250529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200710153513.6A Active CN100543967C (zh) | 2006-09-20 | 2007-09-20 | 半导体装置及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7800155B2 (zh) |
JP (1) | JP2008078298A (zh) |
KR (1) | KR100936585B1 (zh) |
CN (1) | CN100543967C (zh) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
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US8436410B2 (en) * | 2005-10-31 | 2013-05-07 | Samsung Electronics Co., Ltd. | Semiconductor devices comprising a plurality of gate structures |
JP2009010011A (ja) * | 2007-06-26 | 2009-01-15 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2009026802A (ja) * | 2007-07-17 | 2009-02-05 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
KR101566922B1 (ko) | 2009-02-16 | 2015-11-09 | 삼성전자주식회사 | 저스트 드라이 에칭과 케미컬 드라이 에칭을 조합한 반도체소자의 금속 실리사이드막 형성 방법 |
US8445953B2 (en) | 2009-07-08 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for flash memory cells |
US8546239B2 (en) | 2010-06-11 | 2013-10-01 | Sandisk Technologies Inc. | Methods of fabricating non-volatile memory with air gaps |
US8946048B2 (en) | 2010-06-19 | 2015-02-03 | Sandisk Technologies Inc. | Method of fabricating non-volatile memory with flat cell structures and air gap isolation |
US8603890B2 (en) | 2010-06-19 | 2013-12-10 | Sandisk Technologies Inc. | Air gap isolation in non-volatile memory |
US8492224B2 (en) | 2010-06-20 | 2013-07-23 | Sandisk Technologies Inc. | Metal control gate structures and air gap isolation in non-volatile memory |
KR20120000339A (ko) * | 2010-06-25 | 2012-01-02 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR101762661B1 (ko) * | 2010-09-17 | 2017-08-04 | 삼성전자주식회사 | 반도체 소자 제조 방법 |
KR20120031667A (ko) * | 2010-09-27 | 2012-04-04 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자 제조 방법 |
US8778749B2 (en) | 2011-01-12 | 2014-07-15 | Sandisk Technologies Inc. | Air isolation in high density non-volatile memory |
JP2012204537A (ja) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP5076000B2 (ja) * | 2011-04-08 | 2012-11-21 | 株式会社東芝 | 半導体記憶装置および半導体記憶装置の製造方法 |
US20120280325A1 (en) * | 2011-05-03 | 2012-11-08 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
KR20120124706A (ko) * | 2011-05-04 | 2012-11-14 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조방법 |
KR20120131879A (ko) * | 2011-05-26 | 2012-12-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR20130025204A (ko) * | 2011-09-01 | 2013-03-11 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
KR20130036553A (ko) * | 2011-10-04 | 2013-04-12 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조 방법 |
JP2013122959A (ja) * | 2011-12-09 | 2013-06-20 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 |
US9123714B2 (en) | 2012-02-16 | 2015-09-01 | Sandisk Technologies Inc. | Metal layer air gap formation |
JP2013187335A (ja) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2013191680A (ja) * | 2012-03-13 | 2013-09-26 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
JP5668006B2 (ja) * | 2012-03-19 | 2015-02-12 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP2013197482A (ja) * | 2012-03-22 | 2013-09-30 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 |
KR101929453B1 (ko) * | 2012-03-27 | 2018-12-14 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR101901779B1 (ko) * | 2012-03-30 | 2018-09-28 | 삼성전자주식회사 | 반도체 소자 및 이를 제조하는 방법 |
US8778758B2 (en) * | 2012-08-30 | 2014-07-15 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and semiconductor device |
JP2014056899A (ja) * | 2012-09-11 | 2014-03-27 | Toshiba Corp | 不揮発性記憶装置およびその製造方法 |
US8890254B2 (en) * | 2012-09-14 | 2014-11-18 | Macronix International Co., Ltd. | Airgap structure and method of manufacturing thereof |
US9123577B2 (en) | 2012-12-12 | 2015-09-01 | Sandisk Technologies Inc. | Air gap isolation in non-volatile memory using sacrificial films |
US9349740B2 (en) | 2014-01-24 | 2016-05-24 | Sandisk Technologies Inc. | Non-volatile storage element with suspended charge storage region |
US9177853B1 (en) | 2014-05-14 | 2015-11-03 | Sandisk Technologies Inc. | Barrier layer stack for bit line air gap formation |
US9478461B2 (en) | 2014-09-24 | 2016-10-25 | Sandisk Technologies Llc | Conductive line structure with openings |
US9524904B2 (en) | 2014-10-21 | 2016-12-20 | Sandisk Technologies Llc | Early bit line air gap formation |
US9847249B2 (en) | 2014-11-05 | 2017-12-19 | Sandisk Technologies Llc | Buried etch stop layer for damascene bit line formation |
US9401305B2 (en) | 2014-11-05 | 2016-07-26 | Sandisk Technologies Llc | Air gaps structures for damascene metal patterning |
US9524973B1 (en) | 2015-06-30 | 2016-12-20 | Sandisk Technologies Llc | Shallow trench air gaps and their formation |
US9524974B1 (en) | 2015-07-22 | 2016-12-20 | Sandisk Technologies Llc | Alternating sidewall assisted patterning |
US9627399B2 (en) * | 2015-07-24 | 2017-04-18 | Sandisk Technologies Llc | Three-dimensional memory device with metal and silicide control gates |
US9607997B1 (en) | 2015-09-08 | 2017-03-28 | Sandisk Technologies Inc. | Metal line with increased inter-metal breakdown voltage |
US9391081B1 (en) | 2015-09-08 | 2016-07-12 | Sandisk Technologies Llc | Metal indentation to increase inter-metal breakdown voltage |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11317464A (ja) * | 1998-03-02 | 1999-11-16 | Sony Corp | 電気的書き換えが可能なメモリ素子及びその製造方法 |
JP4130494B2 (ja) * | 1998-03-30 | 2008-08-06 | 株式会社東芝 | 不揮発性半導体メモリ |
US6353242B1 (en) * | 1998-03-30 | 2002-03-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory |
JP3246442B2 (ja) * | 1998-05-27 | 2002-01-15 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2000012863A (ja) | 1998-06-19 | 2000-01-14 | Sanyo Electric Co Ltd | 薄膜トランジスタ及びそれを用いた表示装置 |
KR100269628B1 (ko) * | 1998-09-21 | 2000-10-16 | 김영환 | 반도체장치의 제조방법 |
JP2000311992A (ja) | 1999-04-26 | 2000-11-07 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2002280463A (ja) | 2001-03-16 | 2002-09-27 | Toshiba Corp | 半導体装置及びその製造方法 |
US6894341B2 (en) * | 2001-12-25 | 2005-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method |
JP4102112B2 (ja) * | 2002-06-06 | 2008-06-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100454136B1 (ko) * | 2002-10-23 | 2004-10-26 | 삼성전자주식회사 | 플로팅 게이트의 전하 손실을 막을 수 있는 비휘발성메모리 장치 및 그 제조방법 |
JP2006060138A (ja) | 2004-08-23 | 2006-03-02 | Toshiba Corp | 半導体集積回路装置 |
JP4410075B2 (ja) | 2004-09-28 | 2010-02-03 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4528700B2 (ja) | 2005-09-09 | 2010-08-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100809328B1 (ko) * | 2006-07-19 | 2008-03-05 | 삼성전자주식회사 | 비휘발성 메모리 집적 회로 장치의 제조 방법 및 이를통해서 제조된 비휘발성 메모리 집적 회로 장치 |
KR100854498B1 (ko) * | 2006-09-04 | 2008-08-26 | 삼성전자주식회사 | 펀치쓰루 억제용 불순물 영역을 갖는 선택 트랜지스터들을구비하는 낸드형 플래쉬 메모리 소자 및 그 제조방법 |
-
2006
- 2006-09-20 JP JP2006254385A patent/JP2008078298A/ja active Pending
-
2007
- 2007-09-19 KR KR1020070095297A patent/KR100936585B1/ko not_active IP Right Cessation
- 2007-09-20 US US11/858,585 patent/US7800155B2/en active Active
- 2007-09-20 CN CN200710153513.6A patent/CN100543967C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
KR20080026509A (ko) | 2008-03-25 |
US20080246075A1 (en) | 2008-10-09 |
KR100936585B1 (ko) | 2010-01-13 |
CN101150090A (zh) | 2008-03-26 |
US7800155B2 (en) | 2010-09-21 |
JP2008078298A (ja) | 2008-04-03 |
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Effective date of registration: 20170803 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
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Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. |
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Effective date of registration: 20211229 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |