CN100517602C - 基板的处理方法、电子器件的制造方法和程序 - Google Patents
基板的处理方法、电子器件的制造方法和程序 Download PDFInfo
- Publication number
- CN100517602C CN100517602C CNB2006100074778A CN200610007477A CN100517602C CN 100517602 C CN100517602 C CN 100517602C CN B2006100074778 A CNB2006100074778 A CN B2006100074778A CN 200610007477 A CN200610007477 A CN 200610007477A CN 100517602 C CN100517602 C CN 100517602C
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating film
- dielectric constant
- low dielectric
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
- H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
-
- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04C—STRUCTURAL ELEMENTS; BUILDING MATERIALS
- E04C2/00—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels
- E04C2/30—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure
- E04C2/32—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material
- E04C2/322—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material with parallel corrugations
-
- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04B—GENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
- E04B1/00—Constructions in general; Structures which are not restricted either to walls, e.g. partitions, or floors or ceilings or roofs
- E04B1/38—Connections for building structures in general
- E04B1/61—Connections for building structures in general of slab-shaped building elements with each other
- E04B1/6108—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together
- E04B1/612—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces
- E04B1/6125—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface
- E04B1/6137—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface the connection made by formlocking
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0452—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0452—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
- H10P72/0454—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers surrounding a central transfer chamber
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0462—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the construction of the processing chambers, e.g. modular processing chambers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0466—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the construction of the load-lock chamber
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005036716 | 2005-02-14 | ||
| JP2005036716 | 2005-02-14 | ||
| JP2005278843 | 2005-09-26 | ||
| JP2005278843A JP4860219B2 (ja) | 2005-02-14 | 2005-09-26 | 基板の処理方法、電子デバイスの製造方法及びプログラム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1822326A CN1822326A (zh) | 2006-08-23 |
| CN100517602C true CN100517602C (zh) | 2009-07-22 |
Family
ID=36480956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100074778A Expired - Lifetime CN100517602C (zh) | 2005-02-14 | 2006-02-14 | 基板的处理方法、电子器件的制造方法和程序 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7682517B2 (https=) |
| EP (1) | EP1691408A3 (https=) |
| JP (1) | JP4860219B2 (https=) |
| KR (1) | KR100830736B1 (https=) |
| CN (1) | CN100517602C (https=) |
| TW (1) | TWI456691B (https=) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7795148B2 (en) * | 2006-03-28 | 2010-09-14 | Tokyo Electron Limited | Method for removing damaged dielectric material |
| JP2008034736A (ja) * | 2006-07-31 | 2008-02-14 | Tokyo Electron Ltd | 熱処理方法および熱処理装置 |
| US7723237B2 (en) * | 2006-12-15 | 2010-05-25 | Tokyo Electron Limited | Method for selective removal of damaged multi-stack bilayer films |
| JP2008192835A (ja) * | 2007-02-05 | 2008-08-21 | Tokyo Electron Ltd | 成膜方法,基板処理装置,および半導体装置 |
| JP5543336B2 (ja) | 2007-05-18 | 2014-07-09 | ブルックス オートメーション インコーポレイテッド | 高速スワップロボット付コンパクト基板搬送システム |
| TW200908129A (en) * | 2007-06-22 | 2009-02-16 | Ulvac Inc | Method for protecting semiconductor wafer and process for producing semiconductor device |
| TWI459851B (zh) * | 2007-09-10 | 2014-11-01 | 日本碍子股份有限公司 | heating equipment |
| JP5374039B2 (ja) * | 2007-12-27 | 2013-12-25 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置及び記憶媒体 |
| JP5084525B2 (ja) * | 2008-01-22 | 2012-11-28 | 株式会社アルバック | 基板処理装置、及び基板処理方法 |
| JP2010278040A (ja) * | 2009-05-26 | 2010-12-09 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
| US12444651B2 (en) | 2009-08-04 | 2025-10-14 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| US8696815B2 (en) | 2009-09-01 | 2014-04-15 | Samsung Display Co., Ltd. | Thin film deposition apparatus |
| KR101732023B1 (ko) * | 2010-12-23 | 2017-05-02 | 삼성전자주식회사 | 반도체 장치의 형성 방법 |
| US8580664B2 (en) | 2011-03-31 | 2013-11-12 | Tokyo Electron Limited | Method for forming ultra-shallow boron doping regions by solid phase diffusion |
| US8569158B2 (en) | 2011-03-31 | 2013-10-29 | Tokyo Electron Limited | Method for forming ultra-shallow doping regions by solid phase diffusion |
| KR20130004830A (ko) * | 2011-07-04 | 2013-01-14 | 삼성디스플레이 주식회사 | 유기층 증착 장치 및 이를 이용한 유기 발광 표시 장치의 제조 방법 |
| JP2013048127A (ja) * | 2011-07-26 | 2013-03-07 | Applied Materials Inc | アッシュ後の側壁の回復 |
| CN102931130A (zh) * | 2011-08-11 | 2013-02-13 | 应用材料公司 | 灰化后侧壁修复 |
| JP6110848B2 (ja) * | 2012-05-23 | 2017-04-05 | 東京エレクトロン株式会社 | ガス処理方法 |
| US8871639B2 (en) | 2013-01-04 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US9543163B2 (en) | 2013-08-20 | 2017-01-10 | Applied Materials, Inc. | Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process |
| US9576811B2 (en) | 2015-01-12 | 2017-02-21 | Lam Research Corporation | Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch) |
| US9899224B2 (en) | 2015-03-03 | 2018-02-20 | Tokyo Electron Limited | Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions |
| US9806252B2 (en) | 2015-04-20 | 2017-10-31 | Lam Research Corporation | Dry plasma etch method to pattern MRAM stack |
| US9870899B2 (en) | 2015-04-24 | 2018-01-16 | Lam Research Corporation | Cobalt etch back |
| US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
| US10096487B2 (en) | 2015-08-19 | 2018-10-09 | Lam Research Corporation | Atomic layer etching of tungsten and other metals |
| US9984858B2 (en) | 2015-09-04 | 2018-05-29 | Lam Research Corporation | ALE smoothness: in and outside semiconductor industry |
| US10727073B2 (en) | 2016-02-04 | 2020-07-28 | Lam Research Corporation | Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces |
| US10229837B2 (en) | 2016-02-04 | 2019-03-12 | Lam Research Corporation | Control of directionality in atomic layer etching |
| US9991128B2 (en) | 2016-02-05 | 2018-06-05 | Lam Research Corporation | Atomic layer etching in continuous plasma |
| US10269566B2 (en) | 2016-04-29 | 2019-04-23 | Lam Research Corporation | Etching substrates using ale and selective deposition |
| US9837312B1 (en) | 2016-07-22 | 2017-12-05 | Lam Research Corporation | Atomic layer etching for enhanced bottom-up feature fill |
| JP6738485B2 (ja) * | 2016-08-26 | 2020-08-12 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 低圧リフトピンキャビティハードウェア |
| US10566212B2 (en) | 2016-12-19 | 2020-02-18 | Lam Research Corporation | Designer atomic layer etching |
| US10559451B2 (en) * | 2017-02-15 | 2020-02-11 | Applied Materials, Inc. | Apparatus with concentric pumping for multiple pressure regimes |
| JP6956551B2 (ja) * | 2017-03-08 | 2021-11-02 | 東京エレクトロン株式会社 | 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム |
| US20180261464A1 (en) * | 2017-03-08 | 2018-09-13 | Tokyo Electron Limited | Oxide film removing method, oxide film removing apparatus, contact forming method, and contact forming system |
| US10559461B2 (en) | 2017-04-19 | 2020-02-11 | Lam Research Corporation | Selective deposition with atomic layer etch reset |
| US10832909B2 (en) | 2017-04-24 | 2020-11-10 | Lam Research Corporation | Atomic layer etch, reactive precursors and energetic sources for patterning applications |
| US9997371B1 (en) | 2017-04-24 | 2018-06-12 | Lam Research Corporation | Atomic layer etch methods and hardware for patterning applications |
| WO2019190781A1 (en) | 2018-03-30 | 2019-10-03 | Lam Research Corporation | Atomic layer etching and smoothing of refractory metals and other high surface binding energy materials |
| US11131919B2 (en) * | 2018-06-22 | 2021-09-28 | International Business Machines Corporation | Extreme ultraviolet (EUV) mask stack processing |
| JP7349861B2 (ja) * | 2019-09-24 | 2023-09-25 | 東京エレクトロン株式会社 | エッチング方法、ダメージ層の除去方法、および記憶媒体 |
| WO2021178399A1 (en) | 2020-03-06 | 2021-09-10 | Lam Research Corporation | Atomic layer etching of molybdenum |
| TWI895472B (zh) * | 2020-08-17 | 2025-09-01 | 日商東京威力科創股份有限公司 | 蝕刻方法及蝕刻裝置 |
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| EP0376252B1 (en) * | 1988-12-27 | 1997-10-22 | Kabushiki Kaisha Toshiba | Method of removing an oxide film on a substrate |
| US6562544B1 (en) * | 1996-11-04 | 2003-05-13 | Applied Materials, Inc. | Method and apparatus for improving accuracy in photolithographic processing of substrates |
| JP3869089B2 (ja) * | 1996-11-14 | 2007-01-17 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
| US6074951A (en) * | 1997-05-29 | 2000-06-13 | International Business Machines Corporation | Vapor phase etching of oxide masked by resist or masking material |
| JPH1174354A (ja) * | 1997-06-30 | 1999-03-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| US6805139B1 (en) * | 1999-10-20 | 2004-10-19 | Mattson Technology, Inc. | Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing |
| US6265320B1 (en) * | 1999-12-21 | 2001-07-24 | Novellus Systems, Inc. | Method of minimizing reactive ion etch damage of organic insulating layers in semiconductor fabrication |
| US6677549B2 (en) * | 2000-07-24 | 2004-01-13 | Canon Kabushiki Kaisha | Plasma processing apparatus having permeable window covered with light shielding film |
| KR100365641B1 (ko) * | 2000-07-29 | 2002-12-26 | 삼성전자 주식회사 | 배선에 의한 기생 용량을 줄일 수 있는 반도체 장치 및 그형성방법 |
| TW461051B (en) * | 2000-11-10 | 2001-10-21 | Silicon Based Tech Corp | Manufacturing of shrinkable split-gate flash memory with three-sided erase electrodes |
| US6926843B2 (en) * | 2000-11-30 | 2005-08-09 | International Business Machines Corporation | Etching of hard masks |
| JP2002303993A (ja) * | 2001-04-04 | 2002-10-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2002353308A (ja) * | 2001-05-28 | 2002-12-06 | Toshiba Corp | 半導体装置及びその製造方法 |
| TW504799B (en) * | 2001-12-28 | 2002-10-01 | Shr Min | Copper line fabrication method |
| US6660598B2 (en) * | 2002-02-26 | 2003-12-09 | International Business Machines Corporation | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region |
| JP3606272B2 (ja) * | 2002-06-26 | 2005-01-05 | 松下電器産業株式会社 | 配線構造の形成方法 |
| JP3909283B2 (ja) * | 2002-10-31 | 2007-04-25 | 富士通株式会社 | 半導体装置の製造方法 |
| US6838300B2 (en) * | 2003-02-04 | 2005-01-04 | Texas Instruments Incorporated | Chemical treatment of low-k dielectric films |
| JP2004247417A (ja) * | 2003-02-12 | 2004-09-02 | Renesas Technology Corp | 半導体装置の製造方法 |
| US7079760B2 (en) * | 2003-03-17 | 2006-07-18 | Tokyo Electron Limited | Processing system and method for thermally treating a substrate |
| US6951821B2 (en) * | 2003-03-17 | 2005-10-04 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US7029536B2 (en) * | 2003-03-17 | 2006-04-18 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US6905941B2 (en) * | 2003-06-02 | 2005-06-14 | International Business Machines Corporation | Structure and method to fabricate ultra-thin Si channel devices |
| JP4833512B2 (ja) * | 2003-06-24 | 2011-12-07 | 東京エレクトロン株式会社 | 被処理体処理装置、被処理体処理方法及び被処理体搬送方法 |
| US7097779B2 (en) * | 2004-07-06 | 2006-08-29 | Tokyo Electron Limited | Processing system and method for chemically treating a TERA layer |
-
2005
- 2005-09-26 JP JP2005278843A patent/JP4860219B2/ja not_active Expired - Lifetime
-
2006
- 2006-02-13 KR KR1020060013738A patent/KR100830736B1/ko not_active Expired - Lifetime
- 2006-02-13 TW TW095104740A patent/TWI456691B/zh not_active IP Right Cessation
- 2006-02-14 CN CNB2006100074778A patent/CN100517602C/zh not_active Expired - Lifetime
- 2006-02-14 EP EP06002925A patent/EP1691408A3/en not_active Withdrawn
- 2006-02-14 US US11/353,132 patent/US7682517B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7682517B2 (en) | 2010-03-23 |
| EP1691408A3 (en) | 2010-01-06 |
| TWI456691B (zh) | 2014-10-11 |
| EP1691408A2 (en) | 2006-08-16 |
| KR100830736B1 (ko) | 2008-05-20 |
| US20060194435A1 (en) | 2006-08-31 |
| JP4860219B2 (ja) | 2012-01-25 |
| TW200636914A (en) | 2006-10-16 |
| JP2006253634A (ja) | 2006-09-21 |
| CN1822326A (zh) | 2006-08-23 |
| KR20060018918A (ko) | 2006-03-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090722 |
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| CX01 | Expiry of patent term |