CN100502032C - 用于不对称半导体器件性能增强的方法和设备 - Google Patents
用于不对称半导体器件性能增强的方法和设备 Download PDFInfo
- Publication number
- CN100502032C CN100502032C CNB2005800272611A CN200580027261A CN100502032C CN 100502032 C CN100502032 C CN 100502032C CN B2005800272611 A CNB2005800272611 A CN B2005800272611A CN 200580027261 A CN200580027261 A CN 200580027261A CN 100502032 C CN100502032 C CN 100502032C
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/924,650 US7166897B2 (en) | 2004-08-24 | 2004-08-24 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device |
| US10/924,650 | 2004-08-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101002328A CN101002328A (zh) | 2007-07-18 |
| CN100502032C true CN100502032C (zh) | 2009-06-17 |
Family
ID=35941869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005800272611A Expired - Fee Related CN100502032C (zh) | 2004-08-24 | 2005-07-15 | 用于不对称半导体器件性能增强的方法和设备 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7166897B2 (https=) |
| JP (1) | JP2008511169A (https=) |
| KR (1) | KR101174994B1 (https=) |
| CN (1) | CN100502032C (https=) |
| TW (1) | TWI411106B (https=) |
| WO (1) | WO2006023183A2 (https=) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2868207B1 (fr) * | 2004-03-25 | 2006-09-08 | Commissariat Energie Atomique | Transistor a effet de champ a materiaux de source, de drain et de canal adaptes et circuit integre comportant un tel transistor |
| KR100642747B1 (ko) * | 2004-06-22 | 2006-11-10 | 삼성전자주식회사 | Cmos 트랜지스터의 제조방법 및 그에 의해 제조된cmos 트랜지스터 |
| US20070090406A1 (en) * | 2005-10-26 | 2007-04-26 | International Business Machines Corporation | Structure and method for manufacturing high performance and low leakage field effect transistor |
| US8441000B2 (en) | 2006-02-01 | 2013-05-14 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US7943471B1 (en) * | 2006-05-15 | 2011-05-17 | Globalfoundries Inc. | Diode with asymmetric silicon germanium anode |
| US7799644B2 (en) * | 2006-07-28 | 2010-09-21 | Freescale Semiconductor, Inc. | Transistor with asymmetry for data storage circuitry |
| US8809939B2 (en) | 2007-03-28 | 2014-08-19 | Renesas Electronics Corporation | Semiconductor device |
| JP5286701B2 (ja) | 2007-06-27 | 2013-09-11 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
| US7741658B2 (en) * | 2007-08-21 | 2010-06-22 | International Business Machines Corporation | Self-aligned super stressed PFET |
| JP2009164364A (ja) * | 2008-01-08 | 2009-07-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US8384122B1 (en) * | 2008-04-17 | 2013-02-26 | The Regents Of The University Of California | Tunneling transistor suitable for low voltage operation |
| US7964465B2 (en) * | 2008-04-17 | 2011-06-21 | International Business Machines Corporation | Transistors having asymmetric strained source/drain portions |
| US20110049582A1 (en) * | 2009-09-03 | 2011-03-03 | International Business Machines Corporation | Asymmetric source and drain stressor regions |
| US9577079B2 (en) * | 2009-12-17 | 2017-02-21 | Infineon Technologies Ag | Tunnel field effect transistors |
| US8928094B2 (en) | 2010-09-03 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained asymmetric source/drain |
| US8637871B2 (en) * | 2010-11-04 | 2014-01-28 | International Business Machines Corporation | Asymmetric hetero-structure FET and method of manufacture |
| CN103377940B (zh) * | 2012-04-25 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 一种用于sram的p型传输栅极晶体管及其制作方法 |
| US10103226B2 (en) * | 2012-04-30 | 2018-10-16 | International Business Machines Corporation | Method of fabricating tunnel transistors with abrupt junctions |
| CN103426756B (zh) * | 2012-05-15 | 2016-02-10 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| US8836041B2 (en) * | 2012-11-16 | 2014-09-16 | Stmicroelectronics, Inc. | Dual EPI CMOS integration for planar substrates |
| EP3061124A4 (en) * | 2013-09-26 | 2017-04-26 | Intel Corporation | Vertical non-planar semiconductor device for system-on-chip (soc) applications |
| US9525027B2 (en) * | 2014-03-13 | 2016-12-20 | Globalfoundries Inc. | Lateral bipolar junction transistor having graded SiGe base |
| US9391204B1 (en) * | 2015-03-12 | 2016-07-12 | International Business Machines Corporation | Asymmetric FET |
| US10026830B2 (en) * | 2015-04-29 | 2018-07-17 | Stmicroelectronics, Inc. | Tunneling field effect transistor (TFET) having a semiconductor fin structure |
| WO2017111874A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Dual threshold voltage (vt) channel devices and their methods of fabrication |
| WO2018063335A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Tunneling transistors including source/drain regions employing carbon-based etch stop layer |
| WO2018063333A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Tunneling transistors including source/drain regions processed through contact trenches |
| WO2018063315A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Tunneling transistors including source/drain regions employing contact resistance reducing layer |
| WO2018063310A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Tunneling transistors including source/drain regions employing different semiconductor material |
| CN108122973B (zh) * | 2016-11-28 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法、以及sram |
| JP2018125518A (ja) * | 2017-02-03 | 2018-08-09 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ、製造方法 |
| CN108417489B (zh) * | 2017-02-10 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Sram存储器及其形成方法 |
| CN108470734A (zh) * | 2017-02-23 | 2018-08-31 | 中芯国际集成电路制造(上海)有限公司 | Sram存储器及其形成方法 |
| CN108987399A (zh) * | 2017-06-05 | 2018-12-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
| TWI788487B (zh) | 2018-12-21 | 2023-01-01 | 聯華電子股份有限公司 | 半導體元件 |
| US11201246B2 (en) | 2019-11-12 | 2021-12-14 | International Business Machines Corporation | Field-effect transistor structure and fabrication method |
| US11621340B2 (en) * | 2019-11-12 | 2023-04-04 | International Business Machines Corporation | Field-effect transistor structure and fabrication method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040061191A1 (en) * | 2002-09-30 | 2004-04-01 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
| US20040084735A1 (en) * | 2001-11-01 | 2004-05-06 | Anand Murthy | Semiconductor transistor having a stressed channel |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3144032B2 (ja) * | 1992-03-30 | 2001-03-07 | ソニー株式会社 | 薄膜トランジスタ及びその製造方法 |
| US5789306A (en) | 1996-04-18 | 1998-08-04 | Micron Technology, Inc. | Dual-masked field isolation |
| US5849440A (en) | 1996-07-02 | 1998-12-15 | Motorola, Inc. | Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same |
| US5858830A (en) | 1997-06-12 | 1999-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making dual isolation regions for logic and embedded memory devices |
| JP2000286420A (ja) * | 1999-03-30 | 2000-10-13 | Canon Inc | 絶縁ゲート型トランジスタの製造方法および絶縁ゲート型トランジスタ |
| US6197632B1 (en) | 1999-11-16 | 2001-03-06 | International Business Machines Corporation | Method for dual sidewall oxidation in high density, high performance DRAMS |
| JP2001284598A (ja) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| US6541382B1 (en) | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
| JP2002134741A (ja) * | 2000-10-20 | 2002-05-10 | Seiko Epson Corp | 半導体装置とその製造方法 |
| US7312485B2 (en) | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
| US6605498B1 (en) | 2002-03-29 | 2003-08-12 | Intel Corporation | Semiconductor transistor having a backfilled channel material |
| JP3963462B2 (ja) * | 2003-12-24 | 2007-08-22 | 株式会社東芝 | 半導体装置の製造方法 |
| US7413957B2 (en) * | 2004-06-24 | 2008-08-19 | Applied Materials, Inc. | Methods for forming a transistor |
-
2004
- 2004-08-24 US US10/924,650 patent/US7166897B2/en not_active Expired - Lifetime
-
2005
- 2005-07-15 KR KR1020077004356A patent/KR101174994B1/ko not_active Expired - Fee Related
- 2005-07-15 JP JP2007529858A patent/JP2008511169A/ja active Pending
- 2005-07-15 WO PCT/US2005/025535 patent/WO2006023183A2/en not_active Ceased
- 2005-07-15 CN CNB2005800272611A patent/CN100502032C/zh not_active Expired - Fee Related
- 2005-08-03 TW TW094126428A patent/TWI411106B/zh not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040084735A1 (en) * | 2001-11-01 | 2004-05-06 | Anand Murthy | Semiconductor transistor having a stressed channel |
| US20040061191A1 (en) * | 2002-09-30 | 2004-04-01 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070051866A (ko) | 2007-05-18 |
| TWI411106B (zh) | 2013-10-01 |
| JP2008511169A (ja) | 2008-04-10 |
| TW200629540A (en) | 2006-08-16 |
| WO2006023183A3 (en) | 2006-05-04 |
| US20060043498A1 (en) | 2006-03-02 |
| US7166897B2 (en) | 2007-01-23 |
| WO2006023183A2 (en) | 2006-03-02 |
| CN101002328A (zh) | 2007-07-18 |
| KR101174994B1 (ko) | 2012-08-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP America Co Ltd Address before: Texas in the United States Patentee before: Fisical Semiconductor Inc. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090617 Termination date: 20190715 |