CN100501968C - 增强的浅沟槽隔离结构及其制作方法 - Google Patents
增强的浅沟槽隔离结构及其制作方法 Download PDFInfo
- Publication number
- CN100501968C CN100501968C CNB2006101542012A CN200610154201A CN100501968C CN 100501968 C CN100501968 C CN 100501968C CN B2006101542012 A CNB2006101542012 A CN B2006101542012A CN 200610154201 A CN200610154201 A CN 200610154201A CN 100501968 C CN100501968 C CN 100501968C
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- deposit
- isolation structure
- window
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/321,206 | 2005-12-29 | ||
| US11/321,206 US7514336B2 (en) | 2005-12-29 | 2005-12-29 | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1992194A CN1992194A (zh) | 2007-07-04 |
| CN100501968C true CN100501968C (zh) | 2009-06-17 |
Family
ID=38068283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101542012A Expired - Fee Related CN100501968C (zh) | 2005-12-29 | 2006-09-13 | 增强的浅沟槽隔离结构及其制作方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7514336B2 (enExample) |
| EP (1) | EP1806780A3 (enExample) |
| JP (1) | JP5579358B2 (enExample) |
| KR (1) | KR101292025B1 (enExample) |
| CN (1) | CN100501968C (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514336B2 (en) * | 2005-12-29 | 2009-04-07 | Agere Systems Inc. | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures |
| US20110244683A1 (en) * | 2010-04-01 | 2011-10-06 | Michiaki Sano | Fabricating Voids Using Slurry Protect Coat Before Chemical-Mechanical Polishing |
| CN103531519B (zh) * | 2012-07-02 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| US9768055B2 (en) * | 2012-08-21 | 2017-09-19 | Stmicroelectronics, Inc. | Isolation regions for SOI devices |
| US10468529B2 (en) | 2017-07-11 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with etch stop layer |
| KR102661930B1 (ko) | 2018-08-13 | 2024-04-29 | 삼성전자주식회사 | 집적회로 소자 |
| CN109273532B (zh) * | 2018-09-12 | 2022-03-11 | 上海华力微电子有限公司 | 应用于高压电路防静电保护的无回滞效应硅控整流器 |
| CN116053211A (zh) * | 2022-12-30 | 2023-05-02 | 联合微电子中心有限责任公司 | 一种防止源漏区漏电的结构及其制备方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1239821A (zh) * | 1998-06-24 | 1999-12-29 | 三星电子株式会社 | 形成没有凹陷的沟槽隔离的方法 |
| US6187651B1 (en) * | 1998-05-07 | 2001-02-13 | Samsung Electronics Co., Ltd. | Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids |
| US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330410A (ja) * | 1995-05-31 | 1996-12-13 | Sony Corp | 素子分離方法、素子分離構造、及び半導体装置 |
| TW388100B (en) * | 1997-02-18 | 2000-04-21 | Hitachi Ulsi Eng Corp | Semiconductor deivce and process for producing the same |
| US6228741B1 (en) * | 1998-01-13 | 2001-05-08 | Texas Instruments Incorporated | Method for trench isolation of semiconductor devices |
| WO1999044223A2 (en) * | 1998-02-27 | 1999-09-02 | Lsi Logic Corporation | Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing |
| TW398053B (en) * | 1998-07-31 | 2000-07-11 | United Microelectronics Corp | Manufacturing of shallow trench isolation |
| JP2000223704A (ja) * | 1999-01-29 | 2000-08-11 | Sony Corp | 半導体装置およびその製造方法 |
| US6255194B1 (en) * | 1999-06-03 | 2001-07-03 | Samsung Electronics Co., Ltd. | Trench isolation method |
| US6500729B1 (en) * | 2000-06-02 | 2002-12-31 | Agere Systems Guardian Corp. | Method for reducing dishing related issues during the formation of shallow trench isolation structures |
| US6921947B2 (en) * | 2000-12-15 | 2005-07-26 | Renesas Technology Corp. | Semiconductor device having recessed isolation insulation film |
| KR100568100B1 (ko) * | 2001-03-05 | 2006-04-05 | 삼성전자주식회사 | 트렌치형 소자 분리막 형성 방법 |
| JP2003151956A (ja) * | 2001-11-19 | 2003-05-23 | Sony Corp | 半導体装置製造工程における窒化シリコン膜のエッチング方法 |
| TW540135B (en) * | 2002-04-24 | 2003-07-01 | Nanya Technology Corp | Method of forming shallow trench isolation region |
| KR20040002147A (ko) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
| JP2004311487A (ja) * | 2003-04-02 | 2004-11-04 | Hitachi Ltd | 半導体装置の製造方法 |
| KR100505419B1 (ko) * | 2003-04-23 | 2005-08-04 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 제조방법 |
| JP2004363486A (ja) * | 2003-06-06 | 2004-12-24 | Renesas Technology Corp | トレンチ分離を有する半導体装置およびその製造方法 |
| JP2005166700A (ja) * | 2003-11-28 | 2005-06-23 | Toshiba Corp | 半導体装置及びその製造方法 |
| KR100538811B1 (ko) * | 2003-12-29 | 2005-12-23 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
| US7514336B2 (en) | 2005-12-29 | 2009-04-07 | Agere Systems Inc. | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures |
-
2005
- 2005-12-29 US US11/321,206 patent/US7514336B2/en not_active Expired - Fee Related
-
2006
- 2006-09-06 EP EP06254630A patent/EP1806780A3/en not_active Withdrawn
- 2006-09-13 CN CNB2006101542012A patent/CN100501968C/zh not_active Expired - Fee Related
- 2006-12-22 JP JP2006345124A patent/JP5579358B2/ja active Active
- 2006-12-29 KR KR1020060137758A patent/KR101292025B1/ko not_active Expired - Fee Related
-
2009
- 2009-01-21 US US12/356,600 patent/US8022481B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6187651B1 (en) * | 1998-05-07 | 2001-02-13 | Samsung Electronics Co., Ltd. | Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids |
| CN1239821A (zh) * | 1998-06-24 | 1999-12-29 | 三星电子株式会社 | 形成没有凹陷的沟槽隔离的方法 |
| US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5579358B2 (ja) | 2014-08-27 |
| EP1806780A2 (en) | 2007-07-11 |
| EP1806780A3 (en) | 2011-06-01 |
| KR20070072408A (ko) | 2007-07-04 |
| US7514336B2 (en) | 2009-04-07 |
| US20070152294A1 (en) | 2007-07-05 |
| CN1992194A (zh) | 2007-07-04 |
| JP2007184588A (ja) | 2007-07-19 |
| US8022481B2 (en) | 2011-09-20 |
| US20090127651A1 (en) | 2009-05-21 |
| KR101292025B1 (ko) | 2013-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: AGERE SYSTEMS GUARDIAN CORP. Free format text: FORMER NAME: EGREE SYSTEM CO. LTD. |
|
| CP03 | Change of name, title or address |
Address after: Delaware Patentee after: Agere Systems Inc. Address before: American Pennsylvania Patentee before: AGERE SYSTEMS Inc. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: American Pennsylvania Patentee after: Agere Systems Inc. Address before: Delaware Patentee before: Agere Systems Inc. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20160906 Address after: Singapore Singapore Patentee after: Avago Technologies General IP (Singapore) Pte. Ltd. Address before: American Pennsylvania Patentee before: Agere Systems Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090617 Termination date: 20160913 |
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| CF01 | Termination of patent right due to non-payment of annual fee |