CN1239821A - 形成没有凹陷的沟槽隔离的方法 - Google Patents

形成没有凹陷的沟槽隔离的方法 Download PDF

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CN1239821A
CN1239821A CN99109273A CN99109273A CN1239821A CN 1239821 A CN1239821 A CN 1239821A CN 99109273 A CN99109273 A CN 99109273A CN 99109273 A CN99109273 A CN 99109273A CN 1239821 A CN1239821 A CN 1239821A
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trench
nitride
mask
layer
liner
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南信祐
徐俊
崔昶源
洪瑛基
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Samsung Electronics Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

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Abstract

提供一种形成嵌埋于半导体衬底中的沟槽隔离的方法，其中采用干法腐蚀去掉氮化物沟槽掩模，以抑制氮化物沟槽衬里的凹陷现象。干法腐蚀以相同的腐蚀速率腐蚀沟槽掩模和沟槽衬里。

Description

形成没有凹陷的沟槽隔离的方法
本发明涉及半导体制造，特别涉及没有凹陷的沟槽隔离。
随着器件尺寸越来越小，并且器件密度增大，越来越难建立有效且可靠的隔离工艺，以隔离各有源器件。标准LOCOS工艺的局限推动了对新隔离技术的探索和开发，由于其采用完全隐埋的氧化物、没有鸟嘴、完全平面化、且不会发生场氧化物减薄效应，所以沟槽隔离是一种有前途的候选者。
一般情况下，浅沟槽隔离(此后称STI)包括利用沟槽掩模，并腐蚀硅衬底，在其中形成沟槽。氮化物层形成于沟槽内。淀积沟槽填充层，以填满沟槽。对沟槽填充层上进行平面化腐蚀，并去掉沟槽掩模。下面结合图1A-1D介绍常规STI法的缺点。
图1A是示意性显示沟槽16及沟槽掩模12和14的半导体衬底10的剖面图。沟槽掩模由氧化物层12和富硅氮化物层14构成，富硅氮化物层中的硅含量大于氮含量。氧化物层12利用热氧化工艺形成。沟槽掩模利用常规光刻工艺形成。通过各向异性干法腐蚀进行由该掩模暴露的半导体衬底10的腐蚀。
参见图1B，在沟槽内形成热氧化物层18，以便去掉腐蚀半导体衬底10的步骤引起的衬底损伤。在热氧化物层18上形成氮化硅衬里20，以防止沟槽内部氧化，众所周知，沟槽内的氧化会引起体积膨胀和相应的应力，这进而会增大漏电流，并使器件的刷新特性退化。淀积沟槽填充绝缘层22，完全填充沟槽16，以便隔离两有源区。沟槽填充层22一般是USG(未掺杂硅酸盐玻璃)。
参见图1C，向下平面化沟槽填充层22到氮化物沟槽掩模14。这种平面化可以包括化学机械抛光(CMP)。然后在磷酸中剥离氮化物沟槽掩模14。从图1D可以看出，氮化物沟槽掩模14的剥离造成了氮化物衬里20上缘处的凹陷(dent)现象24。具体说，在磷酸中的湿法腐蚀过程中，磷酸沿氮化物衬里20向下渗透，造成了凹陷现象24。这是由于富硅的氮化物沟槽掩模14在磷酸中的腐蚀比氮化物衬里20慢，约三分之一。换言之，氮化硅沟槽衬里20的腐蚀速率是富硅氮化物掩模14的三倍。
沟槽衬里20的凹陷造成了随后栅氧化物层的不均匀。栅多晶硅会留在凹陷部分，引起短路失效。希望氮化物衬里形成得厚，以便改善氧化阻挡层的特性。但沟槽衬里厚度增大，使衬里凹陷现象更严重。
因此，极需要一种形成沟槽隔离的方法，不仅能够抑制沟槽内的氧化，而且能够抑制氮化物衬里凹陷现象。
为了解决上述问题作出了本发明，因此本发明的目的是提供一种在半导体器件中形成沟槽隔离的方法，能够抑制沟槽衬里凹陷和沟槽内部氧化。本发明的主要特征是利用含Cl2的干法腐蚀来腐蚀沟槽掩模。该干法腐蚀对于富硅氮化物沟槽掩模和氮化硅沟槽衬里具有基本上相同的腐蚀速率。这里，所用术语“富硅氮化物层”是指其中具有比氮化硅层大的硅含量的氮化硅层。
通过在半导体衬底上形成氧化物层和富硅氮化物层可以实现本发明的上述和其它目的。进行光刻工艺，形成暴露半导体衬底的选择部分的沟槽掩模。各向异性腐蚀暴露的半导体衬底，在其中形成沟槽。在沟槽内形成热氧化物层，治疗腐蚀半导体衬底期间造成的衬底损伤。在热氧化物层上形成氮化硅沟槽衬里，防止其氧化。淀积如USG层的沟槽填充层，以完全填充沟槽的其余部分。根据该工艺步骤，可以进行退火，以致密化沟槽填充层。然后利用化学机械抛光技术向下平面化沟槽填充层到氮化物掩模。接下来的工艺步骤是本发明的关键。进行干法腐蚀，以去掉氮化物掩模。干法腐蚀含Cl2，并以相同的腐蚀速率腐蚀氮化物掩模和氮化物沟槽衬里。由于该干法腐蚀，可以抑制现有技术中发生的氮化物沟槽衬里凹陷。
结合如下各附图所属领域的技术人员可以理解本发明，并清楚本发明的目的：
图1A-1D是展示在各选择制造阶段的常规技术半导体衬底的剖面图；及
图2A-2D是展示在各选择制造阶段的本发明优选实施例的半导体衬底的剖面图。
下面结合附图介绍本发明的优选实施例。本发明涉及一种形成嵌埋于半导体衬底中的沟槽隔离以便隔离各有源区的方法。图2A是示意性展示沟槽106及沟槽掩模102和104的半导体衬底100的剖面图。沟槽掩模由氧化物层102和氮化物层104构成。氧化物层102利用热氧化工艺形成为厚约160埃-200埃。该热氧化物层102可减小由上层氮化物层104造成的作用于半导体衬底100上表面(具体说为有源区)的应力。该氮化物层由富硅氮化硅层构成，其中硅含量大于氮含量，以便减小作用于半导体衬底的有源区的应力。沟槽掩模利用常规光刻工艺形成。在富硅氮化硅层104上旋涂光刻胶层(未示出)，并构图成要求构形。该构图的光刻胶层将利用等离子灰化去掉。利用该构图的光刻胶层，腐蚀氮化物层104和氧化物层102，以形成暴露半导体衬底100的选择部分的沟槽掩模。利用该掩模，腐蚀暴露的半导体衬底，以形成沟槽106。利用各向异性干法腐蚀进行暴露的半导体衬底100的腐蚀。
参见图2B，在沟槽内即底部和侧壁上形成热氧化物层108，以便去除腐蚀半导体衬底100步骤造成的衬底损伤。在热氧化物层108上形成氮化硅沟槽衬里110，用于防止沟槽内部氧化。氮化硅衬里110防止了O2渗透通过随后的沟槽填充层112达到侧壁。为了充分防止氧化，形成厚约60埃或以上的氮化硅层112。众所周知，沟槽内部的氧化会引起体积膨胀和相应的应力，这进而会增大漏电流，并使器件的刷新操作特性退化。淀积沟槽填充绝缘层112，以完全填充沟槽106。沟槽填充层112包括USG(未掺杂硅酸盐玻璃)层。
参见图2C，向下平面化沟槽填充层112和氮化物沟槽衬里110到氮化物沟槽掩模104。这种平面化可以包括化学机械抛光(CMP)技术。这里，可以腐蚀掉氮化物沟槽掩模104的部分厚度。
下一工艺步骤是去掉氮化物沟槽掩模104。不象常规技术的湿法腐蚀那样，本发明采用干法腐蚀技术，以避免氮化物沟槽衬里110凹陷。干法腐蚀技术彼此没有腐蚀选择性地腐蚀氮化物沟槽掩模104和氮化物沟槽衬里110，即，不管硅组分比如何，基本上以相同的腐蚀速率进行腐蚀，因此，可以避免常规湿法腐蚀中发生的凹陷现象。图2D示意性地展示了沟槽隔离的所得外形。由于这种干法腐蚀，氮化物沟槽衬里104可以形成为厚度超过60埃，从而改善刷新特性。
该干法腐蚀采用氯(Cl2)基气体化学试剂。为了使半导体衬底的腐蚀损伤最小，以约为3∶1或以上的氮化物沟槽掩模104与氧化物层102的腐蚀速率比进行该干法腐蚀。
本发明提供了利用浅沟槽隔离技术电隔离各有源区的器件隔离区。所得沟槽隔离具有良好的绝缘特性，没有从相邻有源区的漏电。
所属领域的技术人员应认识到，本申请中公开的发明思想具有广泛的应用。另外，可以按不同的方式改变优选的实施方式。因此，应理解，以下和上述所提供出的改形和改变只是例示性的。这些例子有助于展示本发明思想的范围，但这些例子并未究尽所公开新思想的所有变化范围。

Claims (5)

1.一种形成半导体器件的沟槽隔离的方法，包括以下步骤：
在半导体衬底上提供氮化物沟槽掩模，以暴露所述半导体衬底的选择部分；
利用所述氮化物沟槽掩模，腐蚀所述暴露的半导体衬底，以在其中形成沟槽；
在所述沟槽内形成热氧化物层；
在所述热氧化物层上和所述氮化物沟槽掩模之上形成氮化物沟槽衬里；
在所述沟槽中和所述氮化物沟槽衬里上形成沟槽填充层；
平面化所述沟槽填充层和所述氮化物沟槽衬里，并停止在所述氮化物沟槽掩模；及
干法腐蚀所述沟槽外的氮化物沟槽掩模，并暴露所述半导体衬底。
2.根据权利要求1的方法，其中所述氮化物沟槽掩模包括富硅氮化硅层，所述氮化物沟槽衬里包括氮化硅层。
3.根据权利要求1的方法，其中所述沟槽填充层包括USG(未掺杂硅酸盐玻璃)。
4.根据权利要求1的方法，其中所述氮化物沟槽衬里的厚度约为60埃或以上。
5.根据权利要求1的方法，其中所述干法腐蚀利用Cl2气。
CN99109273A 1998-06-24 1999-06-24 形成没有凹陷的沟槽隔离的方法 Pending CN1239821A (zh)

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Cited By (2)

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CN1327503C (zh) * 2004-09-08 2007-07-18 上海宏力半导体制造有限公司 增进浅槽隔离结构高度均匀性的方法
CN100501968C (zh) * 2005-12-29 2009-06-17 艾格瑞系统有限公司 增强的浅沟槽隔离结构及其制作方法

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KR100698199B1 (ko) * 2001-06-05 2007-03-22 엘지전자 주식회사 전송 안테나 다이버시티 방법
JP2003273206A (ja) 2002-03-18 2003-09-26 Fujitsu Ltd 半導体装置とその製造方法
KR100429555B1 (ko) * 2002-06-29 2004-05-03 주식회사 하이닉스반도체 반도체 소자의 트렌치형 소자분리막 형성방법
JP2004193585A (ja) 2002-11-29 2004-07-08 Fujitsu Ltd 半導体装置の製造方法と半導体装置
KR100499642B1 (ko) * 2003-09-05 2005-07-05 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1327503C (zh) * 2004-09-08 2007-07-18 上海宏力半导体制造有限公司 增进浅槽隔离结构高度均匀性的方法
CN100501968C (zh) * 2005-12-29 2009-06-17 艾格瑞系统有限公司 增强的浅沟槽隔离结构及其制作方法

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