CN100501968C - 增强的浅沟槽隔离结构及其制作方法 - Google Patents

增强的浅沟槽隔离结构及其制作方法 Download PDF

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CN100501968C
CN100501968C CNB2006101542012A CN200610154201A CN100501968C CN 100501968 C CN100501968 C CN 100501968C CN B2006101542012 A CNB2006101542012 A CN B2006101542012A CN 200610154201 A CN200610154201 A CN 200610154201A CN 100501968 C CN100501968 C CN 100501968C
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semiconductor layer
deposit
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isolation structure
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CN1992194A (zh
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阿鲁纳·纳恩达
纳斯·罗西
拉恩伯·赛恩
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Avago Technologies International Sales Pte Ltd
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Abstract

一种半导体衬底中的浅沟槽隔离结构以及一种用来形成此浅沟槽隔离结构的方法，此浅沟槽隔离结构具有安置在沟槽填充材料的空洞中的介质材料。在介质材料被形成在沟槽中之后的清洗工艺过程中，可能形成这种空洞。共形氮化硅层被形成在衬底上和空洞内。在清除氮化硅层之后，这些空洞至少部分地被氮化硅材料填充。

Description

增强的浅沟槽隔离结构及其制作方法
技术领域
本发明一般涉及到集成电路，更确切地说是涉及到在集成电路内制作浅沟槽隔离(STI)结构的方法以及根据此方法制作的浅沟槽隔离结构。
背景技术
集成电路通常包含半导体衬底以及衬底内诸如包含掺杂区的晶体管之类的半导体器件。互连结构位于半导体衬底上，用来电连接各掺杂区以便形成电学器件和电路。常规的互连结构包含与导电层交替的介质层。介质层中基本上垂直的导电通道或栓塞对导电层中基本上水平的各导电轨线进行连接。
CMOS器件(互补金属氧化物半导体场效应晶体管)包含形成在相反地掺杂的相邻阱中的n沟道和p沟道金属氧化物半导体场效应晶体管(MOSFET)。各MOSFET还包含被沟道分隔开的源区和漏区、形成在沟道上方的栅氧化物、以及形成在栅氧化物上的掺杂多晶硅的栅电极。适当的栅电压使沟道反转，从而允许电流在源区与漏区之间流动。
在集成电路衬底中，可能必须对某些掺杂区进行电隔离，以便避免由各掺杂区之间不希望有的相互作用所形成的寄生器件。例如，由CMOS器件的各个阱以及掺杂的源区/漏区形成了寄生的双极结构例如p-n-p-n闸流管。此闸流管在正常的CMOS工作条件下是不工作的(关断)。但在某些偏置条件下，p-n-p区将基极电流馈送到n-p-n区，导致泄漏电流在CMOS器件的二个MOSFET之间流动，这能够引起CMOS器件闭锁。隔离结构通常被形成在相邻MOSFET之间的衬底内，以便防止此泄漏电流。
根据硅的局部氧化(LOCOS)工艺或根据浅沟槽隔离(STI)工艺形成的氧化物(二氧化硅)隔离区，对各相邻晶体管(或形成在集成电路中的其它器件)的掺杂区进行电隔离，以便尽可能减小泄漏电流，从而降低上述寄生效应。
硅的局部氧化工艺在半导体衬底的非有源区(场区)内形成了凹陷的LOCOS隔离区。根据一种LOCOS工艺，氮化硅层被淀积在衬底上，并根据常规的掩蔽和腐蚀步骤而被图形化，以便在氮化硅中形成暴露下方半导体衬底区的窗口。借助于通过窗口对暴露的半导体衬底进行氧化，来形成各隔离的LOCOS区。在被氮化硅掩蔽的区域内不发生氧化。
STI结构包含用来隔离各有源器件的介质填充的衬底沟槽(深度约为300nm)。STI结构占据较小的衬底表面积且上部表面的形貌更平坦，故浅沟槽隔离结构比LOCOS结构更为优越。占据面积的减小使电路设计者能够在集成电路的单位面积内包括更多的晶体管。对于形成尺寸适当的上方材料层以及精确的光刻图形化来说，更为平坦的上部表面形貌是有好处的。
对尺寸小于大约0.25微米的器件特别有用的STI结构，还由于形成在STI沟槽底部处的尖锐的角落产生了倾向于阻挡相邻掺杂区之间的泄漏电流的电压势垒而提供了优异的隔离。LOCOS区通常存在倒圆了的角落，因而可以有一些泄漏电流。
图5-8是沿一共同平面的剖面图(未按比例绘制)，示出了用来在形成于晶片上的多个集成电路之一的衬底内形成浅沟槽隔离结构的现有技术各相继加工步骤。
图5中的半导体衬底30包含分隔开的各掺杂区。用其间的浅沟槽隔离结构将各掺杂区隔离开来，是可取的。降低应力用的二氧化硅层36(也称为衬垫氧化物层36)被淀积或生长在衬底30的上部表面37上。接着，氮化硅层38被淀积(典型地根据低压化学气相淀积工艺)在二氧化硅层36上。
根据已知的工艺，光抗蚀剂层40被淀积、曝光、以及显影，以便在其中形成窗口41。
通过窗口41，具有侧壁47的窗口46被形成在氮化硅层38和衬垫氧化物层36中。优选用氧或诸如C2F6和/或CHF3之类的含氟气体(含氟气体对硅衬底30有选择性)的等离子体腐蚀工艺，来形成窗口46。
光抗蚀剂层40被清除，且晶片被清洗。利用作为掩模的窗口46，在通常包含使用溴化氢和氯的等离子体腐蚀干法腐蚀的腐蚀步骤中，具有侧壁49的沟槽48(见图6)被形成在半导体衬底30中。
介质衬里50被形成或淀积在沟槽48中。
如图7所示，借助于在沟槽48中淀积介质材料，来形成STI结构55。此材料淀积包含第一步骤，其中，密度比较低的介质材料56A被淀积在沟槽48内，基本上邻接衬里膜50。在第二淀积(大块淀积)步骤中，足够的功率被馈送到淀积工作室来形成提高材料淀积速率(以及工艺产率)的高离子密度，以便在沟槽48中形成高密度的介质材料56B(例如不掺杂的硅酸盐玻璃)。典型地根据高密度等离子体不掺杂硅酸盐玻璃的淀积工艺(HDP USG)，来执行后一个淀积。在另一实施方案中，大气压化学气相淀积工艺(APCVD)可以被用来代替HDP USG工艺。为了淀积高密度HDP USG材料56B，在淀积工作室内产生了约为每立方厘米1011-1013离子的等离子体密度，在淀积步骤中介质材料也被淀积在氮化硅层38的上部表面59上。化学机械抛光(CMP)步骤从上部表面59清除介质材料，停止于氮化硅层38。由于介质材料(例如HDP USG)的CMP抛光速率大于氮化硅的CMP抛光速率，故STI结构55的上部表面60被凹陷到氮化硅层38的上部表面59以下。
为了完成STI结构55的制作，根据氢氟酸(HF)清洗工艺来清洗晶片，用诸如HF湿法腐蚀之类的已知工艺，氮化硅层38和衬垫氧化物层36被清除，且最后再次清洗晶片。图8示出了在完成这些加工步骤之后的包括侧壁62的STI结构55的结构元件。为方便起见，没有分别示出低密度介质材料56A和高密度介质材料56B。
在清除氮化硅层38和衬垫氧化物层36的腐蚀工艺中，空洞70(见图8)形成在低密度介质材料与高密度介质材料之间的界面处。
在栅多晶硅层的稍后淀积过程中，不希望有的多晶硅桁条(称为“缠绕”)可能形成在侧壁62周围和空洞70中。这些桁条可以产生损害STI隔离功能的短路或泄漏电流路径，使集成电路的性能降低，导致可靠性问题和器件失效。希望有一种防止在界面处形成空洞的工艺方案。
在减小空洞70的宽度和深度(因而形成多晶硅桁条的可能性)的努力方面，已知要缩短在用来清除氮化硅层38和衬垫氧化物层36的湿法腐蚀工艺之后的清洗步骤(典型是氢氟酸清洗)的持续时间。但也已经知道较短的清洗可能使氮化物残留物和沾污存留在衬底30上，有可能STI结构55和衬底30内引起不希望有的短路或泄漏电流。
发明内容
根据一个实施方案，本发明包含一种用来在集成电路中形成浅沟槽隔离结构的方法。此方法包含提供半导体层、在半导体层中形成窗口、在窗口中淀积介质材料、在介质材料上方淀积共形材料、以及清除共形材料，从而在清除共形材料的步骤之后，可以被形成在介质材料中的空洞至少部分地被共形材料填充。
根据本发明的另一实施方案，集成电路结构包含半导体层、形成在半导体层中的器件隔离结构，此器件隔离结构包含排列在半导体层中沟槽内的第一介质材料以及空洞内的第二介质材料，其中，空洞可以存在于邻近沟槽侧壁的第一介质材料中。
附图说明
结合附图阅读本发明的下列详细描述，能够更容易地理解本发明，其优点和用途更加显而易见，在这些附图中：
图1-4是衬底在根据本发明的技术来形成浅沟槽隔离结构的相继加工步骤中的剖面图。
图5-8是衬底在形成现有技术的浅沟槽隔离结构的相继加工步骤中的剖面图。
根据通常的做法，所述的各种器件特征不按比例绘制，而是被绘制成强调本发明有关的特定特征。在所有附图及文本中，相似的参考号表示相似的元件。
具体实施方式
在详细描述有关根据本发明的STI结构形成的具体方法和结构之前，应该理解本发明主要在于一种新颖的非显而易见的元件以及工艺步骤的组合。为了不使对本技术领域熟练人员来说显而易见的详细公开难于理解，某些常规的元件和步骤被较简单地提及，而附图和说明书更详细地描述了与理解本发明有关的其它元件和步骤。
下列描述不是为了限制本发明的结构或方法，而仅仅是用来提供示例性结构。这些实施方案是允许选择的而不是强制性的，是说明性的而不是详尽的。本发明包含用来制作STI结构的方法，此STI结构避免了与上述现有技术工艺相关的空洞70的不利影响。
图1示出了清除氮化硅层38之后的STI结构55。根据本发明的技术，衬垫氧化物层36保留在衬底30上。
根据本发明，共形氮化硅层80(厚度约为50-100nm)被淀积在衬垫氧化物层36上，并用氮化硅区域80A填充空洞70。见图2。根据一个实施方案，用产生共形材料层的LPCVD工艺来淀积氮化硅层80用来填充空洞70。其它产生共形介质材料层(例如氧氮化硅)的工艺可以被用来代替LPCVD工艺以填充空洞70。例如，恰当地控制的PECVD工艺可以被用来淀积氮化硅的共形层。(典型地根据化学气相淀积工艺淀积的)共形碳化硅层，也可以被用来填充空洞70。
用具有终点控制的常规满铺氮化物回腐蚀工艺，来腐蚀氮化硅层80，此回腐蚀工艺在达及沟槽中的衬垫氧化物层36和介质材料56时终止。见图2。如所示，氮化硅区域80A保留在空洞70中，至少部分地填充空洞70。
在一个实施方案中，氮化物腐蚀包含一种二步骤工艺。在第一步骤中，氧和含氟气体(例如C2F6或CF4)的混合物以分别约为5SCCM和100SCCM的流速被馈送到等离子体腐蚀工作室。工作室的压力约为100毫乇，馈送到工作室的功率约为450W。如本技术领域熟练人员所知，流速、压力、以及功率可以从给定的特定数值变化至少10％而不危及腐蚀结果。
接着，利用提供希望的选择性的聚合气体(例如大约10SCCM的CHF3)、氩(大约20SCCM)、以及含氟气体(大约10SCCM)的混合物，执行对下方半导体衬底30有选择性的过腐蚀工艺。工作室的压力约为100毫乇，馈送到工作室的功率约为300W。流速、压力、以及功率可以从给定的特定数值变化至少10％。本技术领域熟练人员理解的是，其它的腐蚀工艺能够被用来腐蚀氮化硅层80。用诸如HF湿法腐蚀之类的已知工艺来清除衬垫氧化物，并对晶片进行清洗(例如用RCA清洗工艺)。最终STI结构被示于图4中。
在其共形性质的条件下，氮化硅膜80不仅填充空洞70，而且在回腐蚀之后，氮化硅区域80B保留在STI结构84的侧壁62上，在随后的加工中保护侧壁62免于剥落或损伤。
已知宽的STI结构容易受到用来从上部表面59清除二氧化硅的CMP工艺过程中的凹陷的影响。一种夸大了的凹陷被示于图7中。共形氮化硅层80的剩余部分80C覆盖着凹陷的区域，从而提供了较平坦的STI上部表面，在后续各材料层的光刻和淀积过程中，这是有利的。见图4。
本发明的增强方法避免了导致STI结构中形成空洞以及可能引起形成有问题的较大空洞的随机工艺变化(诸如腐蚀速率)的常规制造工艺的影响。根据可重复且一致的工艺，本发明制造了没有空洞的STI结构。多晶硅桁条形成的可能性被显著地减小，器件的可靠性被显著地改善，器件的失效率因而被显著地降低。
一种结构和工艺已经被描述为可用来在半导体衬底中形成STI结构。已经示出并讨论了本发明的具体应用和示例性实施方案，提供了以各种方式和各种电路结构来实施本发明的基础。在本发明的范围内，各种变化是可能的。与一个或多个所述实施方案相关的特征和元件，不要被认为是所有实施方案的必须元件。本发明仅仅受下列权利要求限制。

Claims (10)

1.一种用来形成浅沟槽隔离结构的方法，包括：
在半导体层中形成窗口；
在所述窗口中和在所述半导体层上淀积介质材料；
清除一部分介质材料以形成隔离结构，所述隔离结构具有至少一个空洞，所述空洞位于所述半导体层和所述隔离结构之间；
淀积共形材料覆盖所述隔离结构和所述半导体层，其中所述至少一个空洞被所述共形材料填充；以及
从所述半导体层清除共形材料，并从所述隔离结构清除一部分共形材料，从而在所述清除共形材料的步骤之后，所述至少一个空洞保持被填充，并且所述共形材料的残留物保留在所述半导体层的上部表面上延伸的所述隔离结构的至少一侧上。
2.根据权利要求1的方法，其中，所述清除共形材料的步骤包括：
使用氮化物腐蚀和过腐蚀工艺来腐蚀共形材料，使得在所述清除共形材料的步骤之后，一部分共形材料保留在所述隔离材料上。
3.根据权利要求2的方法，其中，在窗口中淀积介质材料的步骤包括在窗口的侧壁附近淀积低密度介质材料，随后在窗口的剩余区域中淀积高密度介质材料，并且其中，空洞可能被形成在高密度介质材料与低密度介质材料的界面附近。
4.根据权利要求2的方法，其中，在窗口中淀积介质材料的步骤包括：
淀积邻近窗口的侧壁的二氧化硅衬里；
淀积邻近衬里的低密度不掺杂硅酸盐玻璃材料；以及
在窗口的剩余区域内，淀积高密度不掺杂硅酸盐玻璃材料，其中，空洞可能被形成在低密度不掺杂硅酸盐玻璃材料与高密度不掺杂硅酸盐玻璃材料的界面附近。
5.根据权利要求2的方法，其中，淀积共形材料的步骤还包括在半导体层的上部表面上延伸的介质材料的侧壁上淀积共形材料。
6.根据权利要求2的方法，其中，淀积共形材料的步骤包括淀积氮化硅、氧氮化硅、或碳化硅。
7.根据权利要求2的方法，其中，形成窗口的步骤包括：
形成第一材料层覆盖所述半导体层；
形成穿过第一材料层的窗口；以及
清除通过所述窗口而暴露的半导体层材料以在所述半导体层中形成窗口。
8.一种集成电路结构，包括：
半导体层；
形成在所述半导体层中的器件隔离结构，所述器件隔离结构包括设置在所述半导体层中的沟槽内的第一介质材料，其中，在邻近所述沟槽的侧壁的第一介质材料中可能存在空洞；以及
空洞内的第二介质材料和位于在所述半导体层上延伸的器件隔离结构的一侧上的第二介质材料的残留物。
9.根据权利要求8的集成电路结构，其中，第二电介质材料包括氮化硅、氧氮化硅、或碳化硅。
10.根据权利要求8的集成电路结构，其中，第一介质材料的上部区域包括上部表面，且其中，第二介质材料被设置在所述上部表面上。
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