CN100498692C - 用于配置自适应集成电路的装置、系统及方法 - Google Patents
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Abstract
本发明涉及用于自适应或可重配置计算的集成电路的新范畴(category)的配置。优选的自适应计算引擎(ACE)IC包括多个与互连网络连接的异类计算元件。多个异类计算元件包括相应的具有固定且不同的体系结构的计算元件,如适合于不同功能如存储、加法、乘法、复数乘法、减法、配置、重配置、控制、输入、输出、及现场可编程性等的固定体系结构。响应于配置信息,互连网络用于配置和重配置多个异类计算元件为多个工作状态的第一工作状态,响应于第二子集配置信息,互连网络还用于重配置多个异类计算元件为多个不同的工作状态,包括线性算法运算、非线性算法运算、有限状态机运算、控制器运算、存储运算、及位级处理。优选系统实施例包括一同提供一工作状态所需要的配置信息相连联系的ACE集成电路。优选方法包括各种为不同工作状态产生和提供配置信息的方法。
Description
技术领域
本发明总体上涉及集成电路和集成电路系统,特别是涉及用于具有固定、专用计算元件的自适应集成电路的配置的装置、系统及方法,以用于自适应集成电路的功能性的提供或产生。
相关申请的交叉索引
本申请与PaulL.Master等人在2001年3月22日申请的题为“使用具有固定、专用计算元件的不同自适应计算单元的异类和可重配置矩阵(Heterogeneous And Reconfigurable Matrices)的自适应集成电路”的美国专利申请号为09/815,122的申请相关,其已转让给快闪银科技公司并在此组合进来以供参考,且要求该申请所有公开的主题的优先权(“相关申请”)。
背景技术
相关申请公开了一种新形式的或新类型的集成电路,其可有效地结合各种处理器的优点并使这些优点最大化,专用集成电路(“ASIC”),现场可编程门阵列(“FPGA”),同时使潜在缺点最小化。相关申请阐明了一种新形式的或新类型的集成电路(“IC”),称为自适应计算引擎(“ACE”),其提供处理器的编程灵活性、FPGA的后安装的灵活性、及ASIC的高速和高利用因数。该ACE集成电路易于重新配置、能够具有对应的多工作状态、且在增加性能的同时还使功耗最小,其特别适合于低功率应用,如用于手持及其他用电池供电的器件。
然而,该ACE集成电路没有更多的东西,实质上是一空或“空白”器件。更具体地,提前或实时(或潜在地以较慢的速率)要求配置信息以产生配置及重配置,其为ACE电路提供并创建一种或多种工作状态,如无线通信、无线电接收、个人数字助理(“PDA”)、MP3音乐播放、或任何其他想要的功能。
不同的考虑和需要还由于将为一种或多种工作状态而被配置和重配置的ACE体系结构的能力。例如,在一器件中的特定ACE IC的配置(和/或重配置)之前,该ACE的能力应当被确定,以避免可改变或损害器件的先前存在的配置或其他功能性的可能配置的下载或接收。
配置和重配置的安全性也是极为重要的。假定该配置能够改变ACE体系结构的功能,则应实施授权及安全措施以避免潜在的破坏或其他非法的配置,如病毒、蠕虫及其他有害病毒。授权和安全措施对于知识产权保护同样是重要的,如有版权的资料,及其他可能是秘密级或内部级的信息。不同形式的监控、跟踪和其他记录保存还可适于确定和考虑不同配置可能性。
因此,需要保持一用于为自适应集成电路提供配置信息的装置、方法及系统,该装置、方法和系统还用于ACE电路和其他ACE器件的一种或多种工作状态或其他功能性的提供或创建。这样的方法和系统应能够确定ACE能力、应提供安全的和经授权的配置、并应提供对配置及内容使用的适当监控。
发明内容
本发明的自适应计算引擎(“ACE”)电路,用于自适应和重配置运算,包括多个不同的、连接到互连网络的异类计算元件(而不是同样的、同类重复及排列的FPGA单元)。多个异类计算元件包括相应的具有固定及不同体系结构的计算元件,如用于不同功能的固定体系结构,这些功能如存储、加法、乘法、复数乘法、减法、配置、重配置、控制、输入、输出、路由选择、及现场可编程性。响应于配置信息,互连网络提前、实时或潜在地较慢实施对多个异类计算元件的配置及重配置,以得到多个不同的工作状态,包括线性算法运算、非线性算法运算、有限状态机运算、存储运算、及位级处理(bit-levelmanipulation)。反过来,该异类计算元件的配置和重配置,形成不同的计算单元和自适应矩阵,为多种任务的执行而产生所选择的、ACE集成电路的较高等级的工作状态。
本发明的优选系统实施例包括与一组或多组配置信息结合的ACE集成电路。另外,较高等级系统实施例同样被阐明,包括有线和无线器件、消费和汽车电子、网络基础设施装置、等等。该配置信息为ACE提供所选择的工作状态,在没有该配置信息时,ACE没有任何功能。
用于为ACE集成电路产生和提供配置信息的多种装置、方法和系统同样也被阐明。另外,本发明的系统和方法能够确定ACE重配置容量或能力,提供安全的和经授权的配置,并提供配置和内容使用的适当监控。
本发明的大量其他优点和特征从下面的详细描述及其中的实施例、从权利要求及附图均可显而易见地得出。
附图简要说明
图1为根据本发明的多个系统实施例的简图。
图2为根据本发明的一集成系统实施例的简图。
图3为根据本发明的优选自适应计算引擎(ACE)实施例的简图。
图4为根据本发明的可重配置矩阵、多个计算单元、及多个计算元件的简图。
图5为根据本发明的可重配置矩阵的计算单元的更详细的简图。
图6为根据本发明的一具有多个不同的、固定计算元件的优选多功能自适应计算单元的详细简图。
图7为根据本发明的一具有多个固定计算元件的优选自适应逻辑处理器计算单元的详细简图。
图8为根据本发明的一具有固定计算元件的自适应逻辑处理器计算单元的优选核心单元的详细简图。
图9为根据本发明的一自适应逻辑处理器计算单元的核心单元的一优选固定计算元件的详细简图。
图10为根据本发明的方法实施例的流程图。
具体实施方式
虽然本发明可被具体化为许多不同的形式,但附图所示及在此将详细描述的只是其中的特殊的实施方式,应理解的是,该公开应被认为是本发明原理的一个范例且并不意欲将本发明限定为所举例说明的特殊实施方式。
如上面所指出的,需要存在一种为自适应集成电路提供配置信息的装置、方法及系统,以为自适应计算引擎(ACE)及其他组合有ACE技术的装置提供一种或多种工作状态。这样的装置、方法及系统根据本发明而提供,其将配置信息与ACE电路(ACE IC)结合在一起,从而提供一种或多种所选择的工作状态,如无线通信、无线电接收、个人数字助理(“PDA”)、MP3音乐播放、或任何其他想要的功能。此外,本发明装置、系统及方法能够确定ACE重配置容量,提供安全的和经授权的配置,并对配置和内容使用提供适当的监控。
本发明系统和方法使用了称为ACE(自适应计算引擎)的新形式的集成电路。ACE体系结构使用多个固定且不同的计算元件,如(但不限于)相关器、乘法器、复数乘法器、加法器、解调器、互连元件、路由选择元件、并合器、有限状态机元件、精简指令组(RISC)处理元件、位处理元件、输入/输出(I/O)及其他接口元件、形成这些单元的较低级的“构件块”,其可响应于配置信息而被配置和重配置,以在任何给定或选择的时间形成可能需要的功能块(计算单元及矩阵)以执行较高级的功能,从而最后执行所选择的工作状态,如执行无线通信功能。本发明方法和系统还使功率消耗最少且特别适于低功率应用,如用于手持及其他电池供电的装置。
图1为阐明根据本发明的多个系统实施例的简图。参考图1,如上面所指出的(及下面更详细论述的),本发明的优选系统包括与配置信息联系或结合的ACE100,其可被实施在多个实施例中,包括,例如无线器件30和32内、有线器件35内、计算机55内、消费电子、汽车电子37、及网络基础设施装备如服务器54、路由器53、局域网(LAN)41、无线LAN43、广域网(WAN)42、附属网络实体50、交换系统52和56、无线基站25、及任何其他电子器件。
如上所述及如在此所使用的,术语“配置信息”一般应被理解为具有并包括其语言上的、复数涵义,即配置信息是多个信息位、信息群或组,也就是说,“多个”配置信息。例如,“配置信息”可被看作一组包含多个子集的配置信息,这样的子集为第一配置信息、第二配置信息、第三配置信息,依此类推,到第n配置信息。尽管一子集配置信息可以是单一的(包含在子集中的一位信息),每一这样的子集配置信息同样可以是复数的,通常包括可被一单一位如8、16、32、或64信息位编码的多个信息。
配置信息还可在任何给定时间存在于各种形式中,并可具有一存储的(或固定的)特性,或可具有一瞬时的或暂时的特性。例如,如图1所示,配置信息可被保存为闪速存储器10(对于器件35)、计算机、或计算机55B的可读介质20(如CD-ROM、其他光学驱动器、计算机存储器、硬盘驱动器或软盘)中的二进位(位)文件。如下面所详述的,这样的配置信息还可与数据互相交叉、缠结或结合,从而形成在此所定义的“silverware”或“silverware”模块,并保存为silverware存储介质15中的二进位(位)文件。配置信息还可短暂地出现,例如,当在一空中接口上从基站25A无线下载到无线装置32(如移动站或其他移动电话)时,或当从服务器54有线下载到计算机(PC)55时。
更详细地参考图1,多个网络被示出,包括局域网(“LAN”)41、无线LAN43、广域网(“WAN”)42、及更一般地网络40如公共交换电话网络(“PSTN”)或因特网。连接到各个网络的是路由器53A和53B、服务器54A和54B、有线交换中心56、移动交换中心(“MSC”)52、及进一步连接或耦合到无线基站(或其他无线收发器)25A和25B、有线器件35、计算机55A和55B、及附属网络实体50。如现有技术所公知的,这些器件可经中继、光学及其他信号线而相互连接在一起,且可连接到更广的网络(如PSTN或因特网),具有到其他位置的多通信连接,如提供到人造卫星的链路(未独立示出)及提供其他无线链路(空中接口)。路由器53B、服务器54B、基站25B及计算机55B均分别被指定(用“B”)以阐明在这样的基础设施装备内可能包含ACE100(及本发明系统),及除了包含在消费、汽车及移动电子内外,还在LAN41、WAN42、无线LAN43、附属网络实体50内包含。同样,由于规定的及其他历史或遗留的原因,在有线和移动交换中心56和52通常在物理上被分隔开的同时,这些交换中心也可被结合在一个或多个同时具有有线及无线功能的交换中心里。
这些不同的服务器、交换中心、路由器及其他实体还可通过网络40连接到一个或多个称为附属网络实体的智能网络装置,如附属网络实体50,其可以是另外类型的服务器、数据库、服务控制点(“SCP”)、服务电路节点(“SCN”)(还称为服务节点(“SN”))、智能外围设备(“IP”)、网关、或另外的智能网络装置。一个或多个附属网络实体50更适宜连接或连结到网络40,直接或间接连接到有线交换中心56、MSC52、LAN41、WAN42、无线LAN43、路由器53和服务器54。在优选实施例中,一附属网络节点50为特定应用(“应用节点”)51提供一节点或平台,如应用节点51A、51B到51N所示,以履行各种功能如提供配置信息下载、鉴别、安全性、授权及相容性评价。除了包含在附属网络实体50内以外,这些不同的应用节点51还可被分布在其他各种装置之间或包括于其内,如在一个或多个服务器54内。例如,一个服务器54可被使用以提供配置信息,及一附属网络实体50被使用以用于鉴别和安全,跟踪和说明在另一服务器54或计算机55处的事件。
为解释但不是限制的目的,如图1所示,本发明的各种系统包括:系统11(有线器件35的ACE100,配置信息在FLASH10中);系统16(无线器件30的ACE100,配置信息在silverware存储介质15中);系统31(无线器件32的ACE100,配置信息被保存在存储器中(在图2中单独示出),如RAM或矩阵互连网络(“MIN”),如下所述);系统21(计算机55B的ACE100,配置信息保存在计算机可读介质20中);系统22(服务器54B的ACE100,配置信息保存在存储器中(在图2中单独示出));及系统23(路由器53B的ACE100,配置信息被保存在存储器中(在图2中单独示出))。很显然,除了那些所示出的器件(如LAN41、WAN42、无线LAN43及附属网络实体50)以外,本发明系统可被具体在任何器件或其他物品内,其同时包括ACE100及提供相应的工作状态的配置信息,本发明系统也可与特定装置或其他实施方式共同扩张。
其他网络或分布级系统同样被包括在本发明范围内。示例性的网络系统可包括一个或多个应用节点51,在一附属网络实体50或其他服务器54中,其提供为ACE100所用的配置信息或silverware模块(与数据联系的配置信息)。在优选实施例中,响应于来自或代表ACE100的请求,这样的网络或分布级系统可提供下述之一:一组或多组配置信息;被修改以与配置信息一起使用的内容或其他数据;将配置信息与相应的数据或其他内容结合的silverware模块;为独特器件而被剪裁或压制水印配置信息,和/或配置信息或silverware模块的加密。
分布系统同样在本发明范围内,因为配置信息不需要局限于任何给定的ACE100器件。例如,配置信息或silverware可跨网络40被保存,如在应用节点51、附属网络实体50、其他服务器54、及图1中示出的其他元件之间。对于这样的分布系统,ACE100可仅被配置,如通过操作系统(“OS”),以获得配置信息,如通过这些网络器件之一。
图2为表示根据本发明的集成系统实施例60的简图。系统60最好被实施为一单集成电路(芯片上的系统或“SOC”)。系统60包括一ACE100,并还可包括一存储器61、一接口62及一个或多个其他处理元件65。这样的系统60,例如,可被包含于图1的路由器53和服务器54内,或可被包含于其他嵌入系统内,如移动站或器件30和32、有线器件35,等等。当系统60仅由一ACE100组成时,如下面所详述的,ACE100将通常被配置为包括处理、接口及其他I/O功能、及或通过存储计算元件或直接在矩阵互连网络(MIN)内配置的存储。如图2所示,具有光学处理元件65、接口62及存储器61的系统60将通常被实施以向现有的或其他遗留系统和器件提供向后相容性(retrocompatibility)。
接口62被使用以适当连接到相关信道、网络或总线;例如,接口62可为有线接口提供阻抗匹配、驱动器及其他功能,可为无线接口提供解调及模拟到数字的转换,为存储器61及其他器件提供物理接口。总之,接口62被使用以接收和传送数据,根据所选择的实施方式,如声音信息、配置信息、silverware模块、控制消息、鉴别数据及其他有关信息。ACE100还可被配置以提供接口62的功能,包括内部IC I/O及外部(离芯)I/O,如用于PCT总线控制。存储器61可以是集成电路或集成电路的一部分,如各种形式的RAM、DRAM、SRAM、MRAM、FeRAM、ROM、EPROM、E2PROM、flash,等等。对于非IC(或非SOC)实施例,存储器61还可以是磁(硬或软)驱、光存储器件、或任何其他类型的数据存储装置,且如上所述,可跨多个器件分布。此外,取决于所选择的实施方式及如下面所详述的,存储器61还可通过存储计算元件包含于ACE100内或包含于矩阵互连网络(MIN)内。一个或多个处理元件65可任意包含于系统60内,如微处理器或数字信号处理器(“DSP”),以提供任何额外的处理能力,如精简指令组(“RISC”)处理,或者其可被包含为ACE100内的计算元件。
图1和图2所示的各种系统的工作将在下面进行详述,下面对ACE100体系结构的说明将参考图3-9,同样也参考图10。
图3为根据本发明的一优选ACE装置100实施例的简图。ACE100最好被具体实施为一集成电路或具有其他、额外构件的集成电路的一部分。(ACE100在相关申请中也进行了详细描述。)在优选实施例中,如下面所详述的,ACE100包括一个或多个可重配置矩阵(或节点)150,如所示的矩阵150A-150N,及一矩阵互连网络(MIN)110。同样在优选实施例中,如下面所详述的,矩阵150的一个或多个,如矩阵150A和150B,被配置为控制器120的功能,而其他矩阵,如矩阵150C和150D,被配置为存储器140的功能。虽然如图所示的分开的矩阵150A-150D,但应注意到,这些控制和存储功能可以且最好跨多个具有额外功能的矩阵150分布,以避免任何处理或存储“瓶颈”或其他限制。例如,这样的分布式的功能在图4中有所图示。各个矩阵150和矩阵互连网络110还可实施在一起而作为分形子单元,其可从几个节点换算为数千个节点。
明显地区别于现有技术,ACE100不使用用于在可重配置矩阵150、控制器120、及存储器140之间发信号和其他传送或用于其他输入/输出(“I/O”)功能的传统的(且通常分开的)数据、DMA、随机存取、配置及指令总线。而是,数据、控制及配置信息均使用矩阵互连网络110而在这些矩阵150元件之间传送,其可被配置及重配置,以在可重配置矩阵150之间提供任何给定连接,包括那些被配置为控制器120和存储器140的矩阵150,如下所详述的那样。
同样应被注意的是,一旦被配置,MIN110同样且有效地作为一存储器,直接提供对特定功能的互连,直到其被重配置为止。此外,这样的配置和重配置可在特定功能或操作的使用之前出现,和/或实时出现或以较慢的速率出现,即在特定功能或操作的使用之前、期间或同时出现。而且,这样的配置和重配置可以在不破坏功能或操作的情况下出现在分布型式中,部分计算元件在一位置被配置,而其他计算元件(先前已被配置)正同时执行它们被指定的功能。ACE100的这种配置灵活性与FPGA重配置形成强烈对比,二者通常都出现得相当迟缓,不是实时的或与使用同时发生,且其必须在任何操作或其它使用之前被整个完成。
被配置而用作存储器140的矩阵150可以任何想要的或首选的方式实施,使用固定存储元件的计算元件(如下所述),且其可包括在ACE100内或结合在另一IC或IC的一部分内(如存储器61)。在优选实施例中,存储器140包括在ACE100内,且最好由低功耗随机存取存储器(RAM)这样的计算元件组成,其也可以由任何其它形式的存储器组成,如flash、DRAM、SRAM、MRAM、FeRAM、ROM、EPROM或E2PROM。如上所述,该存储功能还可跨多个矩阵150分布,且可在任何给定时间作为特定MIN110配置而暂时嵌入。此外,在优选实施例中,存储器140最好包括直接内存存取(DMA)引擎,在图中未单独示出。
控制器120最好使用被配置为自适应有限状态机、精简指令组(“RISC”)处理器、控制器或能够执行如下所述的两种类型的功能的其他装置或IC的矩阵150A和150B来实施。(或者,这些功能可使用传统RISC或其他处理器来实施,如图2的处理元件65。)该控制功能还可贯穿在执行其他另外功能的一个或多个矩阵150而分布。此外,该控制功能可被包括在配置信息内并直接体现为配置信息,没有分离的硬件控制器功能。称为“内核”控制的第一控制功能被图示为矩阵150A的内核控制器(“KARC”),称为“矩阵”控制的第二控制功能被图示为矩阵150B的矩阵控制器(“MARC”)。控制器120的内核和矩阵控制功能在下面将参考不同矩阵150的可配置性和可重配置性、结合数据及在此可替交地称为“silverware”(“Agware”)或“silverware”模块的配置(和其它控制)信息的优选形式进行详述。
图3的矩阵互连网络110及在图4和5中分别示出的其子集互连网络(布尔逻辑互连网络210、数据互连网络240、及互连220),其全体并通常在此被称为“互连”、“互连网络”或MIN,可按现有技术所公知的方式实施,如使用现场可编程门阵列(“FPGA”)互连网络或交换结构,尽管有相当多的各种各样的方式。(如在此所使用的,“现场可编程”指制造后添加或改变实际IC功能的能力,与现有IC结构或功能的编程相反(如在微处理器或DSP中))。在优选实施例中,各种互连网络被实施为如下各专利所描述的形式,例如,美国专利号5,218,240、5,336,950、5,245,227及5,144,166,同样还实施为如下所述及参考图7、8和9所阐述的。这些不同的互连网络在控制器120、存储器140、多个矩阵150、及如下所述的计算单元200及计算元件250之间提供可选择的(或可交换的)连接,其响应于并在在此称为“配置信息”的配置信令的控制之下,而为在此称为配置和重配置提供物理基础。此外,多个互连网络110、210、240和220在控制器120、存储器140、多个矩阵150、和计算单元200和计算元件250之间提供可选择的、可路由的或可交换的数据、输入、输出、控制和配置路径,代替任何形式的传统的或分开的输入/输出总线、数据总线、DMA、RAM、配置及指令总线。
然而,应当指出的是,在多个互连网络110、210、240和220内的任何给定交换和选择操作可按现有技术公知的形式实施的同时,如下所详述的,根据本发明的多个互连网络110、210、240和220的设计和布局是新的和新颖的。例如,提供可变级别的互连以对应于可变级别的矩阵150、计算单元200、及计算元件250,如下所述。在矩阵150级,与现有技术FPGA互连相比,矩阵互连网络110被相当多地限制并较少“丰富(rich)”,在给定区域具有更小的连接能力,以减少电容和增加运行速度。然而,在特定矩阵150或计算单元200内,互连网络210、220和240可以相当密集,以在狭小的或封闭的基准位置提供更大的适应和重配置能力。
多个矩阵或节点150是可重配置的和异类的,即,总体上依赖于所想要的配置:可重配置矩阵150A通常不同于可重配置矩阵150B-150N;可重配置矩阵150B通常不同于可重配置矩阵150A和150C-150N;可重配置矩阵150C通常不同于可重配置矩阵150A、150B及150D-150N,依次类推。多个可重配置矩阵150的每一个通常包含自适应及可重配置计算单元200的不同的或变化的混合;而计算单元200通常包含固定的、专用的计算元件250的不同的或变化的混合,如下面参考图4和5所详述的,其可通过多个互连网络、以多种方式自适应地连接、配置和重配置以执行不同的功能。除了各种各样的内在配置和重配置外,多个矩阵150可通过矩阵互连网络110、在更高级别被连接、配置和重配置,如下所详述的。
几个不同、有见识、且新颖的概念被组合于本发明的ACE100体系结构内,并为ACE100的实时操作及其内在优点提供有用的说明基础。
本发明的第一新概念涉及专用或固定硬件单元(计算元件250)的自适应及可重配置使用,及用于加速的特定功能的选择,这将被包括在矩阵150的计算单元200(图4)内的这些专用或固定硬件单元(计算元件250)内,如多个乘法器、复数乘法器、及加法器,其每一个均设计用于最佳执行对应的乘法、复数乘法及加法功能。在优选实施例中,假使ACE100将为了低功耗而被最优化,则用于加速的功能基于功耗而选择。例如,对于给定应用如移动通信,相应的C(或C++)或其他编码可为了功耗而被分析。这样的经验分析可揭示,例如,这些编码的小部分,如10%,在执行时实际消耗了90%的运行功率。根据本发明,在这样的功率利用基础上,该小部分编码为了加速而被选择在一定类型的可重配置矩阵150内,例如,使得剩余的编码适于在配置为控制器120的矩阵150内运行。另外的编码同样可为了加速而被选择,从而导致ACE100的功耗的最优化,一直到由设计或操作复杂性引起的任何潜在平衡(potential trade-off)。此外,如参考图4所述,其他功能,如控制编码,可在配置为有限状态机的矩阵150内加速。通过变化级互连,相应的算法接着在任何给定时间、通过固定计算元件250的配置和重配置而被实施,即,在为了效率而已经被优化和配置的硬件内实施,即,一“机器”被实时配置,其被优化以执行特定算法。
本发明的下一个且或许是最重要的概念,其明显区别于现有技术的概念和规则,是被使用来实施前面提及的各种所选择的算法的可重配置“异质(heterogeneity)”概念。如在相关申请中所指出的,现有技术的可重配置性已完全依赖于同类FPGA,其中同样的逻辑门块被重复为一丰富、可编程互连内的一阵列,该互连随后被配置以在同样的门之间提供连接从而实施特定功能,虽然无效率地且经常有路由选择及组合的问题。完全相对地,根据本发明,在计算单元200内,不同的计算元件250被直接实施为相应不同的固定(或专用)专用硬件,如专用乘法器、复数乘法器及加法器。使用互连210和220,这些不同的、异类计算元件250接下来可自适应地配置,提前、实时和较慢的速度,以执行所选择的算法,如经常在移动通信中使用的离散余弦变换的执行。因而,根据本发明,不同的(“异类的”)计算元件250在任何给定时间被配置和重配置,以最佳执行给定算法或其他功能。此外,对于重复的功能,计算元件的给定例示或配置还可在该重复计算的整个过程中适当保持,即,不被改变。
ACE100体系结构的暂时特性同样应被注意。在任何给定时间的瞬间,使用不同级别的互连110、210、240和220,一特定的配置可能存在于已经被优化以执行给定功能或实施特定算法的ACE100内,如为移动站30或32中的CDMA工作状态实施导频信号搜索。在另一时间瞬间,配置可能被改变,以使其他计算元件250互连或不同地连接同样的计算元件250,用于另外的功能或算法如为CDMA工作状态的多路接收的执行。该暂时特性引起两个重要的特征。第一,由于算法可能会随时间的推移而改变以实施新技术标准,ACE100可同时发展且被重配置以实施新算法。第二,因为计算元件在一瞬间被互连,由于一给定算法的例示,及随后在另一瞬间被重配置而用于另外的、不同的算法的执行,门(或晶体管)利用被最大化,从而提供比最有效的ASIC更好的性能,相对于它们的活动因素而言。该暂时可重配置性还阐明了活动因素。该暂时可重配置性同样阐明了MIN110内在的存储功能,如上所述。
用于多个不同算法的执行的计算元件250的暂时可重配置性还一方面阐明了在此使用的配置和重配置之间的概念上的区别,另一方面阐明了编程或可再编程的区别。典型的可编程使用先前存在的功能组,其可随时间以多种顺序被调用以实施特定算法。相反,如在此使用的,可配置和可重配置包括另外的添加或创建新功能的能力,该新功能在先前是不可用的或不存在的。
接下来,本发明还使用数据和配置(或其他控制)信息的紧密结合(或互相交叉),在一个有效连续的信息流内。该数据和配置信息的结合或混合,称为“silverware”或“silverware”模块,是另一、第二相关专利申请的主题。然而,对于本发明的目的,可足以注意到的是,数据和配置信息的这种结合为一个信息(或比特)流,其可以是连续的或分成多信息包,有助于使ACE100能够实时可重配置,并不需要(经常是未被使用)现有技术的硬件互连的多重覆盖网络。例如,作为一模拟,计算元件在特定第一时间段的特定第一配置,由于硬件在第一时间段期间或之后执行相应的算法,可被看作或概念化为“调用”软件中一子例程的硬件模拟,所述软件可执行同样的算法。因而,一旦计算元件的配置已经发生(即,在适当的位置),由于受(第一子集)配置信息指引,在算法中可使用的数据立即可用作silverware模块的一部分。同样的计算元件接着可在第二时间段被重配置,由于第二配置信息(即第二子集配置信息)指引,对于第二不同的算法的执行,同样立即使用可用的数据。数据的直接性,对于使用在已配置的计算元件中,提供了对多个及分开的软件步骤的一个或两个时钟周期硬件模拟,所述软件步骤确定一存储地址并从该地址的寄存器取回所存储的数据。其具有另外的附加效率结果,因为配置的计算元件可能在相对少的时间周期内执行一算法,该算法如果被调用为传统微处理器或数字信号处理器(“DSP”)中的子例程,其可能要求更多的执行时间周期。
作为数据和配置信息的混合,连同多个形成自适应、不同及异类计算单元200和矩阵150的异类且固定的计算元件250的可重配置性,silverware模块的使用使ACE100体系结构能够具有多个不同的工作状态。例如,当被包含于手持设备内时,给定一相应的silverware模块,ACE100可具有多个不同的工作状态,如蜂窝或其他移动电话、音乐播放器、寻呼机、个人数字助理、及其他新的或现有的功能。此外,这些工作状态可基于设备的物理位置而改变。例如,根据本发明,当使用第一组配置信息而配置为第一工作状态,从而作为在美国使用的CDMA移动电话,ACE100可使用第二组配置信息被重配置为在欧洲使用的GSM移动电话工作状态。
再次参考图3,控制器120(最好是矩阵(KARC)150A和矩阵(MARC)150B,配置为有限状态机)的功能可参考silverware模块而得以阐释,即,数据和配置信息在单一信息流内的紧密结合,参考图4中示出的多个潜在工作状态、可重配置矩阵150、及可重配置计算单元200和计算元件250。如上所述,通过silverware模块,ACE100可被配置或重配置以执行新的或附加的功能,如升级到新技术标准或整个新功能的增加,如向移动通信装置增加音乐功能。这样的silverware模块可保存在存储器140的矩阵150中,或者可通过矩阵互连网络110从外部的(有线或无线)源输入。在优选实施例中,为安全目的,多个矩阵150之一被配置来解密该模块并验证其有效性。接下来,在现有的ACE100源的任何配置或重配置之前,控制器120通过矩阵(KARC)150A检验和验证该配置或重配置是否会出现对任何先前已有的功能的不利影响,如音乐功能的增加是否会对先前已有的移动通信功能产生不利影响。在优选实施例中,对该配置或重配置的系统要求包括在silverware模块或配置信息内,以供矩阵(KARC)150A在执行该评估功能时使用。如果配置或重配置不会出现那样的不利影响,silverware模块被允许装载进矩阵150(存储器140的),且矩阵(KARC)150A在存储器140的矩阵150C和150D内安装DMA引擎(或传统存储器的其他独立DMA引擎)。如果配置或重配置会产生不利影响,矩阵(KARC)150A不允许新模块被组合在ACE100内。
继续参考图3,矩阵(MARC)150B管理矩阵150源的调度、计时、及任何相应数据的时间选择,以使不同计算元件250的任何配置或重配置于任何相应的输入数据和输出数据同步。在优选实施例中,时间选择和其他计时信息也被包括在silverware模块内,更通常的是包括在配置信息内,以允许矩阵(MARC)150B通过不同的互连网络及时指引多个矩阵150的重配置,重配置最好刚好发生在相应的数据已出现在多个被重配置的计算单元200的任何输入之前。此外,矩阵(MARC)150B同样可执行任何尚未在多个矩阵150的任何一个内加速的剩余处理。因而,矩阵(MARC)150B可被看作一控制单元,其“调用”矩阵150、计算单元200、及计算元件250的配置和重配置,实时地,与任何将被这些不同的可重配置硬件单元使用的相应数据同步,且其执行任何剩余的或其他控制处理。其他矩阵150也可包括该控制功能,且任何给定矩阵150能够调用和控制其他矩阵150的配置和重配置。
图4为具有多个计算单元200(图示为计算单元200A-200N)及多个计算元件250(图示为计算元件250A-250Z)的可重配置矩阵150的更详细图解的简图,并提供优选类型的计算元件250的附加图解。如图4所示,任何矩阵150包括一矩阵控制器230、多个计算单元200,及作为矩阵互连网络110、数据互连网络240及布尔逻辑互连网络210的逻辑或概念上的子集或部分。如前所述,在优选实施例中,由于ACE100体系结构内的渐增的“深度(depth)”,互连网络变得愈加丰富,以用于更高级别的自适应性和重配置。同样如前所述,布尔逻辑互连网络210在多个计算单元200之间提供重配置和数据互连能力,且最好是较小的(即,只有几位宽),同时数据互连网络240为多个计算单元200之间的数据输入和输出提供重配置和数据互连能力,且最好是相当大的(即,许多位宽)。然而,应当注意的是,在概念上分为重配置和数据能力的同时,矩阵互连网络110的任何给定物理部分在任何给定时间可运行为布尔逻辑互连网络210、数据互连网络240、最低级互连220(在多个计算元件250之间)、或其他输入、输出或连接功能。
继续参考图4,包括在计算单元200内的是多个计算元件250,图示为计算元件250A-250Z(个别及全体均称为计算元件250),及附加的互连220。互连220在多个计算元件250之间提供可重配置互连能力及输入/输出路径。如上所述,多个计算元件250的每一个均由设计来执行给定任务或任务范围的专用硬件组成,其导致多个不同的固定计算元件250。使用互连220,固定计算元件250可被重配置地连接在一起而成为自适应的及各式各样的计算单元200,其也可被进一步重配置和互连,以在任何给定时间使用互连220、布尔逻辑网络210和矩阵互连网络100执行一算法或其他功能。
在优选实施例中,多个计算元件250被设计并集中在一起而成为多个自适应并可重配置的计算单元200(例如,如图5-9中所示)。除了被设计来执行特定算法或功能如乘法、关联或加法的计算元件250以外,其他类型的计算元件250也可被使用在优选实施例中。如图4所示,计算元件250A和250B实施存储,以为任何给定计算或处理功能提供本地存储元件(与更多的“远程”存储器140比较)。此外,计算元件250I、250J、250K和250L被配置来实施有限状态机(例如,使用图7、8和9中所示的计算元件),以提供本地处理能力(与更多的“远程”矩阵(MARC)150B比较),特别是适于复杂控制处理的能力。
具有可利用的各种类型的不同计算元件250,根据所想要的ACE100的功能,计算单元200可被松散分类。第一类的计算单元200包括执行线性计算的计算元件250,如乘法、加法、有限脉冲响应过滤,等等(例如,如下参考图6所示)。第二类的计算单元200包括执行非线性计算的计算元件250,如离散余弦变换、三角计算、及复数乘法。第三类型的计算单元200实施一有限状态机,例如图4所示的及下面参考图7-9详细示出的计算单元200C,对复杂的控制序列、动态调度、及输入/输出管理特别有用,第四类型可实施存储及存储管理,如图4所示的计算单元200A。最后,第五类型的计算单元200可被包括以执行位级处理,如用于加密、解密、通道编码、Viterbi解码、及信息包和协议处理(如因特网协议处理)。
在优选实施例中,除了从其他矩阵或节点150控制以外,矩阵控制器230也可被包括或分布在任何给定矩阵150内,同样提供任何重配置进程及任何相应的数据处理的参考及控制的更大局部性。例如,一旦计算元件250的重配置已发生在任何给定计算单元200内,对于某一时间段如对给定应用的连续重复数据处理,矩阵控制器230可指引特定例示(或配置)保持未动过的。
图5为根据本发明的可重配置矩阵150的示例性的或典型的计算单元200的详细简图。如图5所示,计算单元200通常包括多个不同的、异类的且固定的计算元件250,如多个存储计算元件250A和250B,并形成一计算单元(“CU”)内核260,多个算法或有限状态机计算元件250C-250K。如上所讨论的,多个不同计算元件250的每一计算元件250是固定的或专用的电路,被设计且具有相应的逻辑门布局以执行特殊的功能或算法,如加法或乘法。此外,不同的存储计算元件250A和250B可被实施为具有不同位深度,如RAM(具有很大的深度),或作为一寄存器,具有1或2位的深度。
分别形成概念上的数据和布尔逻辑互连网络240和210,示例性的计算单元200也包括多个输入多路复用器280、多根输入线281(并用于CU内核260的输出(图示为线270))、多个输出多路分配器285和290、及多根输出线291。通过输入多路复用器280,适当的输入线281可被选择用于数据变换中和配置及互连进程中的输入使用,通过输出多路分配器285和290,一个或多个输出可置于所选择的输出线291上,同样用于在附加数据变换中及配置和互连进程中使用。
在优选实施例中,不同输入及输出线281和291的选择及通过互连210、220和240的不同连接的创建均在来自计算单元控制器255的控制位265的控制下,如下所述。基于这些控制位265,各种输入使能251、输入选取252、输出选取253、MUX选取254、DEMUX使能256、DEMUX选取257、及DEMUX输出选取258可被激活或去活。
示例性的计算单元200包括一通过控制位265提供控制的计算单元控制器255,在其上每一计算元件250、互连210、220和240、及其他元件随每一时钟周期工作。没有分别示出,通过互连210、220和240,按照需要,不同的控制位265被分布给计算单元200的不同部分,如不同的输入使能251、输入选取252、输出选取253、MUX选取254、DEMUX使能256、DEMUX选取257、及DEMUX输出选取258。CU控制器295也包括一根或多根用于控制(或配置)信息的接收和状态信息的传输的线295。
如上所述,互连可包括概念上区分的具有不同位宽度的数据互连网络240和布尔逻辑互连网络210。总之,(较宽的)数据互连网络240被使用于创建可配置和可重配置连接而用于数据及配置信息的相应路由选择。(较窄的)布尔逻辑互连网络210,在也被使用于创建可配置及可重配置连接的同时,被使用于数据流图(DFG)的逻辑(或布尔逻辑)决策的控制,在这些DFG中产生决策节点,并还可用于这些DFG内的数据路由选择。
图6为根据本发明的、具有多个不同固定计算元件的示例性优选多功能自适应计算单元500的详细图示。当被配置后,自适应计算单元500因而执行在相关申请中讨论的各种功能,如有限脉冲响应过滤、快速傅立叶变换、及其他功能如离散余弦变换,对通信工作状态是有用的。如图所示,该多功能自适应计算单元500包括用于多个固定计算元件的多个配置的能力,多个固定计算元件包括输入存储器520、数据存储器525、寄存器530(图示为寄存器530A-530Q)、乘法器540(图示为乘法器540A-540D)、加法器545、第一算法逻辑单元(ALU)550(图示为ALU_1 550A-550D)、第二算法逻辑单元(ALU)555(图示为ALU_2 555A-555D)、及流水线(长度1)寄存器560,且输入505、线515、输出570、及多路复用器(MUX或MX)510(图示为MUX和MX510A-510K)形成互连网络210、220和240。两个不同的ALU550和555最好被使用,例如,对于并行加法和减法运算,对离散余弦变换中的二进制运算特别有用。
图7为根据本发明的、具有多个固定计算元件的优选自适应逻辑处理器(ALP)计算单元600的详细图示。ALP600是高度可适应的,且最好被使用于输入/输出配置、有限状态机实现、常规现场可编程、及位处理。ALP600的固定计算元件是多个自适应核心单元(CC)610(图8)的每一个的一部分,如图9中所分别示出的。一互连网络210、220和240由多个纵向输入(VI)615、纵向中继器(VR)620、纵向输出(VO)625、水平中继器(HR)630、水平端接器(HT)635、及水平控制器(HC)形成。
图8为根据本发明的、具有固定计算元件650的自适应逻辑处理器计算单元600的优选核心单元610的详细图示。固定计算元件为一3输入、2输出功能发生器550,在图9中被单独示出。优选核心单元610也包括控制逻辑655、控制输入665、控制输出670(提供输出互连)、输出675、及输入(带有互连MUX)660(提供输入互连)。
图9是根据本发明的、一自适应逻辑处理器计算单元600的核心单元610的优选固定计算元件650的详细图示。固定计算元件650包括多个“异”NOR(XNOR)门680、NOR门685、NAND门690、及“异”0R(XOR)门695组成,具有三个输入720和两个输出710。配置和互连通过MUX705和互连输入730提供。
从上述内容可明显得出的是,多个固定的异类计算元件(250)的使用,其可被配置和重配置以形成异类计算单元(200),其还可被配置和重配置以形成异类矩阵150,通过改变互连(110、210、240和220)的级别,创建完全新类的集成电路,其可被可替换地称为自适应计算体系结构或自适应计算引擎。应当注意的是,本发明的自适应计算体系结构不能从概念上或从命名观点而被完全特征化在FPGA、ASIC或处理器的成规或范畴内。例如,自适应计算体系结构的非FPGA特征是很明显的,因为自适应计算体系结构不包含同样的逻辑单元的阵列,或者更简单地,任何种类的重复阵列。同样例如,自适应计算体系结构的非ASIC特征也是很明显的,因为自适应计算体系结构不是专用的,而是提供多种工作状态且可重配置,最好是实时的。还是举例,自适应计算体系结构的非处理器特性也是很明显的,因为自适应计算体系结构适合被配置,以直接基于数据操作,而不是集中于执行指令、而数据处理仅是副产品。
再次参考图1和2,本发明的各个系统和方法可在ACE100体系结构的上下文中看到,基于固定计算元件250响应于一组或多组配置信息的配置和/或重配置。没有配置信息的“更多东西”,ACE100实质上或有效地是一空的或“空白”装置。为了提供所想要的功能和基于相应数据操作,如无线通信、无线电接收、或MP3音乐播放,配置信息是必须的,以为ACE100产生创建一种或多种工作状态的配置。
这种配置和重配置可以多种方式出现。例如,整个ACE100可在任何特定使用之前配置,如预配置为移动通信装置。在另外的实施例中,ACE100可被配置以具有操作系统、启动(导入)、获得并装载其他用于特定工作状态和功能的配置,如通过网络40。ACE100也可被部分配置,即一些矩阵150被配置并运行,同时其他矩阵150正被配置为其他功能。
如上所述,这样的配置信息可与数据交叉存取以形成silverware(或silverware模块)。此外,这样的配置信息也可分离于任何数据(跨时间有效地分布一silverware模块)。例如,第一组配置信息可被提供给ACE100而用于第一工作状态,如用于移动通信。数据如声音数据可在随后在任何给定通信会话期间被分离提供。ACE100的各个控制器120功能接着将适当的配置信息子集与相应的数据交叉存取以提供silverware模块给矩阵150。如上所述,这样的控制器功能可被分布在各个矩阵150内,或可被嵌入配置信息本身内。
参考图1,ACE100可从多个源获得配置信息。如图1中所示,配置信息可通过从服务器54、WAN42、LAN41或附属网络实体50下载、经网络40(具有任何可使用的干涉开关56和52及基站25)或经路由器53提供给ACE100。下载可以是有线(如双绞线、光纤、同轴电缆、混合同轴光纤)或无线的,如通过基站25的收发器或人造卫星(未示出)或无线LAN43。配置信息也可通过其他介质如闪速存储器10、silverware存储介质15、计算机或其他机器可读的介质20、PCMCIA卡、PDA模块、或其他存储卡而提供给ACE100。在优选ACE100实施例中,该配置信息被存储在存储器140中,在各个矩阵150内分布的存储器,或在系统60(SOC)实施例中,也可被存储在存储器61中。配置信息也可简单地被保存为矩阵150的实际配置,MIN110有效地充作存储器。对于特定应用或简单使用,配置信息也可是瞬时的——实时分布并接收。其他相当的供应和存储手段对本领域技术人员是显而易见的。(一ACE100通过下载或其他介质接收配置信息在此通常被称为“接收”ACE。)
此外,对该配置信息的需要或请求也可源于多个源,包括系统用户、基础设施的元件、ACE100、包括ACE100的另外的装置、或一独立装置。例如,系统用户可请求新配置信息的下载以将装置升级到新标准,或可购买包含新配置信息的存储器模块(如闪存10或silverware存储介质15)以播放附加的、有版权的MP3音乐。基础设施元件也可启动新配置的下载,或者传输给单个ACE100装置(以提供者和接收者一对一(1:1)对应),或者传播给许多ACE100装置(多用户,提供者和接收者为一对多(1:多)对应),以提供系统升级、适应新标准、或提供其他实时性能增强。
本发明的另一新元件涉及由ACE100本身(或包括ACE100的另外装置)产生的配置或重配置请求,提供自我修改和自我配置的机制。例如,通常具有在美国使用的第一CDMA配置的ACE100(在移动站30或32中)可能在欧洲被启动,在没有标准CDMA信令的情况下,ACE100可请求一可适用于其当前位置的第二组配置信息的下载,从而使ACE100能够具有在欧洲使用的GSM配置。
如上所述,配置信息通常是多于一个的,由配置信息的多个子集组成,如第一配置信息、第二配置信息、直到第n配置信息。一“组”配置信息可被认为是对应于ACE100的一特定工作状态。例如,第一组配置信息可提供CDMA工作状态,而第二组配置信息可提供GSM工作状态。
同样如上所述,对于给定或选择的ACE100的高级工作状态(或,等价地,对于配置信息的给定或选择的组),各个固定的异类计算元件250被相应地配置和重配置为不同的响应于配置信息的子集的低级功能状态,如响应于第一配置信息而用于离散余弦变换的配置及响应于第二配置信息而用于快速傅立叶变换的重配置。
配置信息也可具有不同的形式。在一实施例中,配置信息可包括一个或多个离散的二进位信息包,其可保存于存储器140中,分布地保存在矩阵150内,或直接保存为MIN110的配置。配置信息也可被具体化为连续形式,如连续的二进位或其他信息流。如所指引的,自配置信息的配置和其他控制与数据相互交叉以形成silverware模块,实时用于ACE100内。在另一实施例中,配置信息可与相应的数据一起实时提供,以连续流的形式(连续用于所选择功能的持续时间)。例如,用于MP3播放器的配置信息可在silverware流中与用于将要被播放的音乐的数据位文件一起实时提供。
两个另外的特征还被使用在本发明中,以为ACE100提供能够响应于配置信息而安全且有效地被配置和/或重配置的能力。首先,“单元硬件(unit hardware)”的概念,一个用于ACE100源或能力的测量的参数,被用于测量给定ACE100的容量以接纳一新配置并执行新功能,或保持当前配置及功能并提供足够级别的性能,或完全替换当前配置及功能。例如,第一代ACE100可具有足够的测定为单元硬件的源来配置为CDMA移动站且同时配置为个人数字助理。装载新配置的企图,例如用于MP3播放器,由于不足的系统资源而可能是不可取的,从而新配置会导致CDMA性能降低到低于可接受的级别。相反,最初被配置为PDA的第一代ACE100可具有足够的剩余资源来装载新配置,因为对于这些应用,更大的性能降级是可以允许的。继续该例子,第二或第三代ACE100可具有足够的计算元件、互连或其他ACE100资源,以不仅支持其当前存在的配置,而且支持那些新配置(具有相应的附加功能),如保持现有的CDAM配置且同时具有足够的资源用于另外的GSM和MP3配置。
与该测量重配置容量的单元硬件有关的概念是用于增加新功能的配置信息的多版本或库的概念。该配置信息的多版本或库被修改以对应于潜在不同的ACE100装置的能力,特别用于相比于先前体系结构的当前ACE体系结构。例如,一套不同的配置信息组可被开发以提供特定的工作状态,与性能质量和特征的数量和类型具有不同的相关。各组或版本配置信息的每一个被产生以具有对应于可用的及变化级的ACE100重配置容量的系统需求。这样的配置信息库,具有对应于“单元硬件”级的需求级,可在所请求的下载或其他提供之前产生,或可在实时基础上按需产生,被修改为接收ACE100的特定配置容量。例如,相应的、修改后的配置信息下载可被实时确定,基于ACE100和配置提供者之间的协商或相互作用,产生并提供适于用于给定工作状态的协商或预定级的性能的配置信息。
同样例如,用于特定工作状态的配置信息可仅有一个具有预定系统需求的版本可用。在这种情况下,如果特定ACE100不具有相应的满足那些需求的容量,ACE100本身可拒绝该潜在下载。
因而,在用于特定工作状态的特定ACE体系结构的配置(和/或重配置)之前,ACE100的能力被确定,以避免可能潜在改变或不利于装置的先前存在的工作状态或其他功能的配置的下载或接收,或提供更多的修改为适于特定ACE100的能力的适当下载。
可延展ACE100体系结构的特性,具有不同的响应于配置信息而创建或移除的物理连接,导致配置和重配置的安全性的极为重要。假定该配置能够改变ACE体系结构的工作状态,在优选方法、系统和装置实施例中,授权和安全性措施被实施以避免潜在的破坏性的或有害的配置,如病毒或其他不想要的配置信息。
几个级别的安全性可被实施以控制ACE100的可配置性和可重配置性,第一级别的安全性在授权级别实施以请求或接收配置信息。例如,ACE100可具有独特的标识符或数字签名,其在配置信息的下载之前在“握手”或其他信息初始交换期间传送给服务器54。服务器54可访问经授权的收件人的数据库,如果特定ACE100被包括,服务器54将授权该下载。该授权措施对于知识产权的保护是很重要的,如有版权的材料,及其他秘密级或内部级的信息。另外级别的安全性可被实施以防止病毒或腐败配置信息的可能下载,其使用各种加密和解密技术。
各种形式的监控、跟踪及其他记录保持也被使用来确定和说明各种配置和内容使用可能性,并可包括大量不同的网络实体。例如,配置信息的特定下载可从一个以上的网络实体产生,同时用于配置信息的特定下载的一事务处理同样跨多个网络实体分布。继续该例子,一配置信息的下载请求可在无线服务提供者“A”的基站25处接收。为实现该请求,无线服务提供者“A”确定请求ACE100的授权状态,当被授权时,转发请求给另一提供者,如内容提供者“B”,其使用内容服务器54提供所请求的数据,如音乐比特文件。同样响应于来自于提供者“A”的请求,一组MP3配置信息同时由配置提供者“C”提供,其使用在其控制下的第二不同的服务器54,如配置信息服务器。内容(数据)及配置信息被提供给silverware提供者“D”,其随后将数据和配置交叉而形成silverware模块,其使用具有silverware模块应用节点51的第一附属网络实体50。接下来,加密提供者“E”加密silverware模块,使用具有加密应用节点51的第二附属网络实体50,并提供加密后的silverware模块给服务提供者“A”,从而传输给请求ACE100。用于每一分配的事务的相应帐目和其他记录可被产生,以及相应的版税、使用和许可费的分配。内容使用还可由内容服务器跟踪。
除了跨空间分布以外,配置信息的产生和提供也可跨时间分布,且上面提及的(及下面参考图10所述的)各个功能在不同的时间间隔期间执行。例如,配置信息的一个或多个版本或组可在第一预定时间段期间产生和保存,如在任何特定使用之前。随后,该组配置信息可在第二预定时间段提供,如在安全性和财务授权进程之后。
图10为根据本发明的方法实施例的框图,其提供了有用的概要内容。图10中所示的方法涉及通过某类网络40提供配置信息。对于其他形式的递送,下述的许多步骤可被省略,如通过购买闪速模块10提供配置信息。
该方法始于步骤800,请求或确定一组配置信息的接收是必要的或可取的。如上所述,这样的请求或确定可由ACE100、网络实体如服务器54或附属网络实体50、或其他装置产生。该方法接下来在步骤805确定该请求(或确定)是否被授权。当未被授权,该方法将结束,返回步骤840。
当在步骤805授权,该方法在步骤810确定ACE100的重配置能力,即确定接收ACE100的可用单元硬件。接着,在步骤815,确定适于已确定的ACE100的重配置能力的配置信息的一个或多个版本是否可用。如果在步骤805没有适当的版本可用,该方法将结束并返回步骤840。当在步骤815有适当版本可用,在步骤820选取(并产生)适于接收ACE100的版本。如上所述,步骤820可以是交互的或协商的进程,基于可用重配置能力和潜在竞争同一资源的工作状态之间的优先级。此外,同样如上所述,所请求的配置信息的所选择的版本的产生和存储可提前发生,或可在运行时(下载时)发生。
在适当的配置信息的选取之后,在步骤825实施安全性措施,如配置比特文件的加密。安全的配置信息接着在步骤830被转移给接收ACE100,如通过网络下载或包含相应的比特文件的介质的提供(如闪存10或介质15和20)。在优选实施例中,在步骤835产生相应的记录,如更新数据库以反映一新配置版本,并产生帐目或帐单项。在步骤835之后,或在步骤805和815之后,该方法结束并返回步骤840。
本发明的各个实施例的大量优点是很明显的。本发明提供了一种用于自适应集成电路的配置的方法和系统,以为ACE电路或其他组合有ACE技术的装置提供一种或多种工作状态或其他功能。本发明方法和系统将配置信息和ACE电路(或ACE IC)结合在一起,用于所选择的工作状态的提供。此外,本发明系统和方法能够确定ACE重配置能力,提供安全的和授权的配置,并提供对配置和内容使用的适当的监控。
本发明的其他优点对那些本领域技术人员也是很明显的。本发明ACE100体系结构有效地结合了处理器、ASIC和FPGA的各种优点并使它们最大化,同时使潜在缺点最小化。ACE100包括处理器的编程灵活性、GPGA的后安装灵活性、及ASIC的高速度和高使用因数。ACE100很容易重配置,提前、实时或以其他速度,且能够具有相应的多种工作状态。此外,通过对于可重配置加速的特定功能的选择,ACE100使功耗最小并适于低功率应用,如用于手持及其他电池供电的装置。
从前面所述的,在不脱离本发明新颖的概念的精神和范围的情况下,应可看到各种变化及修改均可得到。应该理解的是,本发明并不限于在此图解的特定方法和装置。当然,本发明应为由附属权利要求覆盖的内容及落入权利要求范围内的所有修改。
Claims (41)
1、一种自适应配置系统,该系统包括:
第一组配置信息,第一组配置信息包括第一子集配置信息及第二子集配置信息;
第一多个异类计算元件;第二多个异类计算元件;第一多个异类计算元件包括第一计算元件和第二计算元件,第一计算元件具有第一固定体系结构,第二计算元件具有第二固定体系结构,第一体系结构不同于第二体系结构;及
与第一和第二多个异类计算元件连接的互连网络,互连网络包括多个交换元件和多个路由选择元件,该互连网络适于响应于第一子集配置信息而将第一多个异类计算元件配置为多个工作状态的第一工作状态;该互连网络还适于响应于第二子集配置信息而将第二多个异类计算元件配置为多个工作状态的第二工作状态;第一工作状态不同于第二工作状态。
2、根据权利要求1所述的系统,其中第一组配置信息提供第一系统工作状态。
3、根据权利要求2所述的系统,还包括第二组配置信息,第二组配置信息提供第二系统工作状态。
4、根据权利要求3所述的系统,其中第一组配置信息对应于第一系统配置容量,第二组配置信息对应于第二系统配置容量。
5、根据权利要求1所述的系统,其中第一组配置信息从多组配置信息中选取。
6、根据权利要求1所述的系统,还包括:
与第一和第二多个异类计算元件及互连网络连接的存储器,该存储器用于保存第一组配置信息。
7、根据权利要求1所述的系统,其中第一组配置信息被保存在配置为存储器工作状态的第三多个异类计算元件中。
8、根据权利要求1所述的系统,其中第一组配置信息被保存为多个异类计算元件的配置。
9、根据权利要求1所述的系统,其中第一组配置信息从机器可读的介质传送给系统。
10、根据权利要求1所述的系统,其中第一组配置信息通过无线接口传送给系统。
11、根据权利要求1所述的系统,其中第一组配置信息通过有线接口传送给系统。
12、根据权利要求1所述的系统,其中第一组配置信息被具体为多个离散信息数据包。
13、根据权利要求1所述的系统,其中第一组配置信息被具体为信息数据比特流。
14、根据权利要求1所述的系统,其中第一固定体系结构和第二固定体系结构均从多个固定体系结构中选取,多个固定的体系结构包括适于执行至少下述两种相应功能的固定体系结构:存储、加法、乘法、复数乘法、减法、配置、重配置、控制、输入、输出、及现场可编程。
15、根据权利要求1所述的系统,其中多个工作状态包括至少两种下述工作状态:线性算法运算、非线性算法运算、有限状态机运算、控制器运算、存储运算、及位级处理。
16、根据权利要求1所述的系统,其中第一子集配置信息及第二子集配置信息均与数据混合以形成一单一比特流。
17、根据权利要求1所述的系统,还包括:
与第一和第二多个异类计算元件及互连网络连接的控制器,该控制器适于指引和安排第一多个异类计算元件配置为第一工作状态及第二多个异类计算元件配置为第二工作状态。
18、根据权利要求17所述的系统,其中控制器还适于用相应数据计时和安排第一和第二多个异类计算元件的配置。
19、根据权利要求17所述的系统,其中控制器还适于从单一比特流选取第一子集配置信息及第二子集配置信息,单一比特流包含与第一组配置信息混合的数据。
20、根据权利要求1所述的系统,其中当第二多个异类计算元件被配置为控制器工作状态时,第二多个异类计算元件适于指引和安排第一多个异类计算元件配置为第一工作状态。
21、根据权利要求20所述的系统,其中第二多个异类计算元件还适于用相应数据计时和安排第一多个异类计算元件的配置。
22、根据权利要求20所述的系统,其中第二多个异类计算元件还适于从单一比特流选取第一子集配置信息及第二子集配置信息,单一比特流包含与第一组配置信息混合的数据。
23、根据权利要求1所述的系统,其中该系统被体现在具有多工作状态的移动站内。
24、根据权利要求23所述的系统,其中多工作状态移动站包括下述工作模式中的至少两种:移动远程通信模式、个人数字助理模式、多媒体接收模式、基于移动信息包的通信模式、及寻呼模式。
25、根据权利要求1所述的系统,其中该系统被体现在具有多工作状态的服务器内。
26、根据权利要求1所述的系统,其中该系统被体现在具有多工作状态的附属网络实体内。
27、根据权利要求1所述的系统,其中第一多个异类计算元件被配置以产生一用于第二组配置信息的请求,第二组配置信息用于第二系统工作状态。
28、根据权利要求27所述的系统,其中第一多个异类计算元件还被配置以在使用第二组配置信息重配置第二系统工作状态之前确定系统重配置容量。
29、根据权利要求28所述的系统,其中该系统重配置容量在硬件的多个预先定义的单元中确定。
30、根据权利要求1所述的系统,其中该系统被体现在集成电路内。
31、根据权利要求1所述的系统,其中在第二多个异类计算元件正被配置为第二工作状态的同时,第一多个异类计算元件在第一工作状态中工作。
32、一种自适应集成电路,包括:
适于保存配置信息组的存储器,该配置信息组包括第一子集配置信息及第二子集配置信息;
第一和第二多个异类计算元件,第一多个异类计算元件包括第一计算元件和第二计算元件,第一计算元件具有第一固定体系结构,第二计算元件具有第二固定体系结构,第一固定体系结构不同于第二体系结构;
连接到第一和第二多个异类计算元件的互连网络,互连网络包括多个路由选择元件及第一和第二多个交换元件,第一多个交换元件能够响应于第一子集配置信息将第一多个异类计算元件配置为多个工作状态的第一工作状态,第二多个交换元件能够响应于第二子集配置信息将第二多个异类计算元件配置为多个工作状态的第二工作状态,第一工作状态不同于第二工作状态;路由选择元件能够有差别地将数据和配置信息发送给第一和第二多个异类计算元件;
其中第一多个异类计算元件被配置为控制器工作状态,控制器工作状态包括用于指引多个异类计算元件的配置和重配置的功能、用于从包含与配置信息组混合的数据的单一比特流选取第一子集配置信息和第二子集配置信息的功能、及用于安排以相应的数据对多个异类计算元件配置和重配置的功能;及
其中第二多个异类计算元件被配置为用于保存配置信息组的存储器工作状态。
33、根据权利要求32所述的自适应集成电路,其中第一多个异类计算元件分布于多个异类计算元件之间。
34、一种自适应集成电路,包括:
适于保存配置信息的存储器,所述配置信息包括第一子集配置信息及第二子集配置信息;
具有固定且不同的电路体系结构的多个计算元件,多个计算元件包括第一计算元件和第二计算元件,第一计算元件具有第一固定体系结构,第二计算元件具有第二固定体系结构,第一固定体系结构不同于第二体系结构,多个固定体系结构包括用于存储、加法、乘法、复数乘法、减法、配置、重配置、控制、输入、输出、及现场可编程性的功能;及
连接到多个计算元件的互连网络,互连网络包括多个路由选择元件和多个交换元件,通过有选择地将数据发送给多个计算元件并在多个计算元件的所选计算元件之间有选择地切换输入和输出连接,响应于第一子集配置信息,互连网络能够将多个计算元件配置为多个工作状态的第一工作状态,响应于第二子集配置信息,互连网络还用于重配置多个计算元件为多个工作状态的第二工作状态,第一工作状态不同于第二工作状态,且多个工作状态包括线性算法运算、非线性算法运算、有限状态机运算、控制器运算、存储运算、及位级处理。
35、一种自适应集成电路,包括:
第一配置信息;
第一多个固定且不同的计算元件;及
连接到第一多个固定且不同的计算元件的互连网络,互连网络包括多个路由选择元件,互连网络适于响应于第一配置信息而将第一多个固定且不同的计算元件配置为多个工作状态中的第一工作状态。
36、根据权利要求35所述的自适应集成电路,其中第一配置信息提供工作状态。
37、根据权利要求35所述的自适应集成电路,其中多工作状态包括下述工作状态中的至少两种:线性算法运算、非线性算法运算、有限状态机运算、控制器运算、存储运算、及位级处理。
38、根据权利要求35所述的自适应集成电路,其中第一配置信息被保存在配置为存储器工作状态的多个固定且不同的计算元件的至少一计算元件之中。
39、根据权利要求35所述的自适应集成电路,其中第一配置信息被保存为第一多个固定且不同的计算元件的配置。
40、根据权利要求35所述的自适应集成电路,其中第一多个固定且不同的计算元件从多个固定的电路体系结构中选取,多个固定的电路体系结构包括适于执行至少两种下述功能的电路:存储、加法、乘法、复数乘法、减法、配置、重配置、控制、输入、输出、及现场可编程。
41、根据权利要求35所述的自适应集成电路,其中第一多个固定且不同的计算元件均被配置以从包含与第一配置信息混合的数据的单一比特流识别和选取第一配置信息。
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US8225073B2 (en) | 2012-07-17 |
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CN1599899A (zh) | 2005-03-23 |
EP1449072A4 (en) | 2006-08-16 |
TWI262400B (en) | 2006-09-21 |
TW200303477A (en) | 2003-09-01 |
JP2011123882A (ja) | 2011-06-23 |
US9594723B2 (en) | 2017-03-14 |
JP2005512186A (ja) | 2005-04-28 |
US20090172137A1 (en) | 2009-07-02 |
KR20050058247A (ko) | 2005-06-16 |
US20030102889A1 (en) | 2003-06-05 |
US20130304960A1 (en) | 2013-11-14 |
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