CN100459052C - 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 - Google Patents

形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 Download PDF

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Publication number
CN100459052C
CN100459052C CNB2005800392172A CN200580039217A CN100459052C CN 100459052 C CN100459052 C CN 100459052C CN B2005800392172 A CNB2005800392172 A CN B2005800392172A CN 200580039217 A CN200580039217 A CN 200580039217A CN 100459052 C CN100459052 C CN 100459052C
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CN
China
Prior art keywords
gate electrode
sidewall
spacer
forming
spacers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB2005800392172A
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English (en)
Chinese (zh)
Other versions
CN101073143A (zh
Inventor
M·C·克林
D·邦瑟
S·达克希那-穆尔蒂
A·野村
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/01328—Aspects related to lithography, isolation or planarisation of the conductor by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CNB2005800392172A 2004-12-03 2005-11-29 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 Expired - Fee Related CN100459052C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/002,586 2004-12-03
US11/002,586 US7279386B2 (en) 2004-12-03 2004-12-03 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions

Publications (2)

Publication Number Publication Date
CN101073143A CN101073143A (zh) 2007-11-14
CN100459052C true CN100459052C (zh) 2009-02-04

Family

ID=36218711

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800392172A Expired - Fee Related CN100459052C (zh) 2004-12-03 2005-11-29 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法

Country Status (8)

Country Link
US (1) US7279386B2 (https=)
EP (1) EP1829092B1 (https=)
JP (1) JP2008522441A (https=)
KR (1) KR101142992B1 (https=)
CN (1) CN100459052C (https=)
DE (1) DE602005011483D1 (https=)
TW (1) TWI397107B (https=)
WO (1) WO2006060528A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279386B2 (en) 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
US7585735B2 (en) * 2005-02-01 2009-09-08 Freescale Semiconductor, Inc. Asymmetric spacers and asymmetric source/drain extension layers
US20110049582A1 (en) * 2009-09-03 2011-03-03 International Business Machines Corporation Asymmetric source and drain stressor regions
CN103928315B (zh) * 2014-04-28 2017-06-23 上海华力微电子有限公司 一种栅极侧墙减薄工艺
CN103943462A (zh) * 2014-04-28 2014-07-23 上海华力微电子有限公司 针对薄膜沉积产生负载效应的消除方法
US9941388B2 (en) 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10566194B2 (en) * 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
CN1391258A (zh) * 2001-06-12 2003-01-15 三菱电机株式会社 半导体装置的制造方法
CN1470947A (zh) * 2002-06-27 2004-01-28 ��ʽ���綫֥ 电子束曝光的邻近效应修正方法及其应用

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JP2685149B2 (ja) * 1988-04-11 1997-12-03 住友電気工業株式会社 電界効果トランジスタの製造方法
JPH08335554A (ja) * 1995-06-07 1996-12-17 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5656518A (en) * 1996-09-13 1997-08-12 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor
JP3530692B2 (ja) * 1996-11-06 2004-05-24 キヤノン株式会社 走査型露光装置及びそれを用いたデバイスの製造方法
JP3598693B2 (ja) * 1996-12-03 2004-12-08 ソニー株式会社 半導体装置およびその製造方法
JPH10242460A (ja) * 1997-02-25 1998-09-11 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000012844A (ja) * 1998-06-19 2000-01-14 Sony Corp 高耐圧半導体装置及びその製造方法
KR100284905B1 (ko) * 1998-10-16 2001-04-02 윤종용 반도체 장치의 콘택 형성 방법
JP2000260701A (ja) * 1999-03-10 2000-09-22 Toshiba Corp パターン形成方法及びそれを用いた半導体装置の製造方法
JP3381147B2 (ja) * 1999-04-16 2003-02-24 日本電気株式会社 半導体装置及びその製造方法
JP2001250756A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd 半導体集積回路装置の製造方法
TW540102B (en) * 2001-12-31 2003-07-01 Silicon Integrated Sys Corp Formation method of oxide film
JP2004165218A (ja) * 2002-11-08 2004-06-10 Canon Inc 露光装置
TWI222227B (en) * 2003-05-15 2004-10-11 Au Optronics Corp Method for forming LDD of semiconductor devices
JP2005012038A (ja) * 2003-06-20 2005-01-13 Renesas Technology Corp 半導体装置の製造方法
US6893967B1 (en) 2004-01-13 2005-05-17 Advanced Micro Devices, Inc. L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials
US7279386B2 (en) 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
CN1391258A (zh) * 2001-06-12 2003-01-15 三菱电机株式会社 半导体装置的制造方法
CN1470947A (zh) * 2002-06-27 2004-01-28 ��ʽ���綫֥ 电子束曝光的邻近效应修正方法及其应用

Also Published As

Publication number Publication date
WO2006060528A3 (en) 2006-10-26
US20060121711A1 (en) 2006-06-08
EP1829092B1 (en) 2008-12-03
WO2006060528A2 (en) 2006-06-08
KR20070085551A (ko) 2007-08-27
JP2008522441A (ja) 2008-06-26
DE602005011483D1 (de) 2009-01-15
KR101142992B1 (ko) 2012-05-15
US7279386B2 (en) 2007-10-09
TW200623235A (en) 2006-07-01
TWI397107B (zh) 2013-05-21
EP1829092A2 (en) 2007-09-05
CN101073143A (zh) 2007-11-14

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