CN100403534C - 具有集成器件的微电子衬底及其制造方法 - Google Patents

具有集成器件的微电子衬底及其制造方法 Download PDF

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CN100403534C
CN100403534C CNB018173810A CN01817381A CN100403534C CN 100403534 C CN100403534 C CN 100403534C CN B018173810 A CNB018173810 A CN B018173810A CN 01817381 A CN01817381 A CN 01817381A CN 100403534 C CN100403534 C CN 100403534C
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microelectronic
core
dielectric layer
microelectronic substrate
conductive trace
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CN1524293A (zh
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J·李
Q·邬
S·托勒
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Intel Corp
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Intel Corp
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Abstract

一种微电子衬底，包括至少一个设置在微电子衬底核心的开口内的微电子管芯，其中在开口中未被微电子管芯占据的部分内设置了密封材料，或者在没有微电子衬底核心下密封了多个微电子管芯。然后在微电子管芯、密封材料和微电子衬底核心(如果存在的话)上制造出介质材料和导电迹线的互连层，从而形成微电子衬底。

Description

具有集成器件的微电子衬底及其制造方法
技术领域
本申请是于2000年8月16日提交的申请No.09/640961的继续部分。
本发明涉及一种用于微电子衬底的制造的装置和工艺。特别是，本发明涉及一种可将至少一个微电子管芯密封在微电子衬底核心中或密封至少一个微电子管芯(无微电子衬底核心)以形成微电子衬底的制造技术。
背景技术
在所有新近制造的电子设备中实际上都存在着将各个微电子器件相连的衬底。这些衬底通常为印制电路板。印制电路板基本上为介质衬底，并且在介质衬底中或其上形成有金属迹线。一种类型的印制电路板为单面板。如图20所示，单面板200包括诸如FR4材料、环氧树脂、聚酰亚胺、三嗪树脂等的介质衬底202，在其一侧(如第一表面206)上具有诸如铜、铝等的导电迹线204，其中导电迹线204与连接在第一表面206上的微电子器件208(如倒装片)电连接。然而，单面板200导致了相对较长的导电迹线204，这又使速度和性能下降。单面板200还需要用于导电迹线204布线的较大表面积以便与多个微电子器件208互连，这增大了所得组件的尺寸。
当然应当理解，关于图20(以及后面的图21)中的介质衬底202、导电迹线204和微电子器件208的介绍只是出于说明的目的而给出，其中一些尺寸被放大以说明概念，而不是准确地绘出了具体情况。
已经开发出了双面板210以减轻导电迹线较长的问题。如图21所示，双面板210包括介质衬底202，在介质衬底的第一表面206和介质衬底的第二表面212上均具有导电迹线204。至少一个导电通孔214延伸穿过介质衬底202，将第一表面206上的至少一个导电迹线204与第二表面212上的至少一个导电迹线204相连。因此，介质衬底的第一表面206和介质衬底的第二表面212上的微电子器件208可电连通。导电通孔214可以是涂镀的通孔，可由本领域中已知的任何方式形成。
还存在另一种板设计，称为多层板。多层板包括其上和其间带有导电迹线的两片或多片介质材料(例如为第一介质材料和第二介质材料)，并且在第一介质材料和第二介质材料中形成了导电通孔。对导电迹线的布线来说，这种设计只需较短的迹线和较小表面积。虽然这种板对于过去和当前的微电子器件应用来说是足够的，然而随着微电子器件的速度和性能的增加，对更高性能和更短迹线的衬底板的要求也增加。因此，希望开发出能够达到更高的速度和性能的新型衬底/板。
发明内容
根据本发明的第一方面，提出了一种微电子衬底，包括：具有第一表面和相对的第二表面的微电子衬底核心，该微电子衬底核心具有至少一个形成于其中的开口，其从微电子衬底核心的第一表面延伸到微电子衬底核心的第二表面；至少一个设置在所述至少一个开口内的微电子管芯，所述至少一个微电子管芯具有有效面；将微电子衬底核心与至少一个微电子管芯相连的密封材料；设于核心、管芯和密封材料中的至少一个之上的第一介质层；设于第一介质层之上的第一多个导电迹线；第二介质层，其包括设于第一介质层和第一多个导电迹线之上的第二多个通孔；设于第二介质层之上的第二多个导电迹线；设于第二多个导电迹线之上的多个导电凸起，其中第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，该微电子衬底还包括至少两个与多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
根据本发明的第二方面，提出了一种微电子衬底，包括：具有第一表面和相对的第二表面的核心，所述核心具有至少一个形成于其中的开口，其从核心的第一表面延伸到核心的第二表面；至少两个设置在所述至少一个开口内的管芯，各所述至少两个管芯均具有有效面；将核心与至少两个管芯相连的密封材料；设于核心、至少两个管芯和密封材料中的至少一个之上的第一介质层；设于第一介质层之上的第一多个导电迹线；第二介质层，其包括设于第一介质层和第一多个导电迹线之上的第二多个通孔；设于第二介质层之上的第二多个导电迹线，其中第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，所述微电子衬底还包括至少两个与多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
根据本发明的第三方面，提出了一种制造微电子衬底的方法，包括：提供具有第一表面和相对的第二表面的微电子衬底核心，该微电子衬底核心具有至少一个形成于其中的开口，其从微电子衬底核心的第一表面延伸到微电子衬底核心的第二表面；将至少一个微电子管芯设置在所述至少一个开口内，所述至少一个微电子管芯具有有效面；用密封材料将微电子衬底核心与至少一个微电子管芯相连；提供设于第一介质层之上的第一多个导电迹线；提供第二介质层，其包括设于第一介质层和第一多个导电迹线之上的第二多个通孔；提供设于第二介质层之上的第二多个导电迹线；提供设于第二多个导电迹线之上的多个导电凸起，其中第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，所述微电子衬底还包括至少两个与所述多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
根据本发明的第四方面，提出了一种制造微电子衬底的方法，包括：提供保护膜；使多个微电子管芯的有效面与保护膜相邻接；将密封材料至少放置在各所述多个微电子管芯之间；除去保护膜；提供设于第一介质层之上的第一多个导电迹线；提供第二介质层，其包括设于第一介质层和第一多个导电迹线之上的第二多个通孔；提供设于第二介质层之上的第二多个导电迹线；提供设于第二多个导电迹线之上的多个导电凸起，其中第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，所述微电子衬底还包括至少两个与所述多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
附图说明
虽然说明书以权利要求作为结束，且权利要求特别指出和清楚要求了被视为本发明的内容，然而在结合附图阅读时可从本发明的下述介绍中更容易地清楚本发明的特征，在附图中：
图1是根据本发明的微电子衬底核心的斜视图；
图2是根据本发明的具有间隔开的微电子衬底核心开口的示例的微电子衬底核心的顶平面视图；
图3是根据本发明的与保护膜相邻的微电子衬底核心的侧剖视图；
图4是根据本发明的置于微电子衬底核心的开口内的微电子管芯的侧剖视图，其中微电子管芯也与保护膜相邻；
图5是根据本发明的在密封后的图4所示组件的侧剖视图；
图6是根据本发明的除去保护膜后的图5所示组件的侧剖视图；
图7到15是根据本发明的在微电子管芯、密封材料和微电子衬底核心上形成互连层的工艺的侧剖视图；
图16是根据本发明的具有互连层和位于其上的焊球的图6所示组件的侧剖视图；
图17是根据本发明的未带有微电子衬底核心的图16所示组件的侧剖视图；
图18是不同尺寸的微电子管芯和器件的侧剖视图；
图19是位于一个核心开口内的多个微电子管芯的侧剖视图；
图20是本领域内已知的单面板的剖视图；
图21是本领域内已知的双面板的剖视图。
具体实施方式
虽然图1到19显示了本发明的各个视图，然而这些图并不意味着精确且详细地描述了微电子组件。相反，这些图只是以更清楚了表达了本发明概念的方式显示了微电子组件。另外，在这些图中共用的元件以相同的标号表示。
本发明包括了一种衬底制造技术，其可将至少一个微电子管芯置于微电子衬底核心的至少一个开口内并用密封材料将微电子管芯固定在所述开口内，或者是将至少一个微电子管芯密封在没有微电子衬底核心的密封材料内。然后在微电子管芯、密封材料和微电子衬底核心(如果有的话)上制造出介质材料和导电迹线的互连层，从而形成微电子衬底。用语“微电子衬底”包括了母板、外围卡、管壳(cartridge)、多芯片模块衬底和类似的结构，这对本领域的技术人员来说是很明显的。
本发明的技术优点在于，它可以使微电子衬底制造在微电子管芯周围，这就使微电子衬底内的微电子管芯以及与之相连的微电子器件之间的互连距离较短。这又导致了速度和性能的提高。此外，本发明的微电子衬底还导致了较小的形状因数，其能够很好地适用于移动系统(例如膝上型计算机、手持设备、个人数字助理等)。
图1显示了用于制造微电子衬底的微电子衬底核心102。微电子衬底核心102最好包括大致平面的材料。用于制造微电子衬底核心102的此材料包括但不限于双马来酰亚胺三嗪(“BT”)树脂的层合材料、FR4层合材料(一种阻燃玻璃/环氧树脂材料)、各种聚酰亚胺层合材料、陶瓷材料等，以及金属材料(如铜)等。微电子衬底核心102具有至少一个开口104，其从微电子衬底核心102的第一表面106延伸到微电子衬底核心102的相对的第二表面108。如图2所示，开口104可具有任何形状和大小，包括但不限于矩形/正方形104a、带圆角的矩形/正方形104b以及圆形104c。对开口104的大小和形状的唯一限制在于，它们的大小和形状必须能在其中容纳相应的微电子管芯，如下所述。
图3显示了与保护膜112相邻的微电子衬底核心的第一表面106。保护膜112最好为基本上柔性的材料，例如
Figure C0181738100121
聚酰亚胺薄膜(美国特拉华州Wilmington的E.I.du Pont de Nemours andCompany)，然而也可以由任何适当的材料包括金属薄膜制成。在一个优选实施例中，保护膜112具有与微电子衬底核心的热膨胀系数(CTE)基本上相同的热膨胀系数。图4显示了置于微电子衬底核心102的对应开口104中的微电子管芯114，其均具有有效面116和背面118。微电子管芯114可以是任何已知的有源或无源微电子器件，包括但不限于逻辑部件(CPU)、存储器(DRAM，SRAM，SDRAM等)、控制器(芯片组)、电容器、电阻器、电感器，等等。
在一个优选(所示)的实施例中，微电子衬底核心102的厚度117和微电子管芯114的厚度115基本上相等。微电子管芯114分别放置成使得它们的有效面116邻接于保护膜112。保护膜112可具有例如硅酮或丙烯酸的粘合剂，其与微电子衬底核心的第一表面106和微电子管芯的有效面116相连。这种粘合剂型的膜可在将微电子管芯114和微电子衬底核心102放入到模具、液体分配密封系统(优选)或用于密封工艺的其它设备中之前而施用。保护膜112可以是非粘合剂型的膜，例如ETFE(乙烯-四氟乙烯)或
Figure C0181738100122
膜，其在密封工艺中通过模具或其它设备的内表面而固定在微电子管芯的有效面116和微电子衬底核心的第一表面106上。
然后用密封材料122如塑料、树脂、环氧树脂、弹性体(如橡胶)材料等来密封微电子管芯114。如图5所示，密封材料122放置在开口104中未被微电子管芯114所占据的部分中。微电子管芯114的密封可由任何已知的工艺来实现，包括但不限于传递和压缩模制，以及分配。密封材料122将微电子管芯114固定在微电子衬底核心102内，为所得的结构提供了机械刚性，并为后续的迹线层构造提供了表面积。
在密封后除去保护膜112，如图6所示，暴露出微电子管芯的有效面116。同样如图6所示，密封材料122最好被模制或分配以填充在微电子衬底核心的第一表面106和微电子管芯的有效面116之间的空间内。这就形成了至少一个表面124，其基本上与微电子管芯的有效面116和微电子衬底核心的第一表面106成一平面。密封材料表面124可与微电子衬底核心的第一表面106一起在其它制造工序中使用，作为形成互连层如介质材料层和导电迹线的附加表面积。
虽然下述介绍涉及用于形成互连层的无突出块(bumpless)的组合层技术，然而这种制造方法并不限于此。互连层可由本领域中已知的多种技术来制造。
图7显示了用密封材料122密封在微电子衬底核心102内的一个微电子管芯114。当然，微电子管芯114包括位于微电子管芯的有效面116上的多个电触点132。电触点132与微电子管芯114内的电路(未示出)电连接。为简单和清楚起见，图中只显示了四个电触点132。
如图8所示，在微电子管芯的有效面116(包括电触点132)、微电子衬底核心的第一表面106和密封材料表面124上设置了第一介质层136，例如环氧树脂、聚酰亚胺、双苯并环丁烯等。本发明的介质层最好填充有环氧树脂，其可从美国加利福尼亚州Santa Clara的Ibiden美国公司和美国新泽西州Paramus的Ajinomoto美国公司中得到。可通过任何已知的工艺来形成第一介质层136，包括但不限于薄膜层合、旋涂、辊涂和喷射沉积。
如图9所示，随后形成穿过第一介质层136的多个通孔138。可通过本领域中已知的任何方法来形成多个通孔138，包括但不限于激光打孔、光刻术(之后通常还进行蚀刻)，并且如果第一介质层136是光敏的话，则可通过本领域中已知的与在光刻工艺中制造光致抗蚀掩膜相同的方式来形成多个通孔138。
如图10所示，在第一介质层136上形成多个导电迹线142，其中各导电迹线142中的一部分延伸到至少一个所述多个通孔138(见图9)中以与触点132电接触。该多个导电迹线142可由任何适用的导电材料制成，例如铜、铝及它们的合金。
可通过任何已知的技术来形成多个导电迹线142，包括但不限于半添加电镀(semi-additive plating)和光刻技术。代表性的半添加电镀技术包括沉积籽晶层(seed layer)，例如第一介质层136上的喷射沉积或无电沉积的金属。随后在籽晶层上形成抗蚀层的图案，例如钛/铜合金，然后在由形成图案的抗蚀层中的开口区域所暴露出的籽晶层上电解电镀上一层金属，例如铜。剥去形成图案的抗蚀层，并将籽晶层上未镀有金属层的部分蚀刻掉。对本领域的技术人员而言，其它形成此多个导电迹线142的方法是显而易见的。
如图11所示，在多个导电迹线142和第一介质层136上设置第二介质层144。可通过任何已知的工艺来形成第二介质层144，包括但不限于薄膜层合、旋涂、辊涂和喷射沉积。
如图12所示，随后形成穿过第二介质层144的多个第二通孔146。可通过本领域中已知的任何方法来形成多个第二通孔146，包括但不限于激光打孔，并且如果第二介质层144是光敏的话，则可通过本领域中已知的与在光刻工艺中制造光致抗蚀掩膜相同的方式来形成多个第二通孔146。
如果多个导电迹线142无法使多个第二通孔146放入合适的位置，则在此多个第二通孔146内和第二介质层144上形成导电迹线的其它部分，在第二介质层144上形成另一介质层，并在此介质层上例如如图10-12所述地形成另一些多个通孔。重复介质层的成层和导电迹线的形成，直到通孔处于合适的位置为止，这样就建立了足够的电连接性，可得到所需的电性能。因此，单个导电迹线的一些部分可从其多个部分中形成，并可位于不同的介质层上。
可形成第二多个导电迹线148，其中第二多个导电迹线148中的每一个的一部分延伸到至少一个所述多个第二通孔146中。各个第二多个导电迹线148均包括一个连接区150(由虚线152表示的迹线上的扩大区域)，如图13所示。
一旦形成第二多个导电迹线148和连接区150，就可采用它们来形成与外部元件(未示出)相连的导电互连构件，例如焊接块、焊球、引脚等。例如，可在第二介质层144和第二多个导电迹线154以及连接区150上设置焊接掩膜材料156。随后在焊接掩膜材料156上形成多个通孔158，从而暴露出各连接区150的至少一部分，如图14所示。如果需要的话，例如可通过但不限于在各连接区150的暴露部分上丝网印刷焊膏并随后进行回流焊接工艺或其它已知的涂镀技术，从而形成多个导电凸起160如焊接块，如图15所示。
图16显示了用密封材料122密封在微电子衬底核心102内的多个微电子管芯114，以形成本发明的微电子衬底170。在微电子管芯的有效面116、微电子衬底核心的第一表面106和密封材料表面124上以上述方式形成至少一个互连层。在图16中，构成互连层的介质材料和导电迹线层被简单地一起表示为互连层162。此互连层162不仅用于形成微电子管芯114和多个导电凸起160之间的连接，如上所述，而且允许在位于微电子衬底核心102内的微电子管芯114之间形成电连通。
一旦形成互连层162，就通过导电凸起160在互连层162的顶面166上连接至少一个微电子器件164。导电凸起160在至少一个微电子器件164和至少一个微电子管芯114之间形成了电连通。当然应当理解，导电凸起160可形成于互连层162上(如图15所示)，或形成于微电子器件164上。还可以理解，虽然图16显示了如封装的倒装片的微电子器件164，然而微电子器件可以是任何已知的有源或无源微电子器件164，包括但不限于逻辑部件(CPU)、存储器(DRAM，SRAM，SDRAM等)、控制器(芯片组)、电容器、电阻器和电感器，等等。
此外，除倒装片连接外，如图16所示，微电子器件164的连接可通过其它方法来完成，例如引线结合法或本领域的技术人员已知的其它方法。
图17显示了图16所示的组件，其中微电子衬底180制造成没有微电子衬底核心102(如图16所示)。封装材料122邻接于多个微电子管芯114中的两个相邻微电子管芯114之间。微电子衬底180以用于微电子衬底170(如图16所示)所述的相似方式来制造。
如图18所示，微电子管芯114和微电子器件164可具有多种大小和形状。此外，如图19所示，可在微电子衬底核心102的一个开口中设置多个微电子管芯114。这种结构允许使微电子管芯114相互作用，以便尽可能近地相互连通，从而通过缩短导电迹线(未示出)长度来提高电性能，这是本领域的技术人员所能理解的。
通过上述对本发明实施例的详细介绍，应当理解，由所附权利要求定义的本发明并不限于上述的特定细节，在不脱离本发明的精神实质或范围的前提下，可对本发明进行多种明显的变动。

Claims (19)

1.一种微电子衬底，包括：
具有第一表面和相对的第二表面的微电子衬底核心，所述微电子衬底核心具有至少一个形成于其中的开口，其从所述微电子衬底核心的第一表面延伸到所述微电子衬底核心的第二表面；
至少一个设置在所述至少一个开口内的微电子管芯，所述至少一个微电子管芯具有有效面；
将所述微电子衬底核心与所述至少一个微电子管芯相连的密封材料；
设于所述核心、管芯和密封材料中的至少一个之上的第一介质层，所述第一介质层包括多个第一通孔；
设于所述第一介质层之上的第一多个导电迹线；
设于所述第一介质层和所述第一多个导电迹线之上的第二介质层，其包括多个第二通孔；
设于所述第二介质层之上的第二多个导电迹线；
设于所述第二多个导电迹线之上的多个导电凸起，其中所述第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，
所述微电子衬底还包括至少两个与所述多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
2.根据权利要求1所述的微电子衬底，其特征在于，所述密封材料还包括至少一个与所述微电子管芯的有效面和所述微电子衬底核心的第一表面大致成一平面的表面。
3.根据权利要求1所述的微电子衬底，其特征在于，所述微电子衬底还包括至少一个与所述互连层相连的微电子器件。
4.根据权利要求1所述的微电子衬底，其特征在于，所述微电子衬底核心从包括有双马来酰亚胺三嗪树脂的层合材料、FR4层合材料、聚酰亚胺层合材料、陶瓷和金属的组中选择。
5.根据权利要求1所述的微电子衬底，其特征在于，各所述第二多个导电迹线包括连接区。
6.一种微电子衬底，包括：
具有第一表面和相对的第二表面的核心，所述核心具有至少一个形成于其中的开口，其从所述核心的第一表面延伸到所述核心的第二表面；
至少两个设置在所述至少一个开口内的管芯，各所述至少两个管芯均具有有效面；
将所述核心与所述至少两个管芯相连的密封材料；
设于所述核心、所述至少两个管芯和密封材料中的至少一个之上的第一介质层，所述第一介质层包括多个第一通孔；
设于所述第一介质层之上的第一多个导电迹线；
设于所述第一介质层和所述第一多个导电迹线之上的第二介质层，其包括多个第二通孔；和
设于所述第二介质层之上的第二多个导电迹线，其中所述第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，
设于所述第二多个导电迹线之上的多个导电凸起，
所述微电子衬底还包括至少两个与多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
7.根据权利要求6所述的微电子衬底，其特征在于，所述密封材料还包括至少一个与各所述多个微电子管芯的有效面大致成一平面的表面。
8.根据权利要求6所述的微电子衬底，其特征在于，所述微电子衬底还包括至少一个与所述互连层相连的微电子器件。
9.根据权利要求6所述的微电子衬底，其特征在于，各所述第二多个导电迹线包括连接区。
10.一种制造微电子衬底的方法，包括：
提供具有第一表面和相对的第二表面的微电子衬底核心，所述微电子衬底核心具有至少一个形成于其中的开口，其从所述微电子衬底核心的第一表面延伸到所述微电子衬底核心的第二表面；
将至少一个微电子管芯设置在所述至少一个开口内，所述至少一个微电子管芯具有有效面；
用密封材料将所述微电子衬底核心与所述至少一个微电子管芯相连；
提供包括多个第一通孔的第一介质层；
提供设于第一介质层之上的第一多个导电迹线；
提供第二介质层，其包括设于所述第一介质层和所述第一多个导电迹线之上的多个第二通孔；
提供设于所述第二介质层之上的第二多个导电迹线；
提供设于所述第二多个导电迹线之上的多个导电凸起，其中所述第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，
所述微电子衬底还包括至少两个与所述多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
11.根据权利要求10所述的方法，其特征在于，用所述密封材料将所述微电子衬底核心与所述至少一个微电子管芯相连还包括形成至少一个密封材料的表面，其与所述微电子管芯的有效面和所述微电子衬底核心的第一表面大致成一平面。
12.根据权利要求11所述的方法，其特征在于，所述方法还包括将至少一个微电子器件与所述互连层的顶面电连接。
13.根据权利要求10所述的方法，其特征在于，所述提供所述微电子衬底核心包括提供从包括有双马来酰亚胺三嗪树脂的层合材料、FR4层合材料、聚酰亚胺层合材料、陶瓷和金属的组中选出的微电子衬底核心。
14.根据权利要求10所述的方法，其特征在于，所述方法还包括在用密封材料将所述微电子衬底核心与所述至少一个微电子管芯相连之前使所述微电子衬底核心的第一表面和所述微电子管芯的有效面与保护膜相邻接。
15.根据权利要求14所述的方法，其特征在于，使所述微电子衬底核心的第一表面和所述微电子管芯的有效面与保护膜相邻接包括在用密封材料将所述微电子衬底核心与所述至少一个微电子管芯相连之前使所述微电子衬底核心的第一表面和所述微电子管芯的有效面与所述保护膜上的粘合层相邻接。
16.一种制造微电子衬底的方法，包括：
提供保护膜；
使多个微电子管芯的有效面与所述保护膜相邻接；
将密封材料至少放置在各所述多个微电子管芯之间；
除去所述保护膜；
提供包括多个第一通孔的第一介质层；
提供设于第一介质层之上的第一多个导电迹线；
提供第二介质层，其包括设于所述第一介质层和所述第一多个导电迹线之上的多个第二通孔；
提供设于所述第二介质层之上的第二多个导电迹线；
提供设于所述第二多个导电迹线之上的多个导电凸起，其中所述第一介质层、第一多个导电迹线、第二介质层和第二多个导电迹线构成互连层，
所述微电子衬底还包括至少两个与所述多个导电凸起相连的微电子器件，所述至少两个微电子器件包括多种形状和尺寸。
17.根据权利要求16所述的方法，其特征在于，放置所述密封材料包括形成与所述微电子管芯的有效面大致成一平面的至少一个密封材料的表面。
18.根据权利要求16所述的方法，其特征在于，所述方法还包括将至少一个微电子器件电连接到所述互连层的顶面上。
19.根据权利要求16所述的方法，其特征在于，提供所述保护膜包括提供具有粘合剂的所述保护膜；使所述多个微电子管芯的有效面与所述保护膜相邻接包括使所述多个微电子管芯的有效面与所述保护膜的所述粘合剂相邻接。
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