CN100397644C - 半导体设备的电容器和使用同样电容器的存储器设备 - Google Patents

半导体设备的电容器和使用同样电容器的存储器设备 Download PDF

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CN100397644C
CN100397644C CNB2004100903048A CN200410090304A CN100397644C CN 100397644 C CN100397644 C CN 100397644C CN B2004100903048 A CNB2004100903048 A CN B2004100903048A CN 200410090304 A CN200410090304 A CN 200410090304A CN 100397644 C CN100397644 C CN 100397644C
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dielectric layer
band gap
layer
capacitor
lower electrode
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CN1617337A (zh
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李正贤
徐范锡
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种半导体设备的电容器以及包括同样电容器的存储器设备。电容器包括下部电极、具有多个带隙并且形成于下部电极上的介电层、以及上部电极。介电层包括具有第一带隙并且形成于下部电极上的第一介电层、具有第二带隙并且形成于第一介电层上的第二介电层、以及具有第三带隙并且形成于第二介电层上的第三介电层。并且第一至第三带隙满足：第二带隙＜第一带隙＜第三带隙。在另一实施例中，第一至第三带隙满足：第二带隙＜第三带隙＜第一带隙。

Description

半导体设备的电容器和使用同样电容器的存储器设备
技术领域
本发明涉及半导体设备，具体而言涉及半导体设备的电容器以及使用同样电容器的存储器设备。
背景技术
一种例如存储器设备的半导体设备包括晶体管和电容器。电容器应当长时间将数据保持在正常状态。为此，电容器具有大于某个值的电容。
由于增加了存储器设备的集成化程度，所以减少了形成电容器的区域。然而，电容器的电容应当增加或者至少不减少。
根据这一情况，对于能够被应用到高集成化的存储器设备上的电容器的研究已经取得了进步。在该研究中，使用了使介电层变薄的方法、利用铁电物质的方法，以及组合使用这两种方法的方法。
图1是根据现有技术的半导体设备所包含的电容器的横截面图。
参见图1，传统的电容器包括下部电极10、氧化铪层12以及上部电极14。
由于增加了存储器设备的集成化程度，所以增加了传统的电容器的漏电流。
也就是说，用作介电层的氧化铪层12最好尽可能薄。然而，随着氧化铪层12变薄，例如大约4.5nm厚，电容器的漏电流显著地增加。因此，包括传统电容器的存储器设备不能正常工作。
图2是根据氧化铪层12的厚度表示图1中电容器的漏电流密度的曲线图。
参见图2，第一和第二曲线G1和G2表示当氧化铪层12远远厚于4.5nm时的漏电流的特性，同时第三和第四曲线G3和G4表示当氧化铪层12的厚度大约是4.5nm时的漏电流的特性。而且，第一和第三曲线G1和G3给出当将氧化铪层12沉积为比目标厚度薄的厚度时的漏电流密度。此外，第二和第四曲线G2和G4给出当将氧化铪层12沉积为目标厚度时的漏电流密度。将第一和第二曲线G1和G2与第三和第四曲线G3和G4相比，当氧化铪层12的厚度大约为4.5nm时，电容器的漏电流显著地增加了。
可以使用具有多种组成的铁电层，例如STO(SrTio3)层代替氧化铪层12。当电容器具有类似图3中的电容器的复杂结构时，铁电层M3中阳离子的比率发生变化，并且降低了电容器的电特性。参见图4，第五曲线G5表示铁电层M3例如STO层中Sr比Ti的比率，其中以在图3中电容器中的多个点1...9测量该STO层。
根据第五曲线G5，虽然，在铁电层M3的顶面Sr的含量远远多于Ti的含量。然而，在铁电层M3的下面，Ti的含量少于Sr的含量。
在图3的电容器中没有示出上部电极。在图3中，参考标记M1指示二氧化硅(SiO2)层，并且参考标记M2指示下部电极。
发明内容
为了解决以上和其它问题，本发明提供了半导体设备的电容器，其包括纳米级的厚度的介电层，并具有大电容以及极好的漏电流特性，还提供了使用该电容器的存储器设备。
本发明还提供具有该电容器的半导体存储器设备。
根据本发明的一个方面，提供了一种半导体设备的电容器，其包括：下部电极；介电层，它具有多个带隙；以及上部电极。
具体地，介电层包括：第一介电层，具有第一带隙，并且被形成于下部电极上；第二介电层，具有第二带隙，并且被形成于第一介电层上；以及第三介电层，具有第三带隙，并且被形成于第二介电层上。
第一至第三介电层可满足以下条件中的至少一个：
ii)第二带隙<第一带隙<第三带隙
iii)第二带隙<第三带隙<第一带隙
此外，在第一和第二介电层之间还包括介电层，该介电层具有位于第一和第二带隙之间的带隙。同样，在第二和第三介电层之间还包括介电层，该介电层具有位于第二和第三带隙之间的带隙。
根据本发明的另一方面，提供了存储器设备，包括：晶体管；以及被连接到晶体管的电容器，其中电容器包括：被连接到晶体管的下部电极；介电层，具有多个带隙，被形成于下部电极上；以及上部电极，被形成于介电层上。
具体地，介电层包括：第一介电层，具有第一带隙，并且被形成于下部电极上；第二介电层，具有第二带隙，并且被形成于第一介电层上；以及第三介电层，具有第三带隙，并且被形成于第二介电层上。
第一至第三介电层可满足以下条件中的至少一个：
ii)第二带隙<第一带隙<第三带隙
iii)第二带隙<第三带隙<第一带隙
因此，利用以上的本发明，可以实现包括纳米厚的介电层以及具有大电容和低于传统电容器的漏电流的电容器。也能够实现高可靠性的存储器设备。
附图说明
通过参照附图详细描述本发明的示例性实施例，本发明的以上和其它特征和优点将变得更加明显，其中：
图1是半导体设备中所包含的传统电容器的横截面图；
图2是表示根据图1中电容器所包含的氧化铪层的厚度与图1中电容器的漏电流密度关系的曲线图；
图3是具有铁电层但结构复杂的传统电容器的横截面图；
图4是在图3电容器中的多个点处所测量的图3铁电层中所包含的原子的比的曲线图；
图5是根据本发明实施例的半导体设备的电容器的横截面；
图6是表示图5中电容器的漏电流密度的曲线图，其中在层积介电层之前测量该电容器漏电流密度；
图7是表示在层积介电层之后，图5中电容器的漏电流密度的曲线图；以及
图8是根据本发明的实施例，包括图5中半导体设备的电容器的存储器设备的横截面图。
具体实施方式
现在将参照附图更全面地描述本发明，其中给出了其示例性实施例。然而，本发明可以以许多不同的形式实施，并且不应当被解释为是限定在此所述的实施例；相反，提供这些实施例，以便此处的公开将是完全且彻底的，并且将本发明的原理充分地传达给本领域技术人员。在图中，为了清楚起见，放大了元件的形状。为便于理解，在全部附图中，对于同样的元件使用同一参考标号。
图5是根据本发明的半导体设备的电容器的横截面图。
参见图5，根据本发明的电容器包括下部电极40和上部电极50，上部电极50面对着下部电极40。
下部电极40最好是其中掺杂了导电杂质的Si层。但是，也可以使用其它导电层例如TiN层。上部电极50最好是TiN层。但是，也可以使用其它导电层例如其中掺杂了导电杂质的Si层。介电层DL位于下部电极40和上部电极50之间。
通过顺序地沉积具有不同带隙，由此具有不同的介电常量的介电层形成介电层DL，。
具体地，通过顺序地形成三层不同的介电层而形成介电层DL。即，在下部电极40上形成第一介电层42，在第一介电层42上形成第二介电层44，以及在第二介电层44上形成第三介电层46。第一介电层42具有第一带隙，第二介电层44具有第二带隙，以及第三介电层46具有第三带隙。第二带隙最好小于第一带隙和第三带隙。第一和第三带隙相等就更好。
如果第一至第三介电层42、44和46具有以上的带隙分布，则电子穿过具有大带隙的介电层例如第三介电层46就遇到具有小带隙的介电层、即第二介电层44，并且使得声子散射。因此，电子不能穿过与第二介电层44相邻的带隙，也就是第一介电层42。
结果，减少了介电层DL的漏电流。不是由于第一至第三介电层42、44和46的厚度的关系，而是由于形成介电层DL的第一至第三介电层42、44和46之间的带隙关系导致漏电流的减少。因此，即使第一至第三介电层42、44和46的厚度变薄，也能够极好地保持介电层DL的漏电流特性。因此，形成了厚度薄的介电层DL。例如，可以使第一至第三介电层42、44和46的厚度形成为2nm～10nm。
最好是，第一至第三介电层42、44和46具有在2nm～10nm范围内的相同的厚度。
最好是，第一和第三介电层42和46中每一个都是从一个组中选出的，该组是由氧化铪层(HfO2)、氧化铝层(Al2O3)以及氧化镨层(Pr2O3)组成的。最好是，第二介电层44是氧化钛层(TiO2)，但也可以是从以下组中选出的，该组是由氧化钽(Ta2O5)层、STO(SrTiO3)层、BTO(BaTiO3)层、PTO(PbTiO3)层、TNO((Ta，Nb)2O5)层、以及TWO((Ta，W)2O5)组成的。
现在将描述测试根据本发明实施例的电容器的漏电流特性的优越性的实验。
在第一实验中，分别用LaO层、TiO2层和LaO层形成第一至第三介电层42、44和46。在第二实验中，分别用HfO层、TiO2层和HfO层形成第一至第三介电层42、44和46。所形成的第一至第三介电层42、44和46的整个厚度大约是纳米厚。
图6和7是表示以上实验的结果的曲线图。
图6表示在将第一至第三介电层42、44和46层积到目标厚度之前测量的，例如在只层积了第一介电层42之后测量的第一漏电流密度。图7表示在将第一至第三介电层42、44和46完全形成目标厚度之后图5中的电容器的第二漏电流密度。
参见图6和7，第六和第八曲线G6和G8表示在水平放置的衬底的一个位置上所测量的漏电流密度，并且，第七和第九曲线G7和G9表示在衬底的另一个位置上所测量的漏电流密度。
该一个位置可以是接近衬底的平坦区域的一个地点，而另一个位置可以是在与平坦区域相对一侧的另一个地点。
从图6的曲线图与图7的曲线图的比较中可以看出，第二漏电流密度远远小于第一漏电流密度。
还有，当图2中的第三和第四曲线G3和G4与图7中的第八和第九曲线G8和G9相比较时，当提供了预定电压例如±1V时，传统电容器的漏电流密度大约为0.01A/cm2，但根据本发明实施例的电容器的漏电流密度的范围是在1E-7A/cm2和1E-6A/cm2之间。
因此，根据本发明实施例的电容器的漏电流密度远远低于传统电容器的漏电流密度，并且因此，根据本发明实施例的电容器的电容远远大于传统电容器的电容。
同时，通过将第一至第三介电层42、44和46顺序地层积在下部电极40上，然后在第三介电层46上层积上部电极50，可以形成图5的电容器。可以在2nm至10nm的厚度范围内形成第一至第三介电层42、44和46。
此外，还可以使用化学气相沉积(CVD)方法形成第一至第三介电层42、44和46。考虑到形成的第一至第三介电层42、44和46的厚度是纳米级，最好通过原子层沉积(ALD)形成第一至第三介电层42、44和46。
下面将描述包括图5中的电容器的存储器设备。
图8是一存储器设备的剖面图，该存储器设备包括本发明实施例图5中的半导体设备的电容器。
参见图8，存储器设备包括衬底70。衬底70包括第一和第二区域74和76，在这些区域中掺入了杂质，并且上述两个区域以预定的距离被分开。第一区域74是源极区，而第二区域76是漏极区。沟道区位于衬底70中第一和第二区域74和76之间，并且在沟道区上形成栅层积材料72。栅层积材料72根据所施加的电压使沟道区导通或截止。栅层积材料72包括栅绝缘层(未示出)和栅导电层(未示出)。衬底70、第一和第二区域74和76以及栅层积材料72构成金属氧化物半导体场效应晶体管(MOSFET)。在衬底70上形成覆盖栅层积材料72的第一夹层绝缘层78，并且在第一夹层绝缘层78中形成使第二区域露出的第一接触孔80。第一接触孔80用第一导电塞82，例如掺杂了杂质的多晶硅进行填塞。在第一夹层绝缘层78上形成覆盖第一导电塞82的电容器C。电容器C最好是图5中所示的电容器C。还有，最好是，电容器C的下部电极40和第一导电塞82最好用相同的导电材料形成，然而，也可以使用不同的导电材料。在第一夹层绝缘层78上形成覆盖电容器C的第二夹层绝缘层84。在第一和第二夹层绝缘层78和84中形成使第一区域74的一部分露出的第二接触孔86。第二接触孔86用第二导电塞88填塞。最好是，第二导电塞86是掺杂了导电杂质的多晶硅，但也可以是其它导电材料。在第二夹层绝缘层84上形成覆盖第二导电塞88的导电层90。导电层90是位线，并且垂直于栅层积材料72。最好是，导电层90和第二导电塞88用相同的导电材料形成，但也可以使用不同的导电材料。
在根据本发明的存储器设备中，被存储在电容器中的数据能够长时间保持正常状态。即，这就意味着，即使当存储了数据并且过了很长时间之后读取数据时，被存储在电容器中的数据也能正常地被读出，并且因此增强了存储器设备的可靠性。
如上所述，根据本发明实施例的电容器的介电层包括具有不同带隙的多个介电层。与其它介电层相比，当穿过具有大带隙的介电层的电子到达具有较小带隙的介电层时，这些电子能够声子散射。因此，电子不能穿过紧邻具有小带隙的介电层放置的具有大带隙的介电层。因此，即使电容器的介电层具有纳米级的厚度，也不会增加电容器的漏电流。此外，介电层的厚度是具有纳米级的厚度。因此，极大地增强了电容器的电容。
虽然此处给出了详细的说明，但是本发明可以以许多不同的形式来实施，并且不应当认为其被限定为此处所阐述的实施例范围；相反，提供前述优选实施例，以便此处的公开将是完全且彻底的，并且将本发明的原理充分地传述给本领域技术人员。例如，第一和第三介电层42和46可以用具有不同带隙但大于第二介电层44的带隙的介电层代替。还有，在第一和第三介电层42和46之间可以包括多个第二介电层44。同样，在该多个第二介电层44中还可以包括具有与第一或第三介电层的带隙相同的带隙的另一个介电层。此外，在该多个第二介电层44之间还可以包括具有比第二介电层44的带隙小的另一个介电层。这种电容器也可以被用在除了图8中的存储器设备之外的其它存储器设备中。
尽管已经参照本发明的示例性实施例具体示出并描述了本发明，但是本领域技术人员应该理解，在不脱离如后附的权利要求书所规定的本发明的精神和范围的情况下，可以在不同形式和细节方面进行许多改变。

Claims (16)

1.一种半导体设备的电容器，该电容器包括：
下部电极；
在下部电极上形成的介电层，具有多个带隙；以及
形成于介电层上的上部电极，
其中介电层包括第一介电层、第二介电层和第三介电层，第一介电层具有第一带隙并且形成于下部电极上，第二介电层具有第二带隙并且形成于第一介电层上以及第三介电层具有第三带隙并形成于第二介电层上，并且
第一至第三带隙满足：第二带隙＜第一带隙＜第三带隙。
2.一种半导体设备的电容器，该电容器包括：
下部电极；
在下部电极上形成的介电层，具有多个带隙；以及
形成于介电层上的上部电极，
其中介电层包括第一介电层、第二介电层和第三介电层，第一介电层具有第一带隙并且形成于下部电极上，第二介电层具有第二带隙并且形成于第一介电层上以及第三介电层具有第三带隙并形成于第二介电层上，并且
第一至第三带隙满足：第二带隙＜第三带隙＜第一带隙。
3.根据权利要求1或2的电容器，其中还在第一和第二介电层之间提供具有带隙在第一和第二带隙之间的介电层。
4.根据权利要求1或2的电容器，其中还在第二和第三介电层之间提供具有带隙在第二和第三带隙之间的介电层。
5.根据权利要求1或2的电容器，其中第一介电层是从由HfO2层、Al2O3层、La2O3层和Pr2O3层组成的组中选出的一层。
6.根据权利要求1或2的电容器，其中该第二介电层是从由TiO2层、Ta2O5层、SrTiO3层、BaTiO3层、PbTiO3层、(Ta，Nb)2O5层、以及(Ta，W)2O5层组成的组中选出的一层。
7.根据权利要求1或2的电容器，其中第三介电层是从由HfO2层、Al2O3层、La2O3层和Pr2O3层组成的组中选出的一层。
8.根据权利要求3的电容器，其中在第二和第三介电层之间还提供具有带隙在第二和第三带隙之间的介电层。
9.一种半导体设备的存储器设备，包括：
晶体管；以及
被连接到晶体管的电容器，其中电容器包括：
连接到晶体管的下部电极，
介电层，具有多个带隙并且形成于下部电极上，以及
形成于介电层上的上部电极，
其中介电层包括第一介电层、第二介电层和第三介电层，第一介电层具有第一带隙并且形成于下部电极上，第二介电层具有第二带隙并且形成于第一介电层上以及第三介电层具有第三带隙并形成于第二介电层上，并且
第一至第三带隙满足：第二带隙＜第一带隙＜第三带隙。
10.一种半导体设备的存储器设备，包括：
晶体管；以及
被连接到晶体管的电容器，其中电容器包括：
连接到晶体管的下部电极，
介电层，具有多个带隙并且形成于下部电极上，以及
形成于介电层上的上部电极，
其中介电层包括第一介电层、第二介电层和第三介电层，第一介电层具有第一带隙并且形成于下部电极上，第二介电层具有第二带隙并且形成于第一介电层上以及第三介电层具有第三带隙并形成于第二介电层上，并且
第一至第三带隙满足：第二带隙＜第三带隙＜第一带隙。
11.根据权利要求9或10的存储器设备，其中还在第一和第二介电层之间提供具有带隙在第一和第二带隙之间的介电层。
12.根据权利要求9或10的存储器设备，其中还在第二和第三介电层之间提供具有带隙在第二和第三带隙之间的介电层。
13.根据权利要求9或10的存储器设备，其中第一介电层是从由HfO2层、Al2O3层、La2O3层和Pr2O3层组成的组中选出的一层。
14.根据权利要求9或10的存储器设备，其中该第二介电层是从由TiO2层、Ta2O5层、SrTiO3层、BaTiO3层、PbTiO3层、(Ta，Nb)2O5层、以及(Ta，W)2O5层组成的组中选出的一层。
15.根据权利要求9或10的存储器设备，其中第三介电层是从由HfO2层、Al2O3层、La2O3层和Pr2O3层组成的组中选出的一层。
16.根据权利要求11的存储器设备，其中在第二和第三介电层之间还提供具有带隙在第二和第三带隙之间的介电层。
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