CN100347854C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN100347854C CN100347854C CNB031082734A CN03108273A CN100347854C CN 100347854 C CN100347854 C CN 100347854C CN B031082734 A CNB031082734 A CN B031082734A CN 03108273 A CN03108273 A CN 03108273A CN 100347854 C CN100347854 C CN 100347854C
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- Prior art keywords
- film
- interlayer dielectric
- semiconductor device
- dielectric
- sioc
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims description 81
- 239000000126 substance Substances 0.000 claims description 80
- 239000011229 interlayer Substances 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 62
- 239000000203 mixture Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 2
- 150000001721 carbon Chemical class 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 93
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 93
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 238000004090 dissolution Methods 0.000 abstract 2
- 125000003277 amino group Chemical group 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
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- 229910010271 silicon carbide Inorganic materials 0.000 description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 26
- 239000010949 copper Substances 0.000 description 18
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- 230000004888 barrier function Effects 0.000 description 16
- 125000003368 amide group Chemical group 0.000 description 14
- 238000005530 etching Methods 0.000 description 14
- 229910052757 nitrogen Inorganic materials 0.000 description 13
- 239000002585 base Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000007789 gas Substances 0.000 description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910004283 SiO 4 Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 238000006386 neutralization reaction Methods 0.000 description 3
- 238000006555 catalytic reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002329 infrared spectrum Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H01L21/318—Inorganic layers composed of nitrides
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
Description
Claims (13)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002166897A JP2004014841A (ja) | 2002-06-07 | 2002-06-07 | 半導体装置及びその製造方法 |
JP166897/2002 | 2002-06-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1467840A CN1467840A (zh) | 2004-01-14 |
CN100347854C true CN100347854C (zh) | 2007-11-07 |
Family
ID=29706738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031082734A Expired - Fee Related CN100347854C (zh) | 2002-06-07 | 2003-03-27 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US20030227087A1 (zh) |
JP (1) | JP2004014841A (zh) |
KR (1) | KR20030095217A (zh) |
CN (1) | CN100347854C (zh) |
TW (1) | TW589712B (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030043724A (ko) * | 2001-11-27 | 2003-06-02 | 엔이씨 일렉트로닉스 코포레이션 | 반도체 장치 제조 방법 |
TW200428586A (en) * | 2003-04-08 | 2004-12-16 | Matsushita Electric Ind Co Ltd | Electronic device and the manufacturing method thereof |
US7915085B2 (en) * | 2003-09-18 | 2011-03-29 | Cree, Inc. | Molded chip fabrication method |
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
JP4491283B2 (ja) * | 2004-06-10 | 2010-06-30 | 信越化学工業株式会社 | 反射防止膜形成用組成物を用いたパターン形成方法 |
US9659769B1 (en) | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
US8454750B1 (en) | 2005-04-26 | 2013-06-04 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8980769B1 (en) | 2005-04-26 | 2015-03-17 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
JP4533304B2 (ja) | 2005-11-29 | 2010-09-01 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2007234719A (ja) * | 2006-02-28 | 2007-09-13 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US10037905B2 (en) | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
US8465991B2 (en) * | 2006-10-30 | 2013-06-18 | Novellus Systems, Inc. | Carbon containing low-k dielectric constant recovery using UV treatment |
TWI442186B (zh) * | 2007-03-28 | 2014-06-21 | Jsr Corp | 光阻底層膜用組成物及雙鑲嵌結構之形成方法 |
KR101275025B1 (ko) * | 2007-07-12 | 2013-06-14 | 삼성전자주식회사 | 반도체 소자용 배선 구조물 및 이의 형성방법 |
US8211510B1 (en) | 2007-08-31 | 2012-07-03 | Novellus Systems, Inc. | Cascaded cure approach to fabricate highly tensile silicon nitride films |
US9050623B1 (en) | 2008-09-12 | 2015-06-09 | Novellus Systems, Inc. | Progressive UV cure |
US8742587B1 (en) * | 2012-11-18 | 2014-06-03 | United Microelectronics Corp. | Metal interconnection structure |
FR3024587B1 (fr) * | 2014-08-01 | 2018-01-26 | Soitec | Procede de fabrication d'une structure hautement resistive |
CN107785246B (zh) * | 2016-08-30 | 2022-10-14 | 联芯集成电路制造(厦门)有限公司 | 对基底进行离子注入的方法 |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5916823A (en) * | 1998-10-13 | 1999-06-29 | Worldwide Semiconductor Manufacturing Corporation | Method for making dual damascene contact |
US5959361A (en) * | 1997-12-03 | 1999-09-28 | United Microelectronics Corp. | Dielectric pattern |
US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
US6350700B1 (en) * | 2000-06-28 | 2002-02-26 | Lsi Logic Corporation | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
CN1430274A (zh) * | 2002-01-02 | 2003-07-16 | 艾格瑞系统有限公司 | 用于隔离多孔低k介电薄膜的结构和方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6103456A (en) * | 1998-07-22 | 2000-08-15 | Siemens Aktiengesellschaft | Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication |
JP2000150516A (ja) * | 1998-09-02 | 2000-05-30 | Tokyo Electron Ltd | 半導体装置の製造方法 |
US6949203B2 (en) * | 1999-12-28 | 2005-09-27 | Applied Materials, Inc. | System level in-situ integrated dielectric etch process particularly useful for copper dual damascene |
US6541367B1 (en) * | 2000-01-18 | 2003-04-01 | Applied Materials, Inc. | Very low dielectric constant plasma-enhanced CVD films |
JP4377040B2 (ja) * | 2000-07-24 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体の製造方法 |
US6790789B2 (en) * | 2000-10-25 | 2004-09-14 | International Business Machines Corporation | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made |
US6441491B1 (en) * | 2000-10-25 | 2002-08-27 | International Business Machines Corporation | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same |
JP2002164428A (ja) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6583047B2 (en) * | 2000-12-26 | 2003-06-24 | Honeywell International, Inc. | Method for eliminating reaction between photoresist and OSG |
US20020132471A1 (en) * | 2001-03-16 | 2002-09-19 | International Business Machines Corporation | High modulus film structure for enhanced electromigration resistance |
US6486059B2 (en) * | 2001-04-19 | 2002-11-26 | Silicon Intergrated Systems Corp. | Dual damascene process using an oxide liner for a dielectric barrier layer |
KR100416596B1 (ko) * | 2001-05-10 | 2004-02-05 | 삼성전자주식회사 | 반도체 소자의 연결 배선 형성 방법 |
US6861347B2 (en) * | 2001-05-17 | 2005-03-01 | Samsung Electronics Co., Ltd. | Method for forming metal wiring layer of semiconductor device |
JP2002353307A (ja) * | 2001-05-25 | 2002-12-06 | Toshiba Corp | 半導体装置 |
US6879046B2 (en) * | 2001-06-28 | 2005-04-12 | Agere Systems Inc. | Split barrier layer including nitrogen-containing portion and oxygen-containing portion |
JP4160277B2 (ja) * | 2001-06-29 | 2008-10-01 | 株式会社東芝 | 半導体装置の製造方法 |
US6797605B2 (en) * | 2001-07-26 | 2004-09-28 | Chartered Semiconductor Manufacturing Ltd. | Method to improve adhesion of dielectric films in damascene interconnects |
JP3780189B2 (ja) * | 2001-09-25 | 2006-05-31 | 富士通株式会社 | 半導体装置の製造方法及び半導体装置 |
US6686273B2 (en) * | 2001-09-26 | 2004-02-03 | Sharp Laboratories Of America, Inc. | Method of fabricating copper interconnects with very low-k inter-level insulator |
US6623654B2 (en) * | 2001-11-09 | 2003-09-23 | Taiwan Semiconductor Manufacturing Company | Thin interface layer to improve copper etch stop |
KR100442867B1 (ko) * | 2001-12-07 | 2004-08-02 | 삼성전자주식회사 | 반도체 소자의 듀얼 다마신 구조 형성방법 |
US20030134499A1 (en) * | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US6806203B2 (en) * | 2002-03-18 | 2004-10-19 | Applied Materials Inc. | Method of forming a dual damascene structure using an amorphous silicon hard mask |
US6660627B2 (en) * | 2002-03-25 | 2003-12-09 | United Microelectronics Corp. | Method for planarization of wafers with high selectivities |
US6764774B2 (en) * | 2002-06-19 | 2004-07-20 | International Business Machines Corporation | Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same |
US6770570B2 (en) * | 2002-11-15 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
-
2002
- 2002-06-07 JP JP2002166897A patent/JP2004014841A/ja active Pending
-
2003
- 2003-03-12 US US10/385,729 patent/US20030227087A1/en not_active Abandoned
- 2003-03-13 TW TW092105502A patent/TW589712B/zh not_active IP Right Cessation
- 2003-03-27 CN CNB031082734A patent/CN100347854C/zh not_active Expired - Fee Related
- 2003-03-28 KR KR10-2003-0019555A patent/KR20030095217A/ko not_active Application Discontinuation
-
2008
- 2008-10-23 US US12/289,227 patent/US20090149031A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5959361A (en) * | 1997-12-03 | 1999-09-28 | United Microelectronics Corp. | Dielectric pattern |
US5916823A (en) * | 1998-10-13 | 1999-06-29 | Worldwide Semiconductor Manufacturing Corporation | Method for making dual damascene contact |
US6350700B1 (en) * | 2000-06-28 | 2002-02-26 | Lsi Logic Corporation | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
CN1430274A (zh) * | 2002-01-02 | 2003-07-16 | 艾格瑞系统有限公司 | 用于隔离多孔低k介电薄膜的结构和方法 |
Also Published As
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TW200308053A (en) | 2003-12-16 |
TW589712B (en) | 2004-06-01 |
US20090149031A1 (en) | 2009-06-11 |
JP2004014841A (ja) | 2004-01-15 |
KR20030095217A (ko) | 2003-12-18 |
US20030227087A1 (en) | 2003-12-11 |
CN1467840A (zh) | 2004-01-14 |
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