AU2009325425B2 - Method for manufacturing composite substrate on which wide bandgap semiconductor is laminated - Google Patents

Method for manufacturing composite substrate on which wide bandgap semiconductor is laminated Download PDF

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Publication number
AU2009325425B2
AU2009325425B2 AU2009325425A AU2009325425A AU2009325425B2 AU 2009325425 B2 AU2009325425 B2 AU 2009325425B2 AU 2009325425 A AU2009325425 A AU 2009325425A AU 2009325425 A AU2009325425 A AU 2009325425A AU 2009325425 B2 AU2009325425 B2 AU 2009325425B2
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AU
Australia
Prior art keywords
substrate
wide bandgap
ion
visible light
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU2009325425A
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English (en)
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AU2009325425A1 (en
Inventor
Shoji Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of AU2009325425A1 publication Critical patent/AU2009325425A1/en
Application granted granted Critical
Publication of AU2009325425B2 publication Critical patent/AU2009325425B2/en
Ceased legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AU2009325425A 2008-12-11 2009-12-10 Method for manufacturing composite substrate on which wide bandgap semiconductor is laminated Ceased AU2009325425B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2008-315566 2008-12-11
JP2008315566 2008-12-11
JP2009-278561 2009-12-08
JP2009278561A JP5389627B2 (ja) 2008-12-11 2009-12-08 ワイドバンドギャップ半導体を積層した複合基板の製造方法
PCT/JP2009/070656 WO2010067835A1 (ja) 2008-12-11 2009-12-10 ワイドバンドギャップ半導体を積層した複合基板の製造方法

Publications (2)

Publication Number Publication Date
AU2009325425A1 AU2009325425A1 (en) 2010-06-17
AU2009325425B2 true AU2009325425B2 (en) 2014-10-02

Family

ID=42242822

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2009325425A Ceased AU2009325425B2 (en) 2008-12-11 2009-12-10 Method for manufacturing composite substrate on which wide bandgap semiconductor is laminated

Country Status (8)

Country Link
US (1) US8546245B2 (enExample)
EP (1) EP2357660B1 (enExample)
JP (1) JP5389627B2 (enExample)
KR (1) KR101607725B1 (enExample)
CN (1) CN102246267B (enExample)
AU (1) AU2009325425B2 (enExample)
TW (1) TWI482198B (enExample)
WO (1) WO2010067835A1 (enExample)

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FR2961719B1 (fr) * 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
JP5884585B2 (ja) * 2012-03-21 2016-03-15 住友電気工業株式会社 炭化珪素半導体装置の製造方法
CN103703542B (zh) * 2012-07-18 2016-06-08 日本碍子株式会社 复合晶片及其制造方法
JP6160617B2 (ja) 2012-07-25 2017-07-12 信越化学工業株式会社 ハイブリッド基板の製造方法及びハイブリッド基板
CN104871431B (zh) * 2012-12-26 2018-04-10 日本碍子株式会社 复合基板及其制造方法，以及弹性波装置
WO2014192597A1 (ja) * 2013-05-31 2014-12-04 日本碍子株式会社 複合基板用支持基板および複合基板
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396852B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396854B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396853B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6632462B2 (ja) * 2016-04-28 2020-01-22 信越化学工業株式会社 複合ウェーハの製造方法
JP6387375B2 (ja) 2016-07-19 2018-09-05 株式会社サイコックス 半導体基板
CN107785235A (zh) * 2016-08-31 2018-03-09 沈阳硅基科技有限公司 一种在基板上制造薄膜的方法
RU2699606C1 (ru) * 2016-11-28 2019-09-06 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Способ ионно-лучевого синтеза нитрида галлия в кремнии
CN107326435A (zh) * 2017-07-28 2017-11-07 西安交通大学 一种生长GaN的SiC衬底的剥离方法
US10510532B1 (en) * 2018-05-29 2019-12-17 Industry-University Cooperation Foundation Hanyang University Method for manufacturing gallium nitride substrate using the multi ion implantation
KR101969679B1 (ko) * 2018-07-27 2019-04-16 한양대학교 산학협력단 Soi 웨이퍼와 열처리 공정을 이용한 박막 형성 및 전사 방법
EP4044212B1 (en) * 2019-11-14 2024-02-14 Huawei Digital Power Technologies Co., Ltd. Semiconductor substrate, manufacturing method therefor, and semiconductor device
CN111883651A (zh) * 2020-07-23 2020-11-03 奥趋光电技术(杭州)有限公司 一种制备高质量氮化铝模板的方法
US20250059676A1 (en) 2021-12-21 2025-02-20 Shin-Etsu Handotai Co., Ltd. Nitride semiconductor substrate and method for producing nitride semiconductor substrate
CN117476831B (zh) * 2023-12-20 2024-03-19 青禾晶元(晋城)半导体材料有限公司 Led外延片及其制备方法、led芯片及其制备方法
US20250254943A1 (en) * 2024-02-02 2025-08-07 Wolfspeed, Inc. Power Semiconductor Devices with Stacked Layers
DE102024203093A1 (de) * 2024-04-04 2025-10-09 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen einer Driftzone mit p-dotierten Bereichen eines Superjunction-Leistungshalbleiterbauelements und ein Superjunction-Leistungshalbleiterbauelement

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JP2005252244A (ja) * 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法
JP2008277552A (ja) * 2007-04-27 2008-11-13 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法

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JP3655547B2 (ja) 2000-05-10 2005-06-02 株式会社イオン工学研究所 半導体薄膜の形成方法
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
JP2003347176A (ja) * 2002-03-20 2003-12-05 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
EP1482548B1 (en) * 2003-05-26 2016-04-13 Soitec A method of manufacturing a wafer
JP5358159B2 (ja) 2004-02-03 2013-12-04 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
WO2006082467A1 (en) * 2005-02-01 2006-08-10 S.O.I.Tec Silicon On Insulator Technologies Substrate for crystal growing a nitride semiconductor
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Publication number Priority date Publication date Assignee Title
JP2004140266A (ja) * 2002-10-18 2004-05-13 Ishikawajima Harima Heavy Ind Co Ltd 薄膜層ウェハ製造方法、及び薄膜層ウェハ
JP2005252244A (ja) * 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法
JP2008277552A (ja) * 2007-04-27 2008-11-13 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法

Also Published As

Publication number Publication date
US8546245B2 (en) 2013-10-01
EP2357660B1 (en) 2014-09-03
KR20110099008A (ko) 2011-09-05
JP2010161355A (ja) 2010-07-22
KR101607725B1 (ko) 2016-03-30
AU2009325425A1 (en) 2010-06-17
EP2357660A1 (en) 2011-08-17
JP5389627B2 (ja) 2014-01-15
EP2357660A4 (en) 2012-06-20
CN102246267A (zh) 2011-11-16
TW201104726A (en) 2011-02-01
CN102246267B (zh) 2016-04-27
US20110227068A1 (en) 2011-09-22
WO2010067835A1 (ja) 2010-06-17
TWI482198B (zh) 2015-04-21

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MK14 Patent ceased section 143(a) (annual fees not paid) or expired