WO2024082395A1 - 晶体管、3d存储器及其制造方法、电子设备 - Google Patents

晶体管、3d存储器及其制造方法、电子设备 Download PDF

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Publication number
WO2024082395A1
WO2024082395A1 PCT/CN2022/137325 CN2022137325W WO2024082395A1 WO 2024082395 A1 WO2024082395 A1 WO 2024082395A1 CN 2022137325 W CN2022137325 W CN 2022137325W WO 2024082395 A1 WO2024082395 A1 WO 2024082395A1
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substrate
layer
gate
memory according
layers
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PCT/CN2022/137325
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English (en)
French (fr)
Inventor
戴瑾
余泳
梁静
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北京超弦存储器研究院
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Priority to US18/304,219 priority Critical patent/US20240130106A1/en
Publication of WO2024082395A1 publication Critical patent/WO2024082395A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the embodiments of the present disclosure relate to but are not limited to the field of semiconductor technology, and in particular to a transistor, a 3D memory and a manufacturing method thereof, and an electronic device.
  • 3D memory has received more and more attention, and has certain advantages in improving the density of memory.
  • IGZO indium gallium zinc oxide
  • the metal oxide semiconductor transistor can be used in the 3D stacking structure of memory cells.
  • the embodiment of the present disclosure provides a 3D memory, comprising: a plurality of memory cells stacked in a direction perpendicular to a substrate, and a word line, wherein the word line extends in a direction perpendicular to the substrate and passes through the memory cells in different layers;
  • the storage unit includes: a transistor, the transistor includes a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer located on the side wall of the gate and insulated from the gate; wherein the semiconductor layer includes a source contact region and a drain contact region arranged at intervals, and the channel between the source contact region and the drain contact region is a horizontal channel.
  • the semiconductor layer surrounds a sidewall of the gate.
  • the source electrodes of transistors in different layers are spaced apart from each other, and the drain electrodes of transistors in different layers are spaced apart from each other.
  • the gates of transistors at different layers are part of the word line, and the semiconductor layers corresponding to the transistors at different layers are located on the sidewalls of the word line.
  • the source electrode of the same transistor is a source electrode film layer
  • the drain electrode is a drain electrode film layer
  • the drain electrode film layer and the source electrode film layer are located in the same layer and are spaced apart.
  • the source electrode film layers or the drain electrode film layers of different transistors are located in different film layers.
  • orthographic projections of the source electrode and the drain electrode of the same transistor do not overlap;
  • orthographic projections of source electrodes and drain electrodes of different transistors have no overlap.
  • the source electrode is located on a first side of the gate
  • the drain electrode is located on a second side of the gate
  • the source electrode and the drain electrode are arranged to face each other.
  • semiconductor layers of the transistors of the memory cells at different layers are spaced apart in a direction perpendicular to the substrate.
  • an insulating layer is exposed between the spaced apart semiconductor layers, and the insulating layer is a gate insulating layer located between the gate and the semiconductor layer.
  • every two adjacent semiconductor layers in the memory cells of different layers are connected to form an integrated structure.
  • An embodiment of the present disclosure provides a vertical transistor for a 3D memory, comprising: a substrate, a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer that fully or partially surrounds the gate and is insulated from the gate; wherein the semiconductor layer comprises a source contact region and a drain contact region that are spaced apart, and a channel between the source contact region and the drain contact region is a horizontal channel.
  • the film layer of the source electrode and the film layer of the drain electrode are different regions of the same conductive film layer and are arranged at intervals, and the same conductive film layer is approximately parallel to the substrate.
  • the material of the semiconductor layer includes a metal oxide semiconductor material.
  • an orthographic projection of the source electrode and an orthographic projection of the drain electrode do not overlap.
  • the source contact region is located on a first side of the semiconductor layer
  • the drain contact region is located on a second side of the semiconductor layer
  • the source electrode contacts the source contact region
  • the drain electrode contacts the drain contact region
  • the source electrode and the drain electrode are arranged facing each other.
  • the semiconductor layer is a ring-shaped fully surrounding semiconductor layer.
  • the embodiment of the present disclosure provides a method for manufacturing a 3D memory, wherein the 3D memory includes a plurality of memory cells stacked in a direction perpendicular to a substrate, and a word line;
  • the memory cell comprises: a transistor, wherein the transistor comprises a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate; the manufacturing method of the 3D memory comprises:
  • each of the stacked structures comprises a stack of insulating layers and conductive layers alternately arranged in a direction perpendicular to the substrate, each of the conductive layers corresponds to a transistor in a layer of the memory cell, and each of the conductive layers comprises a first sub-portion and a second sub-portion connected to each other;
  • a semiconductor film is filled on the sidewall of the through hole to form a semiconductor layer of each of the transistors, wherein the semiconductor layer is in contact with each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode in the same transistor is a horizontal channel;
  • a gate insulating layer and a metal film are sequentially deposited in the through hole, the metal film fills the through hole in the gate insulating layer to form the word line, and the gates of the transistors at different layers are part of the word line.
  • An embodiment of the present disclosure provides an electronic device, comprising the 3D memory described in any of the above embodiments, or comprising the vertical transistor for the 3D memory described in any of the above embodiments.
  • FIG1 is a schematic diagram of a transistor provided by an exemplary embodiment
  • FIG2 is a cross-sectional view of the transistor shown in FIG1 along the AA direction;
  • FIG3 is a schematic diagram of an exemplary embodiment after forming a second insulating film
  • FIG4 is a schematic diagram of an exemplary embodiment after a groove is formed
  • FIG5 is a schematic diagram of an exemplary embodiment after the slot is filled
  • FIG6 is a schematic diagram of an exemplary embodiment after forming a through hole
  • FIG7A is a schematic diagram of an exemplary embodiment after a channel is formed
  • FIG. 7B is a schematic diagram of a first metal layer provided by an exemplary embodiment
  • FIG8A is a schematic diagram of an exemplary embodiment after forming an active layer and a first gate insulating layer
  • FIG8B is a partial schematic diagram of FIG8A ;
  • FIG8C is a schematic cross-sectional view of FIG8B along the BB direction
  • FIG9A is a schematic diagram of an exemplary embodiment after forming a second metal layer
  • FIG9B is a partial schematic diagram of FIG9A ;
  • FIG9C is a schematic cross-sectional view of FIG9B along the BB direction;
  • FIG10A is a schematic diagram of an exemplary embodiment after removing the second metal layer in the through hole
  • FIG10B is a partial schematic diagram of FIG10A ;
  • FIG10C is a schematic cross-sectional view of FIG10B along the BB direction;
  • FIG. 11A is a schematic diagram of an exemplary embodiment after a gate is formed
  • FIG11B is a partial schematic diagram of FIG11A ;
  • FIG11C is a schematic cross-sectional view of FIG11B along the BB direction;
  • FIG11D is a schematic cross-sectional view of a source electrode, a drain electrode, and a gate provided by an exemplary embodiment
  • FIG12 is a schematic diagram of an exemplary embodiment after forming a second insulating film
  • FIG13 is a schematic diagram of an exemplary embodiment after a groove is formed
  • FIG14 is a schematic diagram of an exemplary embodiment after the slot is filled
  • FIG15 is a schematic diagram of an exemplary embodiment after forming a through hole
  • FIG16 is a schematic diagram of an exemplary embodiment after forming a gate
  • FIG17A is a schematic diagram of a semiconductor device provided by an exemplary embodiment
  • FIG17B is a partial schematic diagram of FIG17A
  • FIG18 is a flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment
  • FIG. 19 is a flow chart of a method for manufacturing a semiconductor device according to another exemplary embodiment.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the situation where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function includes the situation where components are connected together through an element having some kind of electrical function.
  • electrical function includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • FIG1 is a schematic cross-sectional view of a transistor in a memory cell array provided by an exemplary embodiment.
  • FIG2 is a cross-sectional view of the transistor shown in FIG1 in the AA direction.
  • this embodiment provides a transistor, which may include: a substrate 1, a source electrode 51, a drain electrode 52 and a gate 11 extending along a first direction Z arranged on the substrate 1, and a semiconductor layer 9 surrounding the gate 11 and insulated from the gate 11, for example, a gate insulating layer 10 surrounding the gate 11 and a semiconductor layer 9 surrounding the gate insulating layer 10.
  • the substrate is a base that plays a supporting role. Its material and internal structure are not the focus of this application, so this application will not describe them in detail.
  • the source electrode 51 , the drain electrode 52 and the gate 11 extending along the first direction Z on the substrate 1 may be understood as the source electrode 51 , the drain electrode 52 and the gate 11 extending along the first direction Z arranged above the substrate.
  • the gate 11 extending along the first direction Z can be understood as a gate extending in a direction perpendicular to the substrate, and as a whole only extends along the substrate direction, but the morphology of the side surface of the gate is not specifically limited.
  • the cross-sectional shape and size of the gate can be similar, or the cross-sectional shape and size are different in different regions.
  • the functions of the source electrode 51 and the drain electrode 52 can be interchanged.
  • the source electrode 51 in FIG. 1 is a drain electrode in other embodiments
  • the drain electrode 52 in FIG. 1 is a source electrode in other embodiments.
  • the gate extends in a direction perpendicular to the substrate, wherein the gate includes a side surface and end faces at the upper and lower ends, the side surface is perpendicular to the substrate as a whole, or in other words, the partial area of the side wall corresponding to the semiconductor layer that plays a gate control role, the film layer in this area is perpendicular to the substrate.
  • the two opposite main surfaces have a larger surface area than the end surfaces.
  • the semiconductor layer 9 extends along the side wall of the gate, the film layer thickness direction is parallel to the substrate direction, the length of the film layer extending up and down the side wall of the gate is the height of the film layer, and the length surrounding the gate is the width of the film layer.
  • surrounding can be understood as partially or completely surrounding the gate.
  • the surrounding can be completely surrounded as a whole, and the cross section of the semiconductor layer after surrounding is annular.
  • the interception direction of the cross section is intercepted along the direction parallel to the substrate.
  • the surrounding can be partially surrounded, and the cross section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening.
  • the semiconductor layer 9 may include a source contact region 91 and a drain contact region 92 that are spaced apart, the source electrode 51 is in contact with the source contact region 91, the drain electrode 52 is in contact with the drain contact region 92, the source electrode 51 and the drain electrode 52 are insulated from the gate 11 by the gate insulating layer 10, and the channel between the source contact region 91 and the drain contact region 92 is a horizontal channel, that is, the transmission direction of the carriers in the channel is parallel to the upper surface of the substrate 1 (that is, the surface facing the side of the gate 11).
  • the length direction of the channel is parallel to the substrate 1.
  • the channel has a carrier transmission direction, which is the length direction of the channel, and the direction perpendicular to the length direction is the width direction of the channel.
  • the first direction Z may be perpendicular to the substrate 1.
  • the source contact region 91 and the drain contact region 92 are spaced apart from each other and are not directly connected. In some embodiments, they may be spaced apart in a direction parallel to the substrate 1. In the direction perpendicular to the substrate 1, the center positions of the source contact region 91 and the drain contact region 92 may be in the same plane or offset from each other by a certain distance. However, it is necessary to ensure that the channel direction as a whole is not perpendicular to the substrate but tends to be horizontal.
  • the semiconductor layer 9 is only located on the side wall of the gate 11.
  • a hole extending along the substrate direction is formed in the insulating layer
  • the semiconductor layer is located on the hole wall, and extends in a direction perpendicular to the substrate to form a hole-like structure
  • the gate is formed in the hole according to the shape of the hole and is insulated from the gate by the gate insulating layer.
  • the gate can be a solid structure or a hollow structure.
  • the semiconductor layer 9 may extend on the sidewall of the gate 11 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1.
  • the semiconductor layer 9 surrounds the gate 11 but does not contact the gate 11.
  • the outer sidewall of the gate 11 is surrounded by a gate insulating layer 10, and the semiconductor layer 9 surrounds the gate insulating layer 10.
  • the semiconductor layer 9 may be a full-surrounding type or a partially-surrounding type. For example, in a direction perpendicular to the substrate 1, the semiconductor layer 9 may have a gap.
  • the source contact region 91 and the drain contact region 92 on the semiconductor layer 9 are determined according to the source electrode and the drain electrode, and the source electrode 51 and the drain electrode 52 are provided and the regions in contact with the semiconductor layer are the source contact region 91 and the drain contact region 92, respectively.
  • the positions of the source contact region 91 and the drain contact region 92 make the transmission direction of the carriers in the channel not in the vertical direction but in the horizontal direction.
  • the channel direction between the source electrode 51 and the drain electrode 52 generally extends in a direction parallel to the substrate 1.
  • the gate 11 of each stacked transistor can be connected as a word line connected to each transistor of the 3D stack.
  • the word line extending in the vertical direction saves space and can form the gate and word line of each transistor in one process, thereby reducing the number of masks, effectively simplifying the process, and reducing costs.
  • Each source electrode 51 is correspondingly provided with an independent source contact region
  • each drain electrode 52 is correspondingly provided with a drain contact region.
  • the word line may extend in a straight line or in a curved line in the vertical direction.
  • the gate 11 extending in the vertical direction of each transistor may be a straight line, and the orthographic projection on the substrate 1 may be at the same position, so that the gates of each transistor are connected to form a straight word line.
  • the curve may not be straight as a whole, but the gate in the corresponding semiconductor region or the effective semiconductor region is a straight line extending in a direction perpendicular to the substrate, and the word line portion between two adjacent layers may not be a straight line.
  • the cross section of the linear word line along the direction parallel to the substrate 1 may be the same everywhere, or may be different.
  • the embodiment of the present application does not limit the cross section characteristics of the straight line.
  • the gate 11 extending in the vertical direction of each transistor can be a straight line, and the orthographic projection on the substrate 1 can be in different positions. After the gate 11 of each transistor is connected, it forms a whole extending in a direction vertical to the substrate 1 but is partially curved.
  • a horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction.
  • the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer.
  • a horizontal channel does not mean that it must extend in a straight line in the horizontal plane, and may extend in different directions.
  • the semiconductor layer 9 is annular
  • the source contact area 91 and the drain contact area 92 on the annular semiconductor layer are part of the ring. At this time, the carriers extend from the source contact area 91 to the drain contact area 92 in one direction as a whole, and may not be in a certain direction locally.
  • the carrier transmission direction in a plane parallel to the substrate 1 is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate.
  • the present application protects the channel between the source electrode 51 and the drain electrode 52 as a channel that is not perpendicular to the substrate 1.
  • the gate of each transistor is a vertical gate and the channel is a horizontal channel, which is convenient for realizing a 3D stacked memory with a simple structure and relatively easy manufacturing.
  • the orthographic projection of the source electrode 51 and the orthographic projection of the drain electrode 52 may not overlap, which ensures that the channel is a horizontal channel.
  • orthographic projections of the source contact region 91 and the drain contact region 92 on a plane perpendicular to the substrate 1 may overlap, wherein the plane is located between the source contact region 91 and the drain contact region 92 .
  • the semiconductor layer 9 may be a fully surrounding type, fully surrounding the side wall of the gate 11, that is, in the area corresponding to the gate 11, the cross section of the semiconductor layer 9 is a closed loop.
  • the semiconductor layer 9 is annular, and in the cross section at each position of the gate 11, the semiconductor layer 9 is annular, and the annular shape is adapted to the outer contour of the cross section of the gate 11.
  • the outer contour of the cross section of the gate 11 may be a circular, elliptical, square or other structure.
  • a first distance between the surface of the source electrode 51 close to the substrate 1 and the substrate 1, and a second distance between the surface of the drain electrode 52 close to the substrate 1 and the substrate 1 may be the same. That is, the source electrode 51 and the drain electrode 52 are at the same distance from the substrate 1.
  • the embodiments of the present disclosure are not limited thereto, and the first distance and the second distance may be different.
  • the source electrode 51 and the drain electrode 52 are located in different regions of the same metal film layer and are spaced apart, and are formed by patterning a metal film layer, and the metal film layer is approximately parallel to the upper surface of the substrate 1.
  • the source electrode 51 and the drain electrode 52 respectively have two upper and lower main surfaces and side surfaces, the side surfaces are in contact with the semiconductor layer 9, and the shape of the side surfaces is adapted to the shape of the side walls of the semiconductor layer 9.
  • the first thickness of the source electrode 51 and the second thickness of the drain electrode 52 may be the same.
  • the embodiments of the present disclosure are not limited thereto, and the first thickness and the second thickness may be different.
  • the source electrode 51 and the drain electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate 1. It can be understood that the source electrode 51 and the drain electrode 52 are located in the same metal film layer, formed by patterning a metal film layer, and the metal film layer is approximately parallel to the upper surface of the substrate 1.
  • the orthographic projection of the gate 11 may be located outside the orthographic projection of the source electrode 51, and the orthographic projection of the gate 11 may be located outside the orthographic projection of the drain electrode 52.
  • the solution provided in this embodiment can realize a plurality of transistors with a simple structure and relatively easy manufacturing, and the gate 11 of each transistor is connected to form a word line.
  • the semiconductor layer 9 may be a metal oxide semiconductor layer, or a semiconductor layer containing silicon.
  • the metal in the metal oxide semiconductor layer may include at least one of indium, tin, zinc, aluminum, and gallium, but is not limited to the listed material embodiments.
  • the metal oxide semiconductor layer may include: at least one of indium oxide, tin oxide, indium zinc (In-Zn) type oxide, tin zinc (Sn-Zn) type oxide, aluminum zinc (Al-Zn) type oxide, indium gallium (In-Ga) type oxide, indium gallium zinc (In-Ga-Zn) type oxide, indium aluminum zinc (In-Al-Zn) type oxide, indium tin zinc (In-Sn-Zn) type oxide, tin gallium zinc (Sn-Ga-Zn) type oxide, aluminum gallium zinc (Al-Ga-Zn) type oxide, and tin aluminum zinc (Sn-Al-Zn) type oxide.
  • the cross section of the gate 11 may be rectangular, and the side surface has four side surfaces, and each two side surfaces face each other (such as the first side and the second side face each other).
  • the source electrode 51 may be located on the first side of the gate 11, and the drain electrode 52 may be located on the second side of the gate 11, and the source electrode 51 and the drain electrode 52 may be arranged facing each other. That is, the first side and the second side are opposite sides.
  • the embodiments of the present disclosure are not limited thereto, and the source electrode 51 and the drain electrode 52 may be located at other positions.
  • the source electrode 51 when the transistor is placed in an array, the source electrode 51 may extend along a second direction X, and the drain electrode 52 may extend along a third direction Y, the second direction X may be parallel to the substrate 1, and the third direction Y may be parallel to the substrate 1.
  • the embodiments of the present disclosure are not limited thereto, and the source electrode 51 and the drain electrode 52 may be in other shapes. It can be understood that the source electrode 51 is integrally provided with the lead, and the drain electrode 52 is integrally provided with the lead.
  • the lead integrally provided with the source electrode 51 extends in the row direction in a horizontal plane
  • the lead integrally provided with the drain electrode 52 extends in the column direction.
  • the second direction X and the third direction Y may intersect.
  • the second direction X and the third direction Y may be perpendicular to each other, but the embodiments of the present disclosure are not limited thereto, and the second direction X and the third direction Y may be at other angles.
  • the cross-section of the source electrode 51 may be square, circular, elliptical, etc.
  • the cross-section of the drain electrode 52 may be square, circular, elliptical, etc.
  • the embodiments of the present disclosure are not limited thereto, and the cross-section of the source electrode 51 and the cross-section of the drain electrode 52 may be other shapes, such as circular, hexagonal, etc.
  • the source electrode 51 and the drain electrode 52 can be connected at other positions different from the positions shown in Figure 1.
  • the source electrode 51 is connected to the first side of the annular column formed by the semiconductor layer 9, and the drain electrode 52 is connected to the second side of the annular column formed by the semiconductor layer 9, and the first side and the second side are adjacent, and so on.
  • the source electrode 51 and the drain electrode 52 may be disposed in the same layer. That is, the source electrode 51 and the drain electrode 52 may be formed simultaneously by the same patterning process, but the embodiment of the present disclosure is not limited thereto, and the source electrode 51 and the drain electrode 52 may be manufactured separately by different patterning processes.
  • the source electrode 51 and the drain electrode 52 described in the embodiment of the present application only refer to the first electrode and the second electrode of a transistor excluding the gate, one of which is the source electrode and the other is the drain electrode.
  • the identification of the source or drain electrode in the product is determined according to the direction of the current flow.
  • the source electrode described in the embodiment of the present application may be interpreted as the drain electrode according to the direction of the current flow.
  • the size of the channel between the source electrode 51 and the drain electrode 52 can be controlled by the overlapping length between the orthographic projection of the source electrode 51 and the orthographic projection of the drain electrode 52 on the plane perpendicular to the substrate 1.
  • the overlapping length between the orthographic projection of the source electrode 51 and the orthographic projection of the drain electrode 52 is d, and the channel size can be controlled by controlling the thickness of the source electrode 51 and the drain electrode 52 along the direction perpendicular to the substrate 1.
  • the channel size is controlled by changing the size of the through hole where the gate is located (the process needs to be changed) or increasing the distance between the source electrode and the drain electrode (which will cause the volume of the transistor to increase).
  • This embodiment can more conveniently control the size of the channel, with small process changes and less impact on the size of the transistor.
  • transistor structures shown in Figures 1 and 2 are simplified schematic diagrams. In the actual manufactured transistor, other film layers may also be included, such as an insulating layer located between the substrate 1 and the source electrode 51 and the drain electrode 52, and an insulating layer covering the source electrode 51 and the drain electrode 52.
  • the technical solution of this embodiment is explained below through the manufacturing process of the transistor of this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies.
  • the "photolithography process” mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, atomic layer deposition, etc.
  • coating can adopt known coating processes
  • etching can adopt known methods, which are not limited here.
  • thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film” does not require a patterning process or a photolithography process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the “thin film” also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a “thin film” before the patterning process and a "layer” after the patterning process. The "layer” after the patterning process or the photolithography process contains at least one "pattern".
  • a manufacturing process of a transistor may include:
  • a first insulating film, a first metal film, and a second insulating film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4, respectively, as shown in FIG. 3 .
  • the substrate 1 can be made of glass, silicon, flexible materials, etc.
  • the flexible material can be made of polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film.
  • the substrate 1 can be a single-layer structure or a multi-layer stacked structure.
  • the stacked structure substrate can include: flexible material/inorganic material/flexible material.
  • the inorganic material can be any one or more of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON).
  • the first insulating film and the second insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9.
  • they may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • the first insulating film and the second insulating film may be made of the same material or different materials.
  • the first metal film may include but is not limited to at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum (Ta), etc.
  • the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a first slot P1 and a second slot P2, as shown in FIG4.
  • the first slot P1 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the second slot P2 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4.
  • the first metal layer 3 may include a first sub-portion 31 extending along the second direction X and a second sub-portion 32 extending along the third direction Y.
  • the cross-sections of the first insulating layer 2, the first metal layer 3 and the second insulating layer 4 may be H-shaped on a plane parallel to the substrate 1.
  • the first metal layer 3 may include a second sub-portion 32 and a third sub-portion 33 opposite to each other, and a first sub-portion 31 connecting the second sub-portion 32 and the third sub-portion 33.
  • first slot P1 and the second slot P2 may have the same size and shape, but the embodiments of the present disclosure are not limited thereto, and the first slot P1 and the second slot P2 may have different sizes and shapes.
  • the third sub-portion 33 may extend along the third direction Y.
  • the embodiments of the present disclosure are not limited thereto, and the third sub-portion 33 may be in other shapes.
  • the third sub-portion 33 may be removed.
  • the pattern of the first metal layer 3 is only an example, and the first metal layer 3 may be a pattern of other shapes.
  • the current second sub-portion 32 is divided into two parts along the extension direction of the first sub-portion 31, and only one of the parts may be retained as the second sub-portion 32.
  • a third insulating film is deposited to form a third insulating layer 5 , and the third insulating layer 5 fills the first groove P1 and the second groove P2 , as shown in FIG. 5 .
  • the third insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • the third insulating film and the first insulating film and the second insulating film may be made of the same material or different materials.
  • a through hole 41 penetrating the first insulating layer 2, the first metal layer 3 and the second insulating layer 4 is formed, and on a plane parallel to the substrate 1, the orthographic projection of the through hole 41 may overlap with the orthographic projection of the first sub-portion 31, and overlap with the orthographic projection of the second sub-portion 32, as shown in FIG6.
  • the cross-section of the through hole 41 shown in FIG6 on a plane parallel to the substrate 1 is a quadrilateral, but the embodiments of the present disclosure are not limited thereto, and the cross-section of the through hole 41 on a plane parallel to the substrate 1 may be other shapes, such as a circle, a pentagon, a hexagon, etc.
  • the first sub-portion 31, the second sub-portion 32, and the connection between the third sub-portion 33 and the first sub-portion 31 in the first metal layer 3 are selectively etched.
  • the third sub-portion 33 remains in the first metal layer 3, and the third sub-portion 33 is provided with a third groove P3 facing the first sub-portion 31 (the first sub-portion 31 has been etched away), as shown in FIGS. 7A and 7B.
  • a first semiconductor film and a first gate oxide film are sequentially deposited to form an active layer 6 and a first gate insulating layer 7, respectively, as shown in FIGS. 8A, 8B, and 8C, wherein FIG. 8C is a cross-sectional view of FIG. 8B along the BB direction, and only shows the active layer 6 and the first gate insulating layer 7.
  • the active layer 6 and the first gate insulating layer 7 serve as the channel walls of the channel, and the active layer 6 surrounds the first gate insulating layer 7.
  • the first gate oxide film may be a High-K dielectric material.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, and hafnium oxide.
  • the first semiconductor film as a channel layer may be a film layer containing silicon, or a metal oxide semiconductor, wherein the metal oxide semiconductor includes but is not limited to at least one of the following materials: IGZO, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO).
  • ITO Indium Tin Oxide
  • IZO indium zinc oxide
  • the subsequent second semiconductor film is similar and will not be repeated.
  • the first semiconductor film and the first gate oxide film may be deposited by an atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • FIG. 9C is a cross-sectional view of FIG. 9B along the BB direction, and only shows the active layer 6, the first gate insulating layer 7, and the second metal layer 8. At this time, the first gate insulating layer 7 surrounds the second metal layer 8.
  • the second metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the second metal film may be the same as or different from the first metal film.
  • FIG. 10C is a cross-sectional view of Figure 10B along the BB direction, and only shows the active layer 6, the first gate insulating layer 7 and the second metal layer 8.
  • the second metal layer 8 located in the first channel 42 serves as the source electrode 51 of the transistor
  • the second metal layer 8 located in the second channel 43 serves as the drain electrode 52 of the transistor, and the source electrode 51 and the drain electrode 52 are disconnected from each other.
  • FIG. 11C is a cross-sectional view of Figure 11B along the BB direction, and only shows the active layer 6, the first gate insulating layer 7, the semiconductor layer 9, the gate insulating layer 10, the second metal layer 8 (source electrode 51, drain electrode 52), and the gate 11.
  • the second gate oxide film may be a High-K dielectric material.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, and hafnium oxide.
  • the third metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the third metal film may be the same as or different from the first metal film and the second metal film.
  • the transistor manufactured by the above manufacturing method may further include a first gate insulating layer 7 surrounding the source electrode 51 and the drain electrode 52, and an active layer 6 surrounding the first gate insulating layer 7 (the side of the source electrode 51 and the drain electrode 52 away from the gate 11 is sequentially covered with the first gate insulating layer 7 and the active layer 6, as shown in FIG11D).
  • the active layer 6 and the first gate insulating layer 7 may be etched away, which is not limited in the embodiment of the present disclosure.
  • a patterning process can be used to form an H-shaped first metal layer 3.
  • a second insulating film is deposited to form a second insulating layer 4, and there is no need to form the first groove P1 and the second groove P2 by groove formation, and there is no need to deposit a third insulating film.
  • the present disclosure also provides an electronic device, including the transistor described in any of the above embodiments.
  • the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include a memory in a computer, etc., which is not limited here.
  • the manufacturing process of the transistor may include:
  • a first insulating film, a first metal film, and a second insulating film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4, respectively, as shown in FIG. 12 .
  • the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a third slot P3 and a fourth slot P4, as shown in FIG13.
  • the third slot P3 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the fourth slot P4 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4.
  • the first metal layer 3 may include a first sub-portion 31 extending along the second direction X and a second sub-portion 32 extending along the third direction Y.
  • the third slot P3 and the fourth slot P4 may have the same size and shape, but the embodiments of the present disclosure are not limited thereto, and the third slot P3 and the fourth slot P4 may have different sizes and shapes.
  • the pattern of the first metal layer 3 is only an example, and the first metal layer 3 may be a pattern of other shapes.
  • the current second sub-portion 32 is divided into two parts along the extension direction of the first sub-portion 31, and only one of the parts may be retained as the second sub-portion 32.
  • a third insulating film is deposited to form a third insulating layer 5 , and the third insulating layer 5 fills the third groove P3 and the fourth groove P4 , as shown in FIG. 14 .
  • the third insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • the third insulating film and the first insulating film and the second insulating film may be made of the same material or different materials.
  • a through hole 41 penetrating the first insulating layer 2, the first metal layer 3 and the second insulating layer 4 is etched, and on a plane parallel to the substrate 1, the orthographic projection of the through hole 41 may overlap with the orthographic projection of the first sub-portion 31, and the orthographic projection of the through hole 41 may overlap with the orthographic projection of the second sub-portion 32, as shown in FIG15.
  • the first sub-portion 31 and the second sub-portion 32 are etched, one of them forms a drain electrode, and the other forms a source electrode.
  • the cross-section of the through hole 41 shown in FIG15 on a plane parallel to the substrate 1 is a quadrilateral, but the embodiments of the present disclosure are not limited thereto, and the cross-section of the through hole 41 on a plane parallel to the substrate 1 may be other shapes, such as a circle, a pentagon, a hexagon, and the like.
  • a second semiconductor film, a second gate oxide film and a third metal film are sequentially deposited on the sidewalls of the through hole 41 to form a semiconductor layer 9, a gate insulating layer 10 and a gate 11, respectively, and the gate insulating layer 10 surrounds the gate 11, the semiconductor layer 9 surrounds the gate insulating layer 10, and the gate 11 completely fills the area surrounded by the gate insulating layer 10.
  • the semiconductor layer 9 is the semiconductor layer of the transistor
  • the gate insulating layer 10 is the gate insulating layer of the transistor
  • the gate 11 is the gate of the transistor, as shown in FIG16 .
  • the second gate oxide film may be a High-K dielectric material.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, and hafnium oxide.
  • the third metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the third metal film may be the same as or different from the first metal film.
  • insulating films and metal films are alternately stacked, so that a plurality of transistors sharing the semiconductor layer 9, the gate insulating layer 10 and the gate electrode 11 can be manufactured.
  • the above transistors can be used in 3D memory.
  • a column stacking structure can be formed in the vertical direction according to the above transistors.
  • the column stacking structure can be a stack of transistors in a 1T1C memory cell, or can be a stack of one of the transistors in a 2T0C or 2T1C structure.
  • a 3D memory which may include: a plurality of memory cells stacked in a direction perpendicular to a substrate, a word line, wherein the word line extends in a direction perpendicular to the substrate and passes through the memory cells in different layers;
  • the memory cell may include: a transistor, wherein the transistor may include a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate and insulated from the gate; wherein the semiconductor layer may include a source contact region and a drain contact region spaced apart, and a channel between the source contact region and the drain contact region is a horizontal channel.
  • the source electrodes of transistors in different layers may be arranged at intervals, and the drain electrodes of transistors in different layers may be arranged at intervals.
  • the gates of transistors at different layers are part of the word lines.
  • FIG. 17A and FIG. 17B transistor stacking in a two-layer stacked memory cell is shown.
  • the embodiment of the present disclosure provides a 3D memory, which may include:
  • a plurality of memory cells (only transistors are shown in the figure, but capacitors are not shown) stacked in a direction perpendicular to the substrate 1, a word line 110 (the word line 110 includes a gate 11), wherein:
  • the memory cell may include: a transistor, the transistor may include a source electrode 51 (FIGS. 17A and 17B are three-dimensional structures, not cross-sectional views, and the source electrode 51 cannot be shown inside, so the source electrode 51 is not shown in the drawings, please refer to FIG. 2, FIG. 11A to FIG.
  • the semiconductor layer 9 may include a source contact region and a drain contact region arranged at intervals, the source electrode 51 contacts the source contact region, and the drain electrode 52 contacts the drain contact region; the channel between the source contact region and the drain contact region is a horizontal channel;
  • the word line 110 extends in a direction perpendicular to the substrate 1 and passes through the memory cells at different layers.
  • the semiconductor layer 9 may surround the sidewall of the gate 11.
  • the sidewall of the gate extends only in a direction perpendicular to the substrate, and the semiconductor layer as a whole extends only in a direction perpendicular to the substrate.
  • the area where there may be local bending is also included in the above-mentioned situation of the present application.
  • the source electrodes 51 of transistors in different layers may be spaced apart, and the drain electrodes 52 of transistors in different layers may be spaced apart.
  • the spaced apart arrangement may be understood as having no connection relationship between them and being separated from each other by an insulating layer in position, but it does not mean that the source electrodes or drain electrodes of different layers are coupled in other areas.
  • the gates 11 of the transistors of different layers may be part of the word line 110, and the semiconductor layers 9 corresponding to the transistors of different layers are located on the sidewalls of the word line 110.
  • This design can form the word lines and gates of the storage cells of different layers at one time in terms of process, significantly reducing the cost.
  • the gates 11 of transistors at different layers are connected to form the word line 110. It can be understood that the word line only extends along the vertical direction without a branch structure extending on the sidewall.
  • the word line 110 extending in a direction perpendicular to the substrate 1 may be a straight line.
  • the material composition of different regions of the word line extending in a direction perpendicular to the substrate 1 is the same, which can be understood as being formed using the same film manufacturing process.
  • the same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.
  • the cross-sectional shapes of the word lines 110 extending in a direction perpendicular to the substrate 1 are approximately the same, which can be understood as using a process to form a hole, the hole is a longitudinal hole, and the word line is filled in the hole formed with a channel and a gate insulating layer.
  • the cross-sectional shapes of the holes are approximately the same and the sizes are approximately similar.
  • the word lines correspond to regions of different layers, and the cross-sectional shapes are all annular, specifically all square, all elliptical, or other shapes, which are not limited in this application.
  • the semiconductor layers 9 corresponding to transistors of different layers are located on the sidewalls of the word line 110 and are respectively located in different regions extending in a direction perpendicular to the substrate 1 .
  • the source electrode 51 and the drain electrode 52 of the same transistor may be located in the same conductive film layer, and the source electrode 51 or the drain electrode 52 of different transistors may be located in different conductive film layers.
  • the source electrode of the same transistor is a source electrode film layer
  • the drain electrode is a drain electrode film layer
  • the drain electrode film layer and the source electrode film layer are located in the same layer and are spaced apart.
  • the source electrode and the drain electrode of a transistor are formed by patterning a conductive film layer, so it can be understood that the drain electrode film layer and the source electrode film layer are located in the same layer, and in actual products, the cross section is on the same horizontal plane and the material is the same.
  • the source electrode film layer or the drain electrode film layer of different transistors is located in different film layers, reflecting the 3D stacking structure of different transistors.
  • a multi-layer stacked source electrode and drain electrode can be formed by the relative stacking of the conductive layer and the insulating layer and then by a mask, so that the process is simple.
  • the conductive film layer may be parallel to the substrate 1 .
  • orthographic projections of the source contact region and the drain contact region on a plane perpendicular to the substrate 1 overlap.
  • an orthographic projection of the source electrode 51 and an orthographic projection of the drain electrode 52 of the same transistor do not overlap.
  • orthographic projections of the source electrode 51 and the drain electrode 52 of different transistors do not overlap.
  • the source electrode 51 may be located at a first side of the gate 11
  • the drain electrode 52 may be located at a second side of the gate 12
  • the source electrode 51 and the drain electrode 52 may be disposed facing each other.
  • the semiconductor layers 9 of the transistors of the memory cells of different layers may be spaced apart in a direction perpendicular to the substrate 1.
  • the solution provided in this embodiment can prevent leakage of electricity between transistors of different layers through the semiconductor layer 9, thereby reducing power consumption.
  • an isolation layer is provided between the semiconductor layers 9 that are spaced apart from each other.
  • the isolation layer may be an insulating layer obtained by doping the semiconductor layer 9 .
  • a gate insulating layer 10 surrounding the word line 110 is disposed on a sidewall of the word line 110 , and the semiconductor layers 9 of the transistors at different layers may be continuously distributed on the sidewall of the word line 110 .
  • an insulating layer may be exposed between the spaced semiconductor layers 9 , and the insulating layer may be a gate insulating layer 10 located between the gate electrode 11 and the semiconductor layer 9 .
  • every two adjacent semiconductor layers 9 in the storage units of different layers may be connected to form an integrated structure.
  • stacked transistors in different layers may share a word line 110 extending in a direction perpendicular to the substrate 1 .
  • transistors in different layers may share a ring-shaped gate insulating layer 10 extending in a direction perpendicular to the substrate 1.
  • the gate insulating layer 10 of the multi-layer transistors may be formed through a single manufacturing process, simplifying the process and reducing costs.
  • transistors in different layers may share a ring-shaped semiconductor layer 9 extending in a direction perpendicular to the substrate 1.
  • semiconductor layers 9 of multiple layers of transistors may be formed through a single manufacturing process, thereby simplifying the process and reducing costs.
  • the semiconductor layer 9 may be a metal oxide semiconductor layer, or the semiconductor layer 9 may be a semiconductor layer containing silicon.
  • the projections of the source electrodes 51 of different layers on the substrate 1 may be located in the same area, the projections of the drain electrodes 52 of different layers on the substrate 1 may be located in the same area; the projections of the gate electrodes 11 of different layers on the substrate 1 may be located in the same area.
  • the orthographic projections of the source electrodes 51, the drain electrodes 52, and the gate electrodes 11 of different layers are located in the same area, which can make the 3D memory structure compact, and in addition, the manufacturing process can be simplified, and there is no need to separately pattern the source electrodes 51 and the drain electrodes 52 of each layer.
  • the structure of a single transistor in the above 3D memory may refer to the structures of transistors in the above-mentioned multiple embodiments, which will not be described in detail here.
  • the gate of the transistor is a vertical gate, and the channel is a horizontal channel, which is convenient for realizing a 3D stacked memory with a simple structure and relatively easy manufacturing, and has a high 3D integration.
  • the gate of each stacked transistor can be shared as a word line, and the word line extending in the vertical direction saves space.
  • the 3D memory provided by this embodiment can change the channel size in the semiconductor device by adjusting the thickness of the source electrode or the drain electrode, and the process is simple and has little effect on the size of the device.
  • FIG17A only shows three insulating layers and two metal layers stacked alternately, but the embodiments of the present disclosure are not limited thereto, and more layers may be stacked as needed, for example, hundreds of insulating layers and hundreds of metal layers, and the embodiments of the present disclosure are not limited thereto.
  • the present disclosure also provides an electronic device, including the 3D memory described in any of the above embodiments.
  • the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include a memory in a computer, etc., which is not limited here.
  • an embodiment of the present disclosure provides a method for manufacturing a 3D memory, wherein the 3D memory includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a word line, wherein the memory cell includes a transistor, wherein the transistor includes a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate; the method for manufacturing the 3D memory includes:
  • Step 1801 providing a substrate, and alternately depositing a plurality of insulating films and a plurality of metal films on the substrate in sequence, and patterning to form a plurality of stacked structures, each of the stacked structures comprising a stack of alternately arranged insulating layers and metal layers, each of the metal layers corresponding to a transistor in a layer of the memory cell, and each of the metal layers comprising a first sub-portion and a second sub-portion connected to each other;
  • Step 1802 etching the stacked structure to form a through hole penetrating the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes the first sub-portion and the second sub-portion of each metal layer and the insulating layer; etching each first sub-portion in the through hole to form a first channel, etching each second sub-portion in the through hole to form a second channel, wherein the first channel and the second channel are connected to the through hole;
  • Step 1803 depositing a metal film in a channel formed by the first channel, the second channel and the through hole, and etching the metal film in the through hole to form a source electrode located in the first channel and a drain electrode located in the second channel;
  • Step 1804 filling the sidewalls of the through holes with a semiconductor film to form a semiconductor layer of each of the transistors, wherein the semiconductor layer is in contact with each of the source electrodes and each of the drain electrodes, and the channel between the source electrode and the drain electrode in the same transistor is a horizontal channel;
  • Step 1805 depositing a gate insulating layer and a metal film in sequence in the through hole, the metal film filling the through hole in the gate insulating layer to form the word line, and the gates of the transistors in different layers are part of the word line.
  • insulating films and metal films After the above-mentioned alternate deposition of insulating films and metal films, a plurality of insulating films and metal films are formed, and the film farthest from the substrate is the insulating film.
  • the method before depositing the metal film in the channel formed by the first channel, the second channel and the through hole, the method further includes:
  • Etching the metal film in the through hole includes: etching a gate insulating film and a metal film in the through hole.
  • the above manufacturing process may refer to the manufacturing process of the transistor in the above embodiment.
  • the processing of the multiple metal films may be consistent with the processing of the metal films in the above transistor manufacturing process, and will not be repeated here.
  • the manufacturing method of the 3D memory provided in this embodiment is to arrange the source contact area and the drain contact area on the semiconductor layer of the manufactured 3D memory so that the channel direction between the source and the drain generally extends in a direction parallel to the substrate, which is convenient for realizing a 3D stacked memory with a simple structure and relatively easy manufacturing.
  • the gate of each stacked transistor can be shared as a word line, and the word line extending in the vertical direction saves space.
  • the 3D memory provided in this embodiment can change the channel size by adjusting the thickness of the source electrode or the drain electrode, and the process is simple and has little effect on the size of the device.
  • an embodiment of the present disclosure provides a method for manufacturing a 3D memory, wherein the 3D memory may include multiple layers of memory cells and word lines stacked in a direction perpendicular to a substrate, wherein the memory cell may include: a transistor, wherein the transistor may include a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding a sidewall of the gate; the manufacturing method may include:
  • Step 1901 providing a substrate, and alternately depositing a plurality of insulating films and a plurality of metal films on the substrate in sequence, and patterning to form a plurality of stacked structures; each of the stacked structures comprises a stack of alternately arranged insulating layers and metal layers, each of the metal layers corresponds to a transistor in a layer of the memory cell, and each of the metal layers comprises a first sub-portion and a second sub-portion connected to each other;
  • Step 1902 etching the stacked structure to form a through hole penetrating the stacked structure in a direction perpendicular to the substrate, and forming a source electrode obtained by etching the first sub-portion, and forming a drain electrode obtained by etching the second sub-portion;
  • Step 1903 sequentially depositing semiconductor films on the sidewalls of the through holes to form semiconductor layers, wherein the semiconductor layers are in contact with each of the source electrodes and each of the drain electrodes; the length direction of the channel between the source electrode and the drain electrode in the same transistor is parallel to the substrate;
  • Step 1904 depositing a gate insulating layer and a metal film in sequence in the through hole, the metal film filling the through hole in the gate insulating layer to form the word line, and the gates of the transistors in different layers are part of the word line.
  • the manufacturing method of the 3D memory provided by the embodiment of the present disclosure facilitates the realization of a 3D stacked memory with a simple structure and relatively easy manufacturing, and the 3D memory provided by the embodiment of the present disclosure can change the channel size by adjusting the thickness of the source electrode or the drain electrode, the process is simple, and the effect on the size of the transistor is small.
  • the manufacturing method of the embodiment of the present disclosure can be realized by using existing mature manufacturing equipment, with little improvement on the existing process, and can be well compatible with the existing manufacturing process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.
  • the embodiment of the present disclosure provides a method for manufacturing a 3D memory, wherein the 3D memory includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a word line;
  • the memory cell includes: a transistor, wherein the transistor includes a source electrode, a drain electrode, a gate extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate; the manufacturing method of the 3D memory may include:
  • each of the stacked structures comprises a stack of insulating layers and conductive layers alternately arranged in a direction perpendicular to the substrate, each of the conductive layers corresponds to a transistor in a layer of the memory cells, and each of the conductive layers comprises a first sub-portion and a second sub-portion connected to each other;
  • a semiconductor film is filled on the sidewall of the through hole to form a semiconductor layer of each of the transistors, wherein the semiconductor layer is in contact with each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode in the same transistor is a horizontal channel;
  • a gate insulating layer and a metal film are sequentially deposited in the through hole, the metal film fills the through hole in the gate insulating layer to form the word line, and the gates of the transistors at different layers are part of the word line.

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Abstract

一种晶体管、3D存储器及其制造方法、电子设备，涉及半导体技术领域，3D存储器包括多层沿垂直于衬底（1）的方向堆叠的存储单元，字线（110），存储单元包括：晶体管，所述晶体管包括源电极（51）和漏电极（52）、沿垂直于衬底（1）的方向延伸的栅极（11）、环绕栅极（11）侧壁的半导体层（9）；半导体层（9）包括间隔设置的源接触区和漏接触区；源接触区和漏接触区之间的沟道为水平沟道，字线（110）沿着垂直衬底（1）的方向延伸且贯穿不同层的所述存储单元。

Description

晶体管、3D存储器及其制造方法、电子设备
本申请要求于2022年10月18日提交中国专利局、申请号为202211270027.3、发明名称为“一种晶体管、3D存储器及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域，尤指一种晶体管、3D存储器及其制造方法、电子设备。
背景技术
近些年，3D结构的存储器受到越来越多的关注，在提高存储器的密度具有一定优势。示例性的，以具有可沉积在任意材料表面特性和高开关比特性的金属氧化物，比如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)作为沟道的半导体存储器件受到业界关注。在存储器领域，为了提高存储单元的密度，可以将该金属氧化物半导体晶体管用于存储单元的3D堆叠结构。
目前越来越多地关注3D器件的设计结构在产业上制作的便利性以及存储密度上的优势等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种3D存储器，包括：多层沿垂直于衬底的方向堆叠的存储单元，字线，其中，所述字线沿着垂直所述衬底的方向延伸且贯穿不同层的所述存储单元；
所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极，位于所述栅极侧壁且与所述栅极相绝缘的半 导体层；其中，所述半导体层包括间隔设置的源接触区和漏接触区，所述源接触区和漏接触区之间的沟道为水平沟道。
在一示例性实施例中，所述半导体层环绕所述栅极的侧壁。
在一示例性实施例中，不同层的晶体管的所述源电极间隔设置，不同层的晶体管的所述漏电极间隔设置。
在一示例性实施例中，不同层的晶体管的所述栅极为所述字线的一部分，不同层的晶体管对应的半导体层位于所述字线的侧壁。。
在一示例性实施例中，同一所述晶体管的所述源电极为源电极膜层，所述漏电极为漏电极膜层，所述漏电极膜层和源电极膜层位于同一层且间隔设置。
在一示例性实施例中，不同晶体管的所述源电极膜层或所述漏电极膜层位于不同膜层。
在一示例性实施例中，在平行于所述衬底的平面上，同一个所述晶体管的所述源电极和所述漏电极的正投影无交叠；
在平行于所述衬底的平面上，不同晶体管的源电极和漏电极的正投影无交叠。
在一示例性实施例中，所述源电极位于所述栅极的第一侧，所述漏电极位于所述栅极的第二侧，所述源电极和所述漏电极相向设置。
在一示例性实施例中，不同层的所述存储单元的所述晶体管的半导体层在垂直所述衬底的方向上间隔设置。
在一示例性实施例中，所述间隔设置的所述半导体层之间露出绝缘层，所述绝缘层为位于所述栅极和所述半导体层之间的栅绝缘层。
在一示例性实施例中，不同层的所述存储单元中每相邻两个半导体层之间连接为一体式结构。
本公开实施例提供一种用于3D存储器的垂直晶体管，包括：衬底，设置在所述衬底上的源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、全部或部分环绕所述栅极且与所述栅极相绝缘的半导体层；其中，所述半导 体层包括间隔设置的源接触区和漏接触区，所述源接触区和漏接触区之间的沟道为水平沟道。
在一示例性实施例中，所述源电极的膜层和所述漏电极的膜层为同一导电膜层的不同区域，且间隔设置，所述同一导电膜层与所述衬底大约平行。
在一示例性实施例中，所述半导体层的材料包括金属氧化物半导体材料。
在一示例性实施例中，在平行于所述衬底的平面上，所述源电极的正投影和所述漏电极的正投影无交叠。
在一示例性实施例中，所述源接触区位于所述半导体层的第一侧，所述漏接触区位于所述半导体层的第二侧，所述源电极与所述源接触区接触，所述漏电极与所述漏接触区接触，所述源电极和所述漏电极相向设置。
在一示例性实施例中，所述半导体层为环状的全环绕型半导体层。
本公开实施例提供一种3D存储器的制造方法，所述3D存储器包括多层沿垂直于衬底的方向堆叠的多个存储单元、一条字线；
所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、环绕所述栅极的半导体层；所述3D存储器的制造方法包括：
提供衬底，在所述衬底上依次交替沉积多个绝缘薄膜和多个导电薄膜，进行构图形成多个在平行于衬底方向间隔的堆叠结构；每个所述堆叠结构包括在垂直衬底方向交替设置的绝缘层和导电层的堆叠，每个所述导电层对应一层所述存储单元中的一个晶体管，每个所述导电层包括相连的第一子部和第二子部；
刻蚀所述堆叠结构以形成在垂直所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层的所述第一子部和第二子部以及所述绝缘层；刻蚀所述通孔内的每个所述第一子部形成对应多个晶体管的多个第一通道，刻蚀所述通孔内的每个所述第二子部形成对应多个晶体管的多个第二通道，每个所述第一通道、每个所述第二通道间隔且分别与所述通孔贯通；
在各所述第一通道、各第二通道和所述通孔构成的通道内沉积金属薄膜， 刻蚀去除所述通孔内的所述金属薄膜保留每个所述第一通道、每个所述第二通道内的金属膜层以形成位于多个所述第一通道的多个源电极和位于多个所述第二通道的多个漏电极；
在所述通孔的侧壁填充半导体薄膜以形成每个所述晶体管的半导体层，所述半导体层与每个所述源电极接触且与每个所述漏电极接触，同一个晶体管中所述源电极和所述漏电极之间的沟道为水平沟道；
在所述通孔内依次沉积栅极绝缘层和金属薄膜，所述金属薄膜填充所述栅极绝缘层内的通孔形成所述字线，不同层的所述晶体管的所述栅极为所述字线的一部分。
本公开实施例提供一种电子设备，包括上述任一实施例所述的3D存储器，或者，包括任一实施例所述的用于3D存储器的垂直晶体管。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1为一示例性实施例提供的晶体管示意图；
图2为图1所示晶体管AA方向的截面图；
图3为一示例性实施例提供的形成第二绝缘薄膜后的示意图；
图4为一示例性实施例提供的形成开槽后的示意图；
图5为一示例性实施例提供的填充所述开槽后的示意图；
图6为一示例性实施例提供的形成通孔后的示意图；
图7A为一示例性实施例提供的形成通道后的示意图；
图7B为一示例性实施例提供的第一金属层的示意图；
图8A为一示例性实施例提供的形成有源层和第一栅绝缘层后的示意图；
图8B为图8A的局部示意图；
图8C为图8B沿BB方向的截面示意图；
图9A为一示例性实施例提供的形成第二金属层后的示意图；
图9B为图9A的局部示意图；
图9C为图9B沿BB方向的截面示意图；
图10A为一示例性实施例提供的去除通孔内的第二金属层后的示意图；
图10B为图10A的局部示意图；
图10C为图10B沿BB方向的截面示意图；
图11A为一示例性实施例提供的形成栅极后的示意图；
图11B为图11A的局部示意图；
图11C为图11B沿BB方向的截面示意图；
图11D为一示例性实施例提供的源电极、漏电极和栅极的截面示意图；
图12为一示例性实施例提供的形成第二绝缘薄膜后的示意图；
图13为一示例性实施例提供的形成开槽后的示意图；
图14为一示例性实施例提供的填充所述开槽后的示意图；
图15为一示例性实施例提供的形成通孔后的示意图；
图16为一示例性实施例提供的形成栅极后的示意图；
图17A为一示例性实施例提供的半导体器件示意图；
图17B为17A局部示意图；
图18为一示例性实施例提供的半导体器件制造方法流程图；
图19为另一示例性实施例提供的半导体器件制造方法流程图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下， 本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
下面将按照晶体管，以及3D存储器的顺序分别介绍本申请。
图1为一示例性实施例提供的存储单元阵列中的晶体管截面示意图。图2为图1所示晶体管AA方向的截面图。如图1和图2所示，本实施例提供一种晶体管，可以包括：衬底1，设置在所述衬底1上的源电极51、漏电极52和沿第一方向Z延伸的栅极11，以及，环绕所述栅极11且与所述栅极11相绝缘的半导体层9，比如，可以包括环绕所述栅极11的栅绝缘层10，环绕所述栅绝缘层10的半导体层9。
所述衬底为起支撑作用的基底，其材料和内部构造不是本申请的重点，因此，本申请不做具体描述。
所述的衬底1上的源电极51、漏电极52和沿第一方向Z延伸的栅极11，可以理解为设置于衬底上方的源电极51、漏电极52和沿第一方向Z延伸的栅极11。
所述沿第一方向Z延伸的栅极11可以理解为沿着垂直衬底的方向延伸的栅极，且整体上仅沿着衬底方向延伸，但是栅极的侧表面的形貌不做具体限制。示例性的，栅极的横截面形状和尺寸可以是类似，或者，横截面形状和尺寸在不同区域有差异。
其中，一些实施方式中，所述源电极51、漏电极52的功能可以互换，比如，如图1中的源电极51在另一些实施例中为漏电极，如图1中的漏电极52在另一些实施例中为源电极。
所述的栅极沿着垂直衬底的方向延伸，其中，该栅极包括侧表面和上下两端的端面，侧表面整体上与衬底垂直，或者说与半导体层对应的起栅极控制作用的侧壁的部分区域，该区域的膜层与衬底垂直。
其中，环绕所述栅极11且与所述栅极11相绝缘的半导体层9，其中的半导体层可以理解为一个膜层，该膜层具有两个相对的主表面和两个端面。 两个相对主表面为相比端面其表面积更大。比如，半导体层9沿着栅极的侧壁延伸，其膜层厚度方向为平行衬底的方向，膜层在栅极侧壁的上下延伸的长度为膜层的高度，环绕所述栅极的长度为膜层的宽度。
其中，环绕可以理解为部分或全部环绕所述栅极。一些实施例中，所述环绕可以是整体上全部环绕，环绕后的半导体层的横截面为环形。所述横截面的截取方向为沿着平行于衬底的方向截取。一些实施例中，所述环绕可以是部分环绕，环绕后的横截面不是闭合的，但是呈现环形状。比如，具有开口的环形。
如图2所示，所述半导体层9可以包括间隔设置的源接触区91和漏接触区92，所述源电极51与所述源接触区91接触，所述漏电极52与所述漏接触区92接触，所述源电极51和所述漏电极52通过所述栅绝缘层10与所述栅极11绝缘，所述源接触区91和漏接触区92之间的沟道为水平沟道，即沟道中载流子的传输方向与所述衬底1的上表面(即朝向所述栅极11一侧的表面)平行。或者，可以理解为沟道的长度方向与所述衬底1平行。所述沟道具有载流子的传输方向，该方向为沟道的长度方向，与长度方向垂直的方向为沟道的宽度方向。所述第一方向Z可以垂直于所述衬底1。
所述源接触区91和漏接触区92的间隔设置指不直接相连，一些实施例中，可以是在平行于衬底1的方向上间隔设置，在垂直衬底1的方向源接触区91和漏接触区92的中心位置可以是处于同一平面或相互错开一定距离，但是需要确保沟道方向整体上是不垂直于衬底的，而是倾向于水平方向。
在一示例性实施例中，所述半导体层9仅位于所述栅极11的侧壁。或者可以理解为，绝缘层中形成沿着衬底方向延伸的孔，半导体层位于所述孔壁上，沿着垂直衬底的方向延伸形成孔状结构，所述栅极依照所述孔的形状形成于所述孔内通过栅极绝缘层与所述栅极绝缘。所述栅极可以是实心的结构，可以是空心结构。
在一示例性实施例中，所述半导体层9在所述栅极11的侧壁上可以延伸形成沿着垂直所述衬底1方向延伸的环形的半导体层。在一示例性实施例中，半导体层9环绕所述栅极11，但是与栅极11不接触，栅极11外侧壁环绕有栅绝缘层10，半导体层9环绕所述栅绝缘层10。所述半导体层9可以为全环 绕型或部分环绕型，比如，在垂直衬底1的方向上，所述半导体层9可能有间隙。
半导体层9上的源接触区91和漏接触区92是根据源电极和漏电极确定的，设置有源电极51和漏电极52的位置且与半导体层接触的区域分别为源接触区91和漏接触区92。源接触区91和漏接触区92的位置使得沟道中载流子的传输方向不在垂直方向而是在水平方向。比如，源电极51和漏电极52之间的沟道方向总体上沿着平行于衬底1的方向延伸，另外，在制作3D叠层存储单元时，可以将每个叠层的晶体管的栅极11相连作为3D堆叠的每个晶体管连接的字线，垂直方向延伸的字线节约空间且可以一次工艺形成每个晶体管的栅极和字线，减少掩模罩的数量，有效简化工艺制程，降低成本。
每个源电极51对应设置有一个独立的源接触区域，每个漏电极52对应设置有一个漏接触区域。
所述字线在垂直方向延伸可以是沿着直线方向延伸，也可以是曲线方向延伸。一些实施例中，每个晶体管的垂直方向延伸的栅极11可以为直线，且在衬底1上的正投影可以在相同位置，则每个晶体管的栅极连接后形成直线型字线。所述曲线可以是整体上不直，但是在对应半导体区域或有效半导体区域的栅极是沿着垂直衬底的方向延伸的直线，两个相邻层之间的字线部分可以不是直线。
所述直线型字线的沿平行于衬底1方向的横截面可以处处相同，或不完全相同。本申请实施例不对该直线的横截面特点做限定。
一些实施例中，每个晶体管的垂直方向延伸的栅极11可以为直线，且在衬底1上的正投影可以在不完全相同的位置，则每个晶体管的栅极11连接后形成整体沿着垂直衬底1的方向延伸但局部为曲线。
水平沟道为沟道中载流子传输方向在平行于衬底的平面内，但是不限制载流子的传输方向必须是一个方向。实际应用中，载流子的传输方向整体上沿着一个方向延伸，但是在局部，与半导体层的形状有关。换句话说，水平沟道不代表在水平面内必须沿着一个直线方向延伸，可能沿着不同的方向延伸，比如半导体层9为环形时，环形半导体层上的源接触区91和漏接触区92为环形的一部分，此时，载流子从源接触区91向漏接触区92整体上沿着 一个方向延伸，在局部可能不是一个方向。当然载流子传输方向在平行于衬底1的平面内也是一个宏观上的概念，并不局限于绝对的平行于衬底，本申请保护源电极51和漏电极52之间的沟道为非垂直于衬底1的沟道。
本公开一些实施例提供的晶体管，每个晶体管的栅极为垂直方向的栅极，且沟道为水平沟道，便于实现结构简单且制作相对容易的3D堆叠的存储器。在一示例性实施中，在平行于所述衬底1的平面上，所述源电极51的正投影和所述漏电极52的正投影可以无交叠，这确保了沟道为水平沟道。
在一示例性实施中，所述源接触区91和漏接触区92在垂直于所述衬底1的平面上的正投影可以具有交叠，其中，所述平面位于所述源接触区91和漏接触区92之间。
在一示例性实施中，所述半导体层9可以为全环绕型，在栅极11的侧壁上全环绕，也就是说，在栅极11对应的区域，半导体层9的横截面为闭环。示例性的，所述半导体层9为环形，在栅极11的每个位置的横截面，半导体层9为环形，且环形形状与栅极11横截面外轮廓形状相适应。示例性的，所述栅极11的横截面外轮廓可以为圆形、椭圆、方形等结构。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述源电极51靠近所述衬底1一侧的表面与所述衬底1的第一距离，和所述漏电极52靠近所述衬底1一侧的表面与所述衬底1的第二距离可以相同。即，所述源电极51和所述漏电极52与所述衬底1的距离相同。但本公开实施例不限于此，第一距离和第二距离可以不同。可以理解为所述源电极51和所述漏电极52位于同一金属膜层的不同区域且间隔设置，由一个金属膜层图案化形成，所述金属膜层与所述衬底1的上表面大约平行。所述源电极51和所述漏电极52分别具有上下两个主表面和侧面，所述侧面与所述半导体层9接触，所述侧面的形状与所述半导体层9的侧壁的形状相适应。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述源电极51的第一厚度，和所述漏电极52的第二厚度可以相同。但本公开实施例不限于此，第一厚度和第二厚度可以不同。
在一示例性实施例中，沿垂直于所述衬底1方向，所述源电极51和漏电 极52可以位于同一导电膜层。可以理解为源电极51和漏电极52位于同一金属膜层，由一个金属膜层图案化形成，所述金属膜层与所述衬底1的上表面大约平行。
在一示例性实施例中，在平行于所述衬底1的平面上，所述栅极11的正投影可以位于所述源电极51的正投影外，所述栅极11的正投影可以位于所述漏电极52的正投影外。本实施例提供的方案，可以实现结构简单且制作相对容易的多个晶体管，每个晶体管的栅极11连接形成字线。
在一示例性实施例中，所述半导体层9可以为金属氧化物半导体层，或者，为含硅的半导体层。
在一示例性实施例中，所述金属氧化物半导体层中的金属可以包括：铟、锡、锌、铝、镓中的至少之一，但并不限于该列举的材料实施例。
在一示例性实施例中，所述金属氧化物半导体层可以包含如下：氧化铟、氧化锡、铟锌(In-Zn)类氧化物、锡锌(Sn-Zn)类氧化物、铝锌(Al-Zn)类氧化物、铟镓(In-Ga)类氧化物、铟镓锌(In-Ga-Zn)类氧化物、铟铝锌(In-Al-Zn)类氧化物、铟锡锌(In-Sn-Zn)类氧化物、锡镓锌(Sn-Ga-Zn)类氧化物、铝镓锌(Al-Ga-Zn)类氧化物、锡铝锌(Sn-Al-Zn)类氧化物中的至少一种。
在一示例性实施例中，如图2所示，栅极11的横截面可以为矩形，侧表面具有四个侧面，每两个侧面相向(如第一侧和第二侧相向)。所述源电极51可以位于所述栅极11的第一侧，所述漏电极52可以位于所述栅极11的第二侧，所述源电极51和所述漏电极52可以相向设置。即，所述第一侧和所述第二侧为相对的两侧。但本公开实施例不限于此，源电极51和漏电极52可以是其他位置。
在一示例性实施例中，将所述晶体管置于阵列中时，所述源电极51可以沿第二方向X延伸，所述漏电极52可以沿第三方向Y延伸，所述第二方向X可以平行于所述衬底1，所述第三方向Y可以平行于所述衬底1。但本公开实施例不限于此，所述源电极51和所述漏电极52可以是其他形状。可以理解为所述源电极51与引线一体式设置，所述漏电极52与引线一体式设置，此时难以鉴定所述源电极51和所述漏电极52与各自的引线之间的分界， 但是可以理解为与所述源电极51一体式设置的引线在水平面内沿着行方向延伸，与所述漏电极52一体式设置的引线在列方向延伸。
在一示例性实施例中，所述第二方向X和所述第三方向Y可以交叉。
在一示例性实施例中，所述第二方向X和所述第三方向Y可以垂直，但本公开实施例不限于此，第二方向X和第三方向Y之间可以是其他角度。
在一示例性实施例中，在垂直于所述衬底1的方向，所述源电极51的截面可以是方形、圆形、椭圆形等，所述漏电极52的截面可以是方形、圆形、椭圆形等，本公开实施例不限于此，所述源电极51的截面和所述漏电极52的截面可以是其他形状，比如，圆形、六边形等等。
在一示例性实施例中，所述源电极51和所述漏电极52可以连接在与图1所示的位置不同的其他位置，比如，所述源电极51连接在所述半导体层9构成的环形柱体的第一侧，所述漏电极52连接在所述半导体层9构成的环形柱体的第二侧，且第一侧和第二侧相邻，等等。
在一示例性实施例中，所述源电极51和所述漏电极52可以同层设置。即所述源电极51和所述漏电极52可以通过同一次图案化工艺同时形成，但本公开实施例不限于此，可以通过不同图案化工艺分别制造所述源电极51和所述漏电极52。
本申请实施例所述的源电极51和漏电极52仅指一个晶体管的除去栅极之外的第一电极和第二电极，所述第一电极和第二电极其中之一为源电极，另一为漏电极。在产品中识别源或漏电极根据电流的流向确定，比如，本申请实施例描述的源电极可能根据电流的流向解释为漏电极。
如图2所示，本实施例提供的方案，源电极51和漏电极52之间的沟道的尺寸可以通过在垂直于所述衬底1的平面上，所述源电极51的正投影与所述漏电极52的正投影之间的交叠长度进行控制。图2中，所述源电极51的正投影与所述漏电极52的正投影之间的交叠长度为d，可以通过控制源电极51和漏电极52沿垂直于衬底1方向的厚度来控制沟道尺寸，相比源电极环绕栅极，漏电极环绕栅极的晶体管，通过改变栅极所在的通孔的尺寸(需改变工艺)或者增大源电极和漏电极之间的距离来控制沟道尺寸(会导致晶体 管体积增大)，本实施例可以更为方便的控制沟道的尺寸，工艺改动小，且对晶体管的尺寸影响较小。
图1和图2所示的晶体管结构为简化示意图。实际制造的晶体管中，还可以包括其他膜层，比如包括位于衬底1与所述源电极51、所述漏电极52之间的绝缘层，以及，覆盖所述源电极51和所述漏电极52的绝缘层等等。
下面通过本实施例晶体管的制造过程说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制造工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制造工艺。沉积可采用溅射、蒸镀、化学气相沉积、原子层沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
上述晶体管3D堆叠有多种制作方法，本申请从理解该案结构的角度，示例性地介绍一种实现方案，该方案用于理解上述结构，但是不用于限制上述结构。
在一示例性实施例中，晶体管的制造过程可以包括：
1)在衬底1上依次沉积第一绝缘薄膜、第一金属薄膜、第二绝缘薄膜，分别形成第一绝缘层2、第一金属层3和第二绝缘层4，如图3所示。
在一示例性实施例中，所述衬底1可以使用玻璃、硅、柔性材料等制造。所述柔性材料可以采用聚酰亚胺(PI)，聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。在示例性实施例中，衬底1可以是单层结构，或者是多层的叠层结构，叠层结构的衬底可以包括：柔性材料/无机材料/柔性材料，所述无机材料比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)等中的任意一种或多种。
在一示例性实施例中，所述第一绝缘薄膜和第二绝缘薄膜可以是low-K介质层，即介电常数K<3.9的介质层。比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。所述第一绝缘薄膜和第二绝缘薄膜可以是相同的材料或者不同的材料。
在一示例性实施例中，所述第一金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)等。
2)对所述第一绝缘层2、第一金属层3、第二绝缘层4通过构图工艺进行构图，形成第一开槽P1和第二开槽P2，如图4所示。所述第一开槽P1贯通所述第一绝缘层2、第一金属层3和第二绝缘层4，所述第二开槽P2贯通所述第一绝缘层2、第一金属层3和第二绝缘层4。所述第一金属层3可以包括沿第二方向X延伸的第一子部31和沿第三方向Y延伸的第二子部32。
在一示例性实施例中，在平行于所述衬底1的平面上，所述第一绝缘层2、所述第一金属层3和所述第二绝缘层4的截面可以为H形。此时所述第一金属层3可以包括彼此相对的第二子部32和第三子部33，以及连接所述第二子部32和第三子部33的第一子部31。
在一示例性实施例中，所述第一开槽P1和第二开槽P2的大小和形状可以相同，但本公开实施例不限于此，第一开槽P1和所述第二开槽P2的大小和形状可以不同。
在一示例性实施例中，所述第三子部33可以沿第三方向Y延伸。但本公开实施例不限于此，第三子部33可以是其他形状。在一示例性实施例中，可以去除第三子部33。
本实施例中，第一金属层3的图案仅为示例，第一金属层3可以是其他形状的图案，比如，沿第一子部31的延伸方向将当前第二子部32进行分割为两个部分，可以只保留其中一个部分作为第二子部32。
3)在形成有前述图案的衬底1上，沉积第三绝缘薄膜，形成第三绝缘层5，所述第三绝缘层5填充所述第一开槽P1和第二开槽P2，如图5所示。
在一示例性实施例中，所述第三绝缘薄膜可以是low-K介质层，即介电 常数K<3.9的介质层，比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。所述第三绝缘薄膜和第一绝缘薄膜、第二绝缘薄膜可以是相同的材料或者不同的材料。
4)在形成有前述图案的衬底1上，形成贯穿所述第一绝缘层2、第一金属层3和第二绝缘层4的通孔41，在平行于所述衬底1的平面上，所述通孔41的正投影可以与所述第一子部31的正投影存在交叠，与所述第二子部32的正投影存在交叠，如图6所示。图6所示的通孔41在平行于所述衬底1的平面上的截面为四边形，但本公开实施例不限于此，通孔41在平行于所述衬底1的平面上的截面可以是其他形状，比如圆形、五边形、六边形等等。
5)在形成有前述图案的衬底1上，选择性刻蚀掉第一金属层3中的第一子部31、第二子部32，以及，第三子部33与第一子部31的连接处，此时，第一金属层3只剩下第三子部33，且第三子部33设置有朝向第一子部31(第一子部31已被刻蚀掉)的第三开槽P3，如图7A和图7B所示，此时形成了由被选择性刻蚀掉的第一子部31所在的区域形成的第一通道42、第二子部32所在的区域形成的第二通道43和所述通孔41，所述第一通道42与所述通孔41贯通，所述第二通道43与所述通孔41贯通。
6)在步骤5形成的通道(即通孔41、第一通道42和第二通道43)的侧壁，依次沉积第一半导体薄膜和第一栅极氧化物薄膜，以分别形成有源层6和第一栅绝缘层7，如图8A、8B和8C所示，其中，图8C为图8B沿BB方向的截面图，且仅示出了有源层6和第一栅绝缘层7。此时有源层6和第一栅绝缘层7作为所述通道的通道壁，所述有源层6环绕所述第一栅绝缘层7。
在一示例性实施例中，所述第一栅极氧化物薄膜可以为High-K介质材料。High-K介质材料可以包括但不限于以下至少之一：氧化硅，氧化铝，氧化铪。
在一示例性实施例中，所述第一半导体薄膜作为沟道层，可以是含有硅的膜层，或金属氧化物半导体，其中，所述金属氧化物半导体包括但不限于以下至少之一材料形成：IGZO、氧化铟锡(Indium Tin Oxide，ITO)、氧化铟 锌(Indium Zinc Oxide，IZO)。使用IGZO作为半导体层时，具备低漏电，刷新时间短的优势。后续第二半导体薄膜类似，不再赘述。
在一示例性实施例中，可以通过原子层沉积(Atomic Layer Deposition，ALD)方法沉积所述第一半导体薄膜和所述第一栅极氧化物薄膜。
6)在所述通道(即通孔41、第一通道42和第二通道43)内沉积第二金属薄膜，形成第二金属层8，所述第二金属层8完全填充所述通道，如图9A、图9B和图9C所示。图9C为图9B沿BB方向的截面图，且仅示出了有源层6、第一栅绝缘层7和第二金属层8。此时，第一栅绝缘层7环绕所述第二金属层8。
在一示例性实施例中，所述第二金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。所述第二金属薄膜可以和所述第一金属薄膜相同或不同。
7)选择性地光刻和刻蚀所述通孔41所在的位置中的第二金属层8和第一栅绝缘层7，保留通道中其他位置的第二金属层8(与衬底1平行的第一通道42和第二通道43中的第二金属层8)，如图10A、图10B和图10C所示，图10C为图10B沿BB方向的截面图，且仅示出了有源层6、第一栅绝缘层7和第二金属层8。位于第一通道42的第二金属层8作为晶体管的源电极51，位于第二通道43的第二金属层8作为晶体管的漏电极52，且源电极51和漏电极52彼此断开。
8)在上述刻蚀所得的通孔的侧壁依次沉积第二半导体薄膜、第二栅极氧化物薄膜和第三金属薄膜，分别形成半导体层9、栅绝缘层10和栅极11，且所述栅绝缘层10环绕所述栅极11，所述半导体层9环绕所述栅绝缘层10，所述栅极11完全填充所述栅绝缘层10环绕的区域。如图11A、图11B和图11C所示，图11C为图11B沿BB方向的截面图，且仅示出了有源层6、第一栅绝缘层7、半导体层9、栅绝缘层10、第二金属层8(源电极51、漏电极52)、栅极11。
在一示例性实施例中，所述第二栅极氧化物薄膜可以为High-K介质材料。High-K介质材料可以包括但不限于以下至少之一：氧化硅，氧化铝，氧 化铪。
在一示例性实施例中，所述第三金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。所述第三金属薄膜可以和所述第一金属薄膜、第二金属薄膜相同或不同。
采用上述制造方法制造的晶体管，还可以包括环绕所述源电极51和所述漏电极52的第一栅绝缘层7，以及环绕所述第一栅绝缘层7的有源层6(源电极51和漏电极52远离所述栅极11的一侧依次覆盖有第一栅绝缘层7和有源层6，如图11D所示)。在另一示例性实施例中，可以刻蚀去除有源层6和第一栅绝缘层7，本公开实施例对此不作限定。
上述制造过程仅为示例，本公开实施例不限于此，可以通过其他方式进行制造。比如，可以在沉积第一金属薄膜后，通过构图工艺进行构图，形成H形的第一金属层3。后续再沉积第二绝缘薄膜形成第二绝缘层4，无需开槽形成第一开槽P1和第二开槽P2以及无需沉积第三绝缘薄膜。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的晶体管。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
在另一示例性实施例中，所述晶体管的制造过程可以包括：
1)在衬底1上依次沉积第一绝缘薄膜、第一金属薄膜、第二绝缘薄膜，分别形成第一绝缘层2、第一金属层3和第二绝缘层4，如图12所示。
2)对所述第一绝缘层2、第一金属层3、第二绝缘层4通过构图工艺进行构图，形成第三开槽P3和第四开槽P4，如图13所示。所述第三开槽P3贯穿所述第一绝缘层2、第一金属层3和第二绝缘层4，所述第四开槽P4贯穿所述第一绝缘层2、第一金属层3和第二绝缘层4。所述第一金属层3可以包括沿第二方向X延伸的第一子部31和沿第三方向Y延伸的第二子部32。
在一示例性实施例中，所述第三开槽P3和第四开槽P4的大小和形状可以相同，但本公开实施例不限于此，第三开槽P3和第四开槽P4的大小和形状可以不同。
本实施例中，第一金属层3的图案仅为示例，第一金属层3可以是其他形状的图案，比如，沿第一子部31的延伸方向将当前第二子部32进行分割为两个部分，可以只保留其中一个部分作为第二子部32。
3)在形成有前述图案的衬底1上，沉积第三绝缘薄膜，形成第三绝缘层5，所述第三绝缘层5填充所述第三开槽P3和第四开槽P4，如图14所示。
在一示例性实施例中，所述第三绝缘薄膜可以是low-K介质层，即介电常数K<3.9的介质层，比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。所述第三绝缘薄膜和第一绝缘薄膜、第二绝缘薄膜可以是相同的材料或者不同的材料。
4)在形成有前述图案的衬底1上，刻蚀形成贯穿所述第一绝缘层2、第一金属层3和第二绝缘层4的通孔41，在平行于所述衬底1的平面上，所述通孔41的正投影可以与所述第一子部31的正投影存在交叠，所述通孔41的正投影可以与所述第二子部32的正投影存在交叠，如图15所示。第一子部31和第二子部32被刻蚀后其中之一形成漏电极，另一形成源电极。图15所示的通孔41在平行于所述衬底1的平面上的截面为四边形，但本公开实施例不限于此，通孔41在平行于所述衬底1的平面上的截面可以是其他形状，比如圆形、五边形、六边形等等。
5)在上述通孔41的侧壁依次沉积第二半导体薄膜、第二栅极氧化物薄膜和第三金属薄膜，分别形成半导体层9、栅绝缘层10和栅极11，且所述栅绝缘层10环绕所述栅极11，所述半导体层9环绕所述栅绝缘层10，所述栅极11完全填充所述栅绝缘层10环绕的区域。其中，半导体层9即晶体管的半导体层，栅绝缘层10即晶体管的栅绝缘层，栅极11即为晶体管的栅极，如图16所示。
在一示例性实施例中，所述第二栅极氧化物薄膜可以为High-K介质材料。High-K介质材料可以包括但不限于以下至少之一：氧化硅，氧化铝，氧化铪。
在一示例性实施例中，所述第三金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。 所述第三金属薄膜可以和所述第一金属薄膜相同或不同。
制造上述晶体管时，交替堆叠绝缘薄膜和金属薄膜，即可制造共用半导体层9、栅绝缘层10和栅极11的多个晶体管。
上述晶体管可以用于3D存储器。本申请实施例提供的上述晶体管在制作3D叠层存储单元时，若不同层的存储单元中的至少一个晶体管需要堆叠设置时，可以按照上述的晶体管在垂直方向形成一列堆叠结构。该列堆叠结构可以是1T1C存储单元中的晶体管的堆叠，或者，可以是2T0C或2T1C结构中其中一个晶体管的堆叠。
以1T1C存储单元为例，仅介绍纵向一列不同晶体管之间的堆叠方案，介绍如下。本公开实施例提供一种3D存储器，可以包括：多层沿垂直于衬底的方向堆叠的存储单元，字线，其中，所述字线沿着垂直所述衬底的方向延伸且贯穿不同层的所述存储单元；
所述存储单元可以包括：晶体管，所述晶体管可以包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极，环绕所述栅极且与所述栅极相绝缘的半导体层；其中，所述半导体层可以包括间隔设置的源接触区和漏接触区，所述源接触区和漏接触区之间的沟道为水平沟道。
在一示例性实施例中，不同层的晶体管的所述源电极可以间隔设置，不同层的晶体管的所述漏电极可以间隔设置。
在一示例性实施例中，不同层的晶体管的所述栅极为所述字线的一部分。
如图2、图17A和图17B所示，示出两层堆叠的存储单元中的晶体管堆叠，本公开实施例提供一种3D存储器，可以包括：
多层沿垂直于衬底1的方向堆叠的存储单元(附图中仅示出晶体管，没有示出电容)，字线110(字线110中包含栅极11)，其中，
所述存储单元可以包括：一个晶体管，所述晶体管可以包括源电极51(图17A和图17B为立体结构，不是剖面图，源电极51在里面无法显示出来，因此附图中未示出源电极51，请参考晶体管的实施例中的图2、图11A至图11D)、漏电极52、沿垂直于所述衬底1的方向延伸的栅极11、位于所述栅极11侧壁且与所述栅极11相绝缘的半导体层9；其中，所述半导体层可以9 包括间隔设置的源接触区和漏接触区，所述源电极51与所述源接触区接触，所述漏电极52与所述漏接触区接触；所述源接触区和漏接触区之间的沟道为水平沟道；
所述字线110沿着垂直衬底1的方向延伸且贯穿不同层的所述存储单元。
在一示例性实施例中，所述半导体层9可以环绕所述栅极11的侧壁。一些实施例中，所述栅极的侧壁仅沿着垂直衬底的方向延伸，所述半导体层整体上仅沿着垂直衬底的方向延伸，在实际制作产品过程中局部可能存在弯曲的区域也包含在本申请上述所述的情况中。
在一示例性实施例中，不同层的晶体管的所述源电极51可以间隔设置，不同层的晶体管的所述漏电极52可以间隔设置，间隔设置可以理解为相互之间无之间连接关系，位置上相互被绝缘层隔开，但是不代表不同层的源电极或漏电极在其他区域相耦合。
在一示例性实施例中，不同层的所述晶体管的栅极11可以为所述字线110的一部分，不同层的晶体管对应的半导体层9位于所述字线110的侧壁。该设计在工艺上，可以一次性形成不同层存储单元的字线和栅极，显著降低成本。
在一示例性实施例中，不同层的晶体管的所述栅极11连接形成所述字线110。可以理解为所述字线仅沿着垂直方向延伸，没有在侧壁延伸的分支结构。
在一示例性实施例中，沿着垂直所述衬底1的方向延伸的所述字线110可以为一条直线。
在一示例性实施例中，沿着垂直所述衬底1的方向延伸的所述字线不同区域的材料组分相同，可以理解为使用同一次膜层制作工艺形成，所述材料的组分相同可以理解为材料中测试出的主要元素相同，比如，都是通过金属或ITO等透明导电材料制作而成，但是不限制其不同区域的原子数比。
在一示例性实施例中，沿着垂直所述衬底1的方向延伸的所述字线110的横截面形状大约相同，可以理解为使用一种工艺形成挖孔，该孔为纵向孔，该字线填充于形成有沟道和栅极绝缘层的孔中，一般地，孔的横截面形状大约相同，尺寸也大约类似。比如，字线对应不同层的区域，横截面都为环形， 具体均为方形、均为椭圆，或其他形状，本申请不做限定。
在一示例性实施例中，不同层的晶体管对应的半导体层9位于所述字线110的侧壁且分别位于沿垂直所述衬底1的方向延伸的不同区域。
在一示例性实施例中，同一晶体管的所述源电极51和所述漏电极52可以位于同一导电膜层，不同晶体管的所述源电极51或所述漏电极52可以位于不同的导电膜层。
在一示例性实施例中，同一所述晶体管的所述源电极为源电极膜层，所述漏电极为漏电极膜层，所述漏电极膜层和源电极膜层位于同一层且间隔设置。在实际工艺中，一个晶体管的所述源电极和漏电极通过对一个导电膜层进行图案化工艺形成，因此可以理解为所述漏电极膜层和源电极膜层位于同一层，在实际产品上，横截面在一个水平面上且材料相同。
在一示例性实施例中，不同晶体管的所述源电极膜层或所述漏电极膜层位于不同膜层，体现出不同晶体管的3D堆叠结构。3D堆叠结构的不同晶体管的所述源电极在垂直衬底的方向的投影重叠，不同晶体管的所述漏电极在垂直衬底的方向的投影重叠，在工艺过程中，可以通过导电层和绝缘层的相对堆叠再通过一个mask形成多层堆叠的源电极和漏电极，实现工艺简单。
在一示例性实施例中，所述导电膜层可以与所述衬底1平行。
在一示例性实施例中，所述源接触区和所述漏接触区在垂直于所述衬底1的平面上的正投影具有交叠。
在一示例性实施例中，在平行于所述衬底1的平面上，同一所述晶体管的所述源电极51的正投影和所述漏电极52的正投影无交叠。
在一示例性实施例中，在平行于所述衬底1的平面上，不同晶体管的所述源电极51和所述漏电极52的正投影无交叠。
在一示例性实施例中，所述源电极51可以位于所述栅极11的第一侧，所述漏电极52可以位于所述栅极12的第二侧，所述源电极51和所述漏电极52可以相向设置。
在一示例性实施例中，不同层的所述存储单元的所述晶体管的半导体层9在垂直所述衬底1的方向上可以间隔设置。本实施例提供的方案，可以避 免不同层的晶体管之间通过半导体层9漏电，降低功耗。
在一示例性实施例中，所述间隔设置的所述半导体层9之间具有隔离层，所述隔离层可以为通过对所述半导体层9掺杂得到的绝缘层。
在一示例性实施例中，所述字线110的侧壁设置有环绕所述字线110的栅绝缘层10，不同层的所述晶体管的所述半导体层9可以连续分布于所述字线110的侧壁。
在一示例性实施例中，所述间隔设置的半导体层9之间可以露出绝缘层，所述绝缘层可以为位于所述栅极11和所述半导体层9之间的栅绝缘层10。
在一示例性实施例中，不同层的所述存储单元中每相邻两个半导体层9之间可以连接为一体式结构。
在一示例性实施例中，不同层的堆叠的晶体管可以共用一条沿着垂直所述衬底1方向延伸的所述字线110。
在一示例性实施例中，不同层的晶体管可以共用一个沿着垂直所述衬底1方向延伸的环状的栅绝缘层10。本实施例中，可以通过一次制造工艺形成多层晶体管的栅绝缘层10，简化工艺，降低成本。
在一示例性实施例中，不同层的晶体管可以共用一个沿着垂直衬底1方向延伸的环状的半导体层9。本实施例中，可以通过一次制造工艺形成多层晶体管的半导体层9，简化工艺，降低成本。
在一示例性实施例中，所述半导体层9可以为金属氧化物半导体层，或所述半导体层9可以为含硅的半导体层。
在一示例性实施例中，不同层的所述源电极51在衬底1上的投影可以位于相同区域，不同层的所述漏电极52在衬底1上的投影可以位于相同区域；不同层的栅极11在衬底1上投影可以位于相同区域。本实施例提供的方案，不同层的源电极51、漏电极52、栅极11的正投影位于相同区域，可以使得3D存储器结构紧凑，另外，可以简化制造工艺，无需为每层的源电极51和漏电极52分别进行构图。
上述3D存储器中单个晶体管的结构可参考前述多个实施例中的晶体管的结构，此处不再赘述。
本实施例提供的3D存储器，晶体管的栅极为垂直方向的栅极，且沟道为水平沟道，便于实现结构简单且制作相对容易的3D堆叠存储器，3D集成度高。另外，可以共用每个叠层的晶体管的栅极作为字线，垂直方向延伸的字线节约空间。且本实施例提供的3D存储器，可以通过调节源电极或漏电极的厚度改变半导体器件中的沟道尺寸，工艺简便，对器件的尺寸影响小。
图17A中仅示出了交替堆叠的3个绝缘层和2个金属层，但本公开实施例不限于此，可以根据需要堆叠更多，比如，数百个绝缘层和数百个金属层，本公开实施例对此不作限定。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的3D存储器。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
如图18所示，本公开实施例提供一种3D存储器的制造方法，所述3D存储器包括多层沿垂直于衬底的方向堆叠的多个存储单元、一条字线，所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、环绕所述栅极的半导体层；所述3D存储器的制造方法包括：
步骤1801，提供衬底，在所述衬底上依次交替沉积多个绝缘薄膜和多个金属薄膜，进行构图形成多个堆叠结构，每个所述堆叠结构包括交替设置的绝缘层和金属层的堆叠，每个所述金属层对应一层所述存储单元中的一个晶体管，每个所述金属层包括相连的第一子部和第二子部；
步骤1802，刻蚀所述堆叠结构以形成在垂直所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述金属层的所述第一子部和第二子部以及所述绝缘层；刻蚀所述通孔内的每个第一子部形成第一通道，刻蚀所述通孔内的每个所述第二子部形成第二通道，所述第一通道、所述第二通道与所述通孔贯通；
步骤1803，在所述第一通道、第二通道和所述通孔构成的通道内沉积金属薄膜，刻蚀所述通孔内的所述金属薄膜以形成位于所述第一通道的源电极 和位于所述第二通道的漏电极；
步骤1804，在所述通孔的侧壁填充半导体薄膜以形成每个所述晶体管的半导体层，所述半导体层与每个所述源电极接触且与每个所述漏电极接触，同一个晶体管中所述源电极和所述漏电极之间的沟道为水平沟道；
步骤1805，在所述通孔内依次沉积栅极绝缘层和金属薄膜，所述金属薄膜填充所述栅极绝缘层内的通孔形成所述字线，不同层的所述晶体管的所述栅极为所述字线的一部分。
上述交替沉积绝缘薄膜和金属薄膜后形成多个绝缘薄膜和金属薄膜，且与衬底距离最远的薄膜为绝缘薄膜。
在一示例性实施例中，所述在所述第一通道、第二通道和所述通孔构成的通道内沉积金属薄膜前，还包括：
在所述第一通道、第二通道和所述通孔构成的通道的侧壁依次沉积半导体薄膜、栅绝缘薄膜；
刻蚀所述通孔内的所述金属薄膜包括：刻蚀所述通孔内的栅绝缘薄膜和金属薄膜。
上述制造过程可参考前述实施例中晶体管的制造过程，对多个金属薄膜的处理与上述晶体管制造过程中对金属薄膜的处理可以一致，此处不再赘述。
本实施例提供的3D存储器的制造方法，制造的3D存储器的半导体层上的源接触区和漏接触区的设置使得源极和漏极之间的沟道方向总体上沿着平行于衬底的方向延伸，便于实现结构简单且制作相对容易的3D堆叠存储器。另外，可以共用每个叠层的晶体管的栅极作为字线，垂直方向延伸的字线节约空间。且本实施例提供的3D存储器，可以通过调节源电极或漏电极的厚度改变沟道尺寸，工艺简便，对器件的尺寸影响小。
如图19所示，本公开实施例提供一种3D存储器的制造方法，所述3D存储器可以包括多层沿垂直于衬底的方向堆叠的存储单元、字线，所述存储单元可以包括：一个晶体管，所述晶体管可以包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、环绕所述栅极侧壁的半导体层；所述制造方法可以包括：
步骤1901，提供衬底，在所述衬底上依次交替沉积多个绝缘薄膜和多个金属薄膜，进行构图形成多个堆叠结构；每个所述堆叠结构包括交替设置的绝缘层和金属层的堆叠，每个所述金属层对应一层所述存储单元中的一个晶体管，每个所述金属层包括相连的第一子部和第二子部；
步骤1902，刻蚀所述堆叠结构以形成在垂直所述衬底的方向上贯穿所述堆叠结构的通孔，以及，形成由第一子部刻蚀得到的源电极，以及，形成由第二子部刻蚀得到的漏电极；
步骤1903，在所述通孔的侧壁依次沉积半导体薄膜以形成半导体层，所述半导体层与每个所述源电极接触且与每个所述漏电极接触；同一个晶体管中所述源电极和漏电极之间的沟道的长度方向平行于所述衬底；
步骤1904，在所述通孔内依次沉积栅极绝缘层和金属薄膜，所述金属薄膜填充所述栅极绝缘层内的通孔形成所述字线，不同层的所述晶体管的所述栅极为所述字线的一部分。
本公开实施例提供的3D存储器的制造方法，便于实现结构简单且制作相对容易的3D堆叠存储器，且本实施例提供的3D存储器，可以通过调节源电极或漏电极的厚度改变沟道尺寸，工艺简便，对晶体管的尺寸影响小。本公开实施例的制造方法利用现有成熟的制造设备即可实现，对现有工艺改进较小，可以很好地与现有制造工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开实施例提供一种3D存储器的制造方法，所述3D存储器包括多层沿垂直于衬底的方向堆叠的多个存储单元、一条字线；
所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、环绕所述栅极的半导体层；所述3D存储器的制造方法可以包括：
提供衬底，在所述衬底上依次交替沉积多个绝缘薄膜和多个导电薄膜，进行构图形成多个在平行于衬底方向间隔的堆叠结构；每个所述堆叠结构包括在垂直衬底方向交替设置的绝缘层和导电层的堆叠，每个所述导电层对应一层所述存储单元中的一个晶体管，每个所述导电层包括相连的第一子部和 第二子部；
刻蚀所述堆叠结构以形成在垂直所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层的所述第一子部和第二子部以及所述绝缘层；刻蚀所述通孔内的每个第一子部形成对应多个晶体管的多个第一通道，刻蚀所述通孔内的每个所述第二子部形成对应多个晶体管的多个第二通道，每个所述第一通道、每个所述第二通道间隔且分别与所述通孔贯通；
在各所述第一通道、各第二通道和所述通孔构成的通道内沉积金属薄膜，刻蚀去除所述通孔内的所述金属薄膜保留每个所述第一通道、每个所述第二通道内的金属膜层以形成位于多个所述第一通道的多个源电极和位于多个所述第二通道的多个漏电极；
在所述通孔的侧壁填充半导体薄膜以形成每个所述晶体管的半导体层，所述半导体层与每个所述源电极接触且与每个所述漏电极接触，同一个晶体管中所述源电极和所述漏电极之间的沟道为水平沟道；
在所述通孔内依次沉积栅极绝缘层和金属薄膜，所述金属薄膜填充所述栅极绝缘层内的通孔形成所述字线，不同层的所述晶体管的所述栅极为所述字线的一部分。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (32)

  1. 一种3D存储器，包括：多层沿垂直于衬底的方向堆叠的存储单元，字线，其中，所述字线沿着垂直所述衬底的方向延伸且贯穿不同层的所述存储单元；
    每层所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极，位于所述栅极侧壁且与所述栅极相绝缘的半导体层；其中，所述半导体层包括间隔设置的源接触区和漏接触区，所述源接触区和漏接触区之间的沟道为水平沟道。
  2. 根据权利要求1所述的3D存储器，其中，所述半导体层为环绕所述栅极的侧壁且沿着垂直与所述衬底的方向延伸的膜层。
  3. 根据权利要求1所述的3D存储器，其中，不同层的晶体管的所述源电极在垂直所述衬底的方向上间隔设置，不同层的晶体管的所述漏电极在垂直所述衬底的方向上间隔设置。
  4. 根据权利要求1所述的3D存储器，其中，不同层的晶体管的所述栅极为所述字线的一部分，不同层的晶体管对应的半导体层位于所述字线的侧壁。
  5. 根据权利要求1所述的3D存储器，其中，不同层的晶体管的所述栅极连接形成所述字线。
  6. 根据权利要求4所述的3D存储器，其中，沿着垂直所述衬底的方向延伸的所述字线为一条直线。
  7. 根据权利要求4所述的3D存储器，其中，沿着垂直所述衬底的方向延伸的所述字线不同区域的材料组分相同。
  8. 根据权利要求4所述的3D存储器，其中，沿着垂直所述衬底的方向延伸的所述字线的横截面形状大约相同。
  9. 根据权利要求1所述的3D存储器，其中，不同层的晶体管对应的半导体层位于所述字线的侧壁且分别位于沿垂直衬底的方向延伸的不同区域。
  10. 根据权利要求1所述的3D存储器，其中，同一所述晶体管的所述源 电极为源电极膜层，所述漏电极为漏电极膜层，所述漏电极膜层和源电极膜层位于同一层且间隔设置。
  11. 根据权利要求10所述的3D存储器，其中，不同晶体管的所述源电极膜层或所述漏电极膜层位于不同膜层。
  12. 根据权利要求1所述的3D存储器，其中，在平行于所述衬底的平面上，同一个所述晶体管的所述源电极和所述漏电极的正投影无交叠。
  13. 根据权利要求1所述的3D存储器，其中，在平行于所述衬底的平面上，不同晶体管的源电极和漏电极的正投影无交叠。
  14. 根据权利要求1所述的3D存储器，其中，所述源电极位于所述栅极的第一侧，所述漏电极位于所述栅极的第二侧，所述源电极和所述漏电极相向设置。
  15. 根据权利要求1至10任一所述的3D存储器，其中，不同层的所述存储单元的所述晶体管的半导体层在垂直所述衬底的方向上间隔设置。
  16. 根据权利要求15所述的3D存储器，其中，所述间隔设置的所述半导体层之间露出绝缘层，所述绝缘层为位于所述栅极和所述半导体层之间的栅绝缘层。
  17. 根据权利要求16所述的3D存储器，其中，所述间隔设置的所述半导体层之间具有隔离层，所述隔离层为通过对所述半导体层掺杂得到的绝缘层。
  18. 根据权利要求1所述的3D存储器，其中，所述字线的侧壁设置有环绕所述字线的栅绝缘层；不同层的所述晶体管的所述半导体层连续分布于所述字线的侧壁。
  19. 根据权利要求1所述的3D存储器，其中，不同层的所述存储单元中每相邻两个半导体层之间连接为一体式结构。
  20. 根据权利要求1所述的3D存储器，其中，不同层的晶体管共用一条沿着垂直所述衬底方向延伸的所述字线。
  21. 根据权利要求1所述的3D存储器，其中，不同层的晶体管共用一个沿着垂直所述衬底方向延伸的环状的栅绝缘层。
  22. 根据权利要求1所述的3D存储器，其中，不同层的晶体管共用一个沿着垂直所述衬底方向延伸的环状的半导体层。
  23. 根据权利要求1所述的3D存储器，其中，所述半导体层为金属氧化物半导体层，或所述半导体层为含硅的半导体层。
  24. 根据权利要求1所述的3D存储器，其中，不同层的所述源电极在衬底上的投影位于相同区域，不同层的所述漏电极在衬底上的投影位于相同区域；不同层的栅极在衬底上投影位于相同区域。
  25. 一种用于3D存储器的垂直晶体管，包括：衬底，设置在所述衬底上的源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、全部或部分环绕所述栅极且与所述栅极相绝缘的半导体层；其中，所述半导体层包括间隔设置的源接触区和漏接触区，所述源接触区和漏接触区之间的沟道为水平沟道。
  26. 根据权利要求25所述的用于3D存储器的垂直晶体管，其中，所述源电极的膜层和所述漏电极的膜层为同一导电膜层的不同区域，且间隔设置，所述同一导电膜层与所述衬底大约平行。
  27. 根据权利要求25所述的用于3D存储器的垂直晶体管，其中，所述半导体层的材料包括金属氧化物半导体材料。
  28. 根据权利要求25所述的用于3D存储器的垂直晶体管，其中，在平行于所述衬底的平面上，所述源电极的正投影和所述漏电极的正投影无交叠。
  29. 根据权利要求25所述的用于3D存储器的垂直晶体管，其中，所述源接触区位于所述半导体层的第一侧，所述漏接触区位于所述半导体层的第二侧，所述源电极与所述源接触区接触，所述漏电极与所述漏接触区接触，所述源电极和所述漏电极相向设置。
  30. 根据权利要求25所述的用于3D存储器的垂直晶体管，其中，所述半导体层为环状的全环绕型半导体层。
  31. 一种3D存储器的制造方法，其特征在于，所述3D存储器包括多层沿垂直于衬底的方向堆叠的多个存储单元、一条字线；
    所述存储单元包括：晶体管，所述晶体管包括源电极、漏电极、沿垂直于所述衬底的方向延伸的栅极、环绕所述栅极的半导体层；所述3D存储器 的制造方法包括：
    提供衬底，在所述衬底上依次交替沉积多个绝缘薄膜和多个导电薄膜，进行构图形成多个在平行于衬底方向间隔的堆叠结构；每个所述堆叠结构包括在垂直衬底方向交替设置的绝缘层和导电层的堆叠，每个所述导电层对应一层所述存储单元中的一个晶体管，每个所述导电层包括相连的第一子部和第二子部；
    刻蚀所述堆叠结构以形成在垂直所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层的所述第一子部和第二子部以及所述绝缘层；刻蚀所述通孔内的每个所述第一子部形成对应多个晶体管的多个第一通道，刻蚀所述通孔内的每个所述第二子部形成对应多个晶体管的多个第二通道，每个所述第一通道、每个所述第二通道间隔且分别与所述通孔贯通；
    在各所述第一通道、各第二通道和所述通孔构成的通道内沉积金属薄膜，刻蚀去除所述通孔内的所述金属薄膜保留每个所述第一通道、每个所述第二通道内的金属膜层以形成位于多个所述第一通道的多个源电极和位于多个所述第二通道的多个漏电极；
    在所述通孔的侧壁填充半导体薄膜以形成每个所述晶体管的半导体层，所述半导体层与每个所述源电极接触且与每个所述漏电极接触，同一个晶体管中所述源电极和所述漏电极之间的沟道为水平沟道；
    在所述通孔内依次沉积栅极绝缘层和金属薄膜，所述金属薄膜填充所述栅极绝缘层内的通孔形成所述字线，不同层的所述晶体管的所述栅极为所述字线的一部分。
  32. 一种电子设备，包括如权利要求1-24任一所述的3D存储器，或包括权利要求25-30任一所述的用于3D存储器的垂直晶体管。
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