WO2024082394A1 - 存储单元、3d存储器及其制备方法、电子设备 - Google Patents

存储单元、3d存储器及其制备方法、电子设备 Download PDF

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Publication number
WO2024082394A1
WO2024082394A1 PCT/CN2022/137319 CN2022137319W WO2024082394A1 WO 2024082394 A1 WO2024082394 A1 WO 2024082394A1 CN 2022137319 W CN2022137319 W CN 2022137319W WO 2024082394 A1 WO2024082394 A1 WO 2024082394A1
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Prior art keywords
electrode
semiconductor layer
substrate
gate
contact region
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PCT/CN2022/137319
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English (en)
French (fr)
Inventor
戴瑾
余泳
梁静
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北京超弦存储器研究院
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Priority to EP22955194.0A priority Critical patent/EP4380330A1/en
Priority to US18/312,389 priority patent/US11825642B1/en
Publication of WO2024082394A1 publication Critical patent/WO2024082394A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to but are not limited to the field of semiconductor technology, and in particular to a storage unit, a 3D memory and a method for preparing the same, and an electronic device.
  • the common dynamic random access memory (DRAM) storage unit structure is 1T1C type, that is, a structure in which the source of a transistor is connected to a capacitor.
  • This structure uses capacitors to store data, but because the power of the capacitor is consumed when reading, and the capacitor itself will also leak electricity, it is necessary to constantly refresh the charge in the capacitor, which consumes a lot of power.
  • miniaturization since the process of manufacturing capacitors occupies a large area, miniaturization has also become a problem.
  • the two-transistor capacitor-free memory cell (2Transistor 0Capacitor, 2T0C) uses two transistors as the unit structure, uses gate capacitance to store charge and changes transistor transconductance to store information.
  • the present disclosure provides a memory cell, the memory cell comprising: a first transistor and a second transistor disposed on a substrate, wherein:
  • the first transistor includes a first gate, a first electrode, a second electrode, and a first semiconductor layer disposed on the substrate, wherein the first gate extends in a direction parallel to the substrate;
  • the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate, and a second semiconductor layer surrounding the sidewall of the second gate, the first gate being connected to the second semiconductor layer;
  • the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, the third electrode is in contact with the second source contact region of the second semiconductor layer, the fourth electrode is in contact with the second drain contact region of the second semiconductor layer, and the channel between the second source contact region and the second drain contact region is a horizontal channel.
  • the orthographic projection of the first gate overlaps with the orthographic projection of the third electrode
  • the orthographic projection of the third electrode overlaps with the orthographic projection of the fourth electrode
  • the first gate of the first transistor and the third electrode of the second transistor are an integral structure.
  • the first gate is connected to a second source contact region of the second semiconductor layer.
  • an orthographic projection of the first electrode overlaps with an orthographic projection of the first gate.
  • the second drain contact region of the second semiconductor layer and the second source contact region of the second semiconductor layer are located on a sidewall of the second semiconductor layer, facing each other and spaced apart.
  • the second electrode surrounds and connects to the first semiconductor layer, and in a plane perpendicular to the substrate, a cross section of the second electrode has a ring-shaped opening, and the first semiconductor layer is located in the opening of the second electrode.
  • the first electrode is disposed on a side of the second electrode away from the second gate.
  • the first semiconductor layer includes a sidewall and two ends
  • the first semiconductor layer includes a first source contact region and a first drain contact region
  • the first source contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer
  • the first drain contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, or is located at the end of the two ends away from the second gate.
  • the first electrode extends along a third direction
  • the first gate extends along a second direction
  • the third electrode extends along the second direction
  • the fourth electrode extends along the third direction
  • the second direction and the third direction intersect and are parallel to the substrate.
  • an orthographic projection of the first electrode and an orthographic projection of the second electrode do not overlap; and an orthographic projection of the third electrode and an orthographic projection of the fourth electrode do not overlap.
  • the first electrode, the second electrode, and the third electrode are located on a first side of the second gate, the fourth electrode is located on a second side of the second gate, and the first side and the second side are opposite sides.
  • a distance between a surface of the first electrode close to the substrate and the substrate is smaller than a distance between a surface of the third electrode close to the substrate and the substrate, and a distance between a surface of the first electrode away from the substrate and the substrate is greater than a distance between a surface of the third electrode away from the substrate and the substrate.
  • the film layers of the third electrode and the fourth electrode are different regions of the same conductive film layer and are arranged at intervals, and the same conductive film layer is approximately parallel to the substrate.
  • the second transistor also includes: a second gate insulating layer arranged between the second gate and the second semiconductor layer and surrounding the side wall of the second gate, and along a direction perpendicular to the substrate, the length of the second semiconductor layer is less than or equal to the length of the second gate insulating layer, and is greater than or equal to the length of the third electrode, and is greater than or equal to the length of the fourth electrode.
  • the materials of the first semiconductor layer and the second semiconductor layer include metal oxide semiconductor materials.
  • the metal in the metal oxide semiconductor material includes at least one of indium, tin, zinc, aluminum, and gallium.
  • the present disclosure provides a memory cell, comprising: a read transistor and a write transistor disposed on a substrate, wherein:
  • the read transistor comprises a first gate, a first semiconductor layer, a first source electrode, and a first drain electrode; the first semiconductor layer surrounds the first gate; the first gate extends in a direction parallel to the substrate;
  • the write transistor comprises a second gate, a second semiconductor layer, a second source electrode, and a second drain electrode; the second semiconductor layer surrounds the second gate; the second gate extends in a direction perpendicular to the substrate, and the second source electrode of the write transistor is connected to the first gate of the read transistor;
  • the channel of the second semiconductor layer of the write transistor is a horizontal channel.
  • the read transistor and the write transistor are spaced apart and distributed on the substrate along a direction parallel to the substrate.
  • the second gate extends in a direction perpendicular to the substrate and has a sidewall, the second semiconductor layer surrounds the sidewall, and the second semiconductor layer includes a second source contact region;
  • the first gate extends in a direction parallel to the substrate and has a sidewall and two ends.
  • the first semiconductor layer at least surrounds the sidewall. One of the two ends extends to a second source contact region of the second semiconductor layer and contacts the second semiconductor layer.
  • the sidewall of the second semiconductor layer further includes a second drain contact region; the second source contact region and the second drain contact region are located in different regions of the sidewall of the second semiconductor layer, and the orthographic projections of the second source contact region and the second drain contact region in a plane perpendicular to the substrate have an overlapping region, so that a channel between the second source contact region and the second drain contact region is parallel to the substrate;
  • a first source contact region and a first drain contact region are provided on a sidewall of the first semiconductor layer, and a channel between the first source contact region and the first drain contact region is parallel to the substrate.
  • the present disclosure provides a 3D memory, comprising a plurality of memory cells stacked in a direction perpendicular to a substrate, wherein:
  • Each layer of the storage unit includes: a read transistor and a write transistor;
  • the read transistor comprises a first gate, a first semiconductor layer, a first source electrode and a first drain electrode, wherein the first gate extends in a direction parallel to the substrate;
  • the write transistor comprises a second gate, a second semiconductor layer, a second source electrode and a second drain electrode, wherein the second gate extends in a direction perpendicular to the substrate;
  • the second source electrode of the write transistor is connected to the first gate of the read transistor; the first semiconductor layer surrounds the first gate, and the second semiconductor layer surrounds the second gate; and the channel of the second semiconductor layer of the write transistor is a horizontal channel.
  • the read transistor and the write transistor in the same layer are spaced apart and distributed on the substrate along a direction parallel to the substrate.
  • the first gate electrode of the read transistor and the second source electrode of the write transistor are an integral structure.
  • the first gate extends along a second direction parallel to the substrate
  • the first semiconductor layer includes a first source contact region and a first drain contact region
  • the second semiconductor layer includes a second source contact region and a second drain contact region
  • Each layer of the memory cell further includes: a first bit line and a second bit line extending along a third direction parallel to the substrate, the third direction intersecting the second direction; the first bit line is connected to a first drain contact region of the first semiconductor layer, and the second bit line is connected to a second drain contact region of the second semiconductor layer;
  • Each layer of the memory cell further includes: a first word line and a second word line extending in a direction perpendicular to the substrate, respectively;
  • the first word lines are respectively connected to the first source contact regions of the first semiconductor layers of the memory cells at different layers, and the second word lines are respectively connected to the second gates of the memory cells at different layers.
  • the first word line surrounds a sidewall of each first semiconductor layer of the memory cells of different layers and is connected to a first source contact region of the sidewall of each first semiconductor layer.
  • the first gate has a sidewall, a first end, and a second end, the first end is connected to the second source contact region of the second semiconductor layer, and the first bit line is connected to the second end.
  • the present disclosure provides a method for preparing a 3D memory, wherein the 3D memory includes multiple layers of memory cells, a first word line, and a second word line stacked in a direction perpendicular to a substrate, wherein each layer of the memory cells includes: a read transistor and a write transistor, wherein the read transistor includes a first gate, a first semiconductor layer, a first source electrode, and a first drain electrode; and the write transistor includes a second gate, a second semiconductor layer, a second source electrode, and a second drain electrode.
  • the preparation method includes:
  • An insulating film and a metal film are alternately deposited on the substrate in sequence, and patterned to form a stacked structure including an insulating layer and a metal layer alternately arranged, wherein the metal layer includes a first sub-portion and a second sub-portion connected to each other, and a first drain electrode of the read transistor;
  • a semiconductor film, a gate insulating film, and a metal film completely filling the channel on the sidewalls of the channel formed by the first channel, the second channel, and the through hole in sequence, and etching the gate insulating film and the metal film in the through hole to form a first semiconductor layer, a second source electrode, a first gate electrode, and a second drain electrode located in the first channel;
  • a semiconductor film on the sidewall of the through hole to form a second semiconductor layer of the write transistor, the second semiconductor layer comprising a second source contact region and a second drain contact region that are spaced apart, the second source electrode contacts the second source contact region, and the second drain electrode contacts the second drain contact region; a channel between the second source contact region and the second drain contact region is a horizontal channel;
  • the first word line extending in a direction perpendicular to the substrate is formed by patterning, and the first source electrode of the read transistor at a different layer is a part of the first word line.
  • An embodiment of the present disclosure provides an electronic device, comprising the storage unit described in any of the above embodiments.
  • FIG. 1A is a schematic diagram of a storage unit provided by an exemplary embodiment
  • FIG1B is a cross-sectional view of the memory cell along the AA direction shown in FIG1A ;
  • FIG2 is an equivalent circuit diagram of a memory cell provided by an exemplary embodiment
  • FIG3 is a schematic diagram of an exemplary embodiment after forming a third insulating film
  • FIG4 is a schematic diagram of an exemplary embodiment after a groove is formed
  • FIG5 is a schematic diagram of an exemplary embodiment after the slot is filled
  • FIG6 is a schematic diagram of an exemplary embodiment after forming a through hole
  • FIG7A is a schematic diagram of an exemplary embodiment after a channel is formed
  • FIG. 7B is a schematic diagram of a first metal layer provided by an exemplary embodiment
  • FIG8A is a schematic diagram of an exemplary embodiment after forming a first semiconductor layer and a first gate insulating layer
  • FIG8B is a partial schematic diagram of FIG8A ;
  • FIG8C is a schematic cross-sectional view of FIG8B along the BB direction
  • FIG9A is a schematic diagram of an exemplary embodiment after forming a second metal layer
  • FIG9B is a partial schematic diagram of FIG9A ;
  • FIG9C is a schematic cross-sectional view of FIG9B along the BB direction;
  • FIG10A is a schematic diagram of an exemplary embodiment after removing the second metal layer in the through hole
  • FIG10B is a partial schematic diagram of FIG10A ;
  • FIG10C is a schematic cross-sectional view of FIG10B along the BB direction;
  • FIG. 11A is a schematic diagram of an exemplary embodiment after a gate is formed
  • FIG11B is a partial schematic diagram of FIG11A ;
  • FIG11C is a schematic cross-sectional view of FIG11B along the BB direction;
  • FIG. 12 is a schematic diagram of an exemplary embodiment after a slot 44 is formed
  • FIG. 13A is a schematic diagram of an exemplary embodiment after forming a fourth metal layer 34′;
  • FIG13B is a partial schematic diagram of FIG13A
  • FIG14A is a schematic diagram of an exemplary embodiment after a slot is formed
  • FIG14B is a partial schematic diagram of FIG14A
  • FIG14C is a schematic cross-sectional view of FIG14B along the BB direction;
  • FIG. 15 is a schematic diagram of an exemplary embodiment after forming a fifth insulating layer.
  • FIG16 is a schematic cross-sectional view of a storage unit provided by an exemplary embodiment
  • FIG17A is a schematic cross-sectional view of a 3D memory device provided by an exemplary embodiment along a direction parallel to a substrate;
  • FIG17B is a schematic cross-sectional view of a 3D memory device provided by an exemplary embodiment along a direction perpendicular to a substrate;
  • FIG. 18 is a flow chart of a method for preparing a 3D memory device according to an exemplary embodiment.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • an electrode may be a source electrode, or may be a drain electrode, and one of the two electrodes of a same transistor is a source electrode and the other is a drain electrode.
  • electrical connection includes the situation where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function includes the situation where components are connected together through an element having some kind of electrical function.
  • electrical function includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • a and B are an integrated structure
  • a film layer patterned to form a connection is an integrated structure.
  • a and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.
  • the embodiments of the present application provide a 2T0C storage unit with a new structure, which is more conducive to the design of high-density storage units in terms of space, and more conducive to industrialized storage units and 3D memory in terms of process.
  • FIG1A is a schematic diagram of a three-dimensional structure of a memory cell provided by an exemplary embodiment, which includes both a word line and a bit line.
  • FIG1B is a cross-sectional view of the memory cell shown in FIG1A in the AA direction.
  • this embodiment provides a memory cell, which may include: a first transistor and a second transistor arranged on a substrate 1, the first transistor may include a first gate 11, a first semiconductor layer 6, a first electrode 33 and a second electrode 34 arranged on the substrate 1, the second transistor may include a third electrode 51, a fourth electrode 52 and a second gate 12 extending along a first direction Z (a direction perpendicular to the substrate 1) arranged on the substrate 1, and a second semiconductor layer 9 surrounding the side wall of the second gate 12, the first gate 11 is connected to the second semiconductor layer 9; the second semiconductor layer 9 includes a second source contact region 91 and a second drain contact region 92 arranged at intervals, the third electrode 51 is in contact with the second source contact region 91, the fourth electrode 52 is in contact with the second drain contact region 92, and the channel between the second source contact region 91 and the second drain contact region 92 is a horizontal channel.
  • the gate of the second transistor is a vertical structure and the channel is a horizontal channel and is not stacked with the first transistor, which can reduce the size of the memory cell in the direction perpendicular to the substrate, and can facilitate the manufacture of a 3D stack of compact 2T0C memory cells, simplify the process, and reduce costs.
  • the non-stacked can be understood as spaced distribution on the substrate, for example, spaced distribution in a direction parallel to the substrate.
  • the second semiconductor layer 9 of the second transistor surrounds the second gate 12, and the source contact region 91 and the drain contact region 92 on the second semiconductor layer 9 are arranged so that the channel direction between the third electrode 51 and the fourth electrode 52 of the second transistor generally extends in a direction parallel to the substrate 1.
  • the third electrode 51 and the fourth electrode 52 overlap in their orthographic projections parallel to the first direction.
  • the structure of the memory is designed as a new structure, which makes the structure between the first transistor and the second transistor more compact.
  • the gate of each stacked second transistor can be connected as a word line, and the word line extending in the vertical direction makes the structure process of 2T0C simple and space-saving.
  • the horizontal channel described in the embodiment of the present application can be understood as a type of non-vertical channel.
  • the horizontal channel can be an embodiment in which the length direction of the channel or the carrier transmission direction is in a plane parallel to the substrate.
  • the horizontal channel can be a planar channel rather than a vertical channel.
  • a planar channel means that the extension direction of the carriers in the channel is generally parallel to the substrate rather than perpendicular to the substrate.
  • the channel extending in the plane may be a linear channel or a ring-shaped or arc-shaped channel, which is specifically determined by the shape of the semiconductor layer between the source electrode and the drain electrode.
  • the channels of the second transistor and the first transistor may be the horizontal channels described above.
  • the second transistor of the present application has a gate extending in the vertical direction and a horizontal channel, which can facilitate the formation of a through hole extending in the vertical direction at one time when a stacked 3D structure is made in the vertical direction, and a channel film layer of each layer of storage unit and a gate insulation layer of each layer of storage unit are formed at one time on the side wall of the through hole in sequence, and then the gate or word line is filled in the through hole, and different areas of the word line are used as gates of transistors of different layers.
  • the first transistor has a first gate 11 extending in a horizontal direction and a channel in a horizontal direction, so as to separate adjacent first transistors of the stacked multiple transistors in a vertical direction, thereby realizing a compact storage unit composed of the first transistor and the second transistor, so as to effectively realize device miniaturization.
  • the channel may be approximately parallel to the substrate 1, which depends on the relative position of the effective source electrode and the drain electrode in practical applications.
  • the outer contour of at least one of the upper surface and the lower surface of the electrode in the longitudinal cross-sectional view of the source electrode and the drain electrode is on a plane, and the plane is approximately parallel to the main surface of the substrate.
  • the second semiconductor layer 9 extends on the side wall of the second gate 12 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1.
  • the second semiconductor layer 9 surrounds each area of the side wall of the gate.
  • the second semiconductor layer 9 is ring-shaped, and in the cross section at each position of the second gate 12, the second semiconductor layer 9 is ring-shaped, and the size of the ring is adapted to the outer contour shape of the cross section of the second gate 12.
  • the second semiconductor layer 9 may be partially surrounded.
  • the semiconductor layer 9 may have a gap.
  • the first direction Z may intersect with the substrate 1.
  • intersecting with the substrate 1 means intersecting with the upper surface of the substrate 1 (i.e., the surface on which the first transistor and the second transistor are arranged), being parallel to the substrate 1 means being parallel to the upper surface of the substrate 1, and being perpendicular to the substrate 1 means being perpendicular to the upper surface of the substrate 1.
  • multiple memory cells may be stacked vertically.
  • the embodiments of the present disclosure are not limited thereto, and the first direction Z may be parallel to the substrate 1.
  • the first direction Z intersecting the substrate 1 is used as an example for explanation, but the following description can be applied to the scheme in which the first direction Z is parallel to the substrate 1, by replacing perpendicular to the substrate 1 with parallel to the first direction Z, and parallel to the substrate 1 with perpendicular to the first direction Z.
  • the second transistor may further include a second gate insulating layer 10 disposed between the second gate 12 and the second semiconductor layer 9 and surrounding the sidewall of the second gate 12, and the second semiconductor layer 9 is isolated from the second gate 12 by the second gate insulating layer 10.
  • the third electrode 51 and the fourth electrode 52 are insulated from the second gate 12 by the second gate insulating layer 10.
  • an orthographic projection of the first gate 11 may overlap with an orthographic projection of the third electrode 51 .
  • the orthographic projection of the first gate 11 may overlap with the orthographic projection of the third electrode 51, the orthographic projection of the third electrode 51 may overlap with the orthographic projection of the fourth electrode 52, and the first gate 11 of the first transistor is connected to the third electrode 51 of the second transistor.
  • the first gate 11 and the third electrode 51 may be an integral structure, that is, the first gate 11 and the third electrode 51 are formed simultaneously using the same material and through the same manufacturing process.
  • the embodiments of the present disclosure are not limited thereto, and the first gate 11 and the third electrode 51 may not be an integral structure, and the first gate 11 and the third electrode 51 may be independent electrodes.
  • the first gate 11 and the third electrode 51 are the same electrode extending in the same direction, and the electrode serves as the first gate 11 and the third electrode 51.
  • the first gate 11 extends in a direction parallel to the substrate 1 and the end thereof extends to the source contact region of the second semiconductor layer and is connected to the source contact region.
  • an orthographic projection of the first electrode 33 and an orthographic projection of the first gate 11 may overlap.
  • the second drain contact region 92 of the second semiconductor layer 9 and the second source contact region 91 of the second semiconductor layer 9 are located on a sidewall of the second semiconductor layer 9 , facing each other and spaced apart.
  • the first transistor may further include a first gate insulating layer 7 surrounding the first gate 11, and a first semiconductor layer 6 surrounding the first gate insulating layer 7.
  • the first electrode 33 is connected to the first semiconductor layer 6.
  • the first semiconductor layer 6 forms a receiving cavity
  • the first gate 11 is disposed in the receiving cavity
  • the first gate insulating layer 7 isolates the first semiconductor layer 6 and the first gate 11.
  • the accommodation cavity formed by the first semiconductor layer 6 may be a cavity having only one opening, or may be a cavity having two openings, and the cross section of the cavity is annular.
  • the second electrode 34 surrounds and connects the first semiconductor layer 6 , and in a plane perpendicular to the substrate 1 , a cross section of the second electrode 34 has a ring-shaped opening, and the first semiconductor layer 6 is located in the opening of the second electrode 34 .
  • the first electrode 33 may be disposed on a side of the second electrode 34 away from the second gate 12 ; and may be disposed on a side of the first gate 11 away from the second gate 12 .
  • the first semiconductor layer 6 may include a sidewall and two ends, and the first semiconductor layer 6 includes a first source contact region 61 and a first drain contact region 62, the first source contact region 61 is located on the sidewall of the first semiconductor layer 6 and surrounds the first semiconductor layer 6, the first drain contact region 62 is located on the sidewall of the first semiconductor layer 6 and surrounds the first semiconductor layer 6, or is located at the end of the two ends away from the second gate 12.
  • the first electrode 33, the second electrode 34, and the third electrode 51 may be located on a first side of the second gate 12
  • the fourth electrode 52 may be located on a second side of the second gate 12 and the first side and the second side are opposite sides.
  • the first electrode 33 may extend along the third direction Y.
  • the length of the second electrode 34 along the third direction Y may be less than the length of the first electrode 33 along the third direction Y.
  • the solution provided in this embodiment can disconnect the second electrodes 34 of different memory cells when forming a memory cell array.
  • the embodiments of the present disclosure are not limited thereto, and the length of the second electrode 34 along the third direction Y may be equal to or greater than the length of the first electrode 33 along the third direction Y.
  • the second electrode 34 may extend along the first direction Z.
  • an orthographic projection of the first electrode 33 and an orthographic projection of the first gate 11 may overlap.
  • the orthographic projection of the first electrode 33 and the orthographic projection of the second electrode 34 may not overlap, and the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 may not overlap.
  • a first distance between the surface of the third electrode 51 close to the substrate 1 and the substrate 1 and a second distance between the surface of the fourth electrode 52 close to the substrate 1 and the substrate 1 may be the same.
  • the embodiments of the present disclosure are not limited thereto, and the first distance and the second distance may be different.
  • the first thickness of the third electrode 51 and the second thickness of the fourth electrode 52 may be the same.
  • the embodiments of the present disclosure are not limited thereto, and the first thickness and the second thickness may be different.
  • the distance between the surface of the third electrode 51 close to the substrate 1 and the substrate 1 may be equal to the distance between the surface of the fourth electrode 52 close to the substrate 1 and the substrate 1, and the distance between the surface of the third electrode 51 away from the substrate 1 and the substrate 1 may be equal to the distance between the surface of the fourth electrode 52 away from the substrate 1 and the substrate 1.
  • the film layers of the third electrode 51 and the fourth electrode 52 may be different regions of the same conductive film layer and are arranged at intervals.
  • the same conductive film layer is approximately parallel to the substrate 1 .
  • the orthographic projection of the second gate 12 may be located outside the orthographic projection of the third electrode 51 , and the orthographic projection of the second gate 12 may be located outside the orthographic projection of the fourth electrode 52 .
  • the first direction Z may be perpendicular to the substrate 1 .
  • the third electrode 51 is located on a first side of the second gate 12
  • the fourth electrode 52 is located on a second side of the second gate 12
  • the first side and the second side are opposite sides.
  • the embodiments of the present disclosure are not limited thereto, and the third electrode 51 and the fourth electrode 52 may be located at other positions.
  • the third electrode 51 may extend along a second direction X
  • the fourth electrode 52 may extend along a third direction Y
  • the second direction X may be parallel to the substrate 1
  • the third direction Y may be parallel to the substrate 1
  • the second direction X and the third direction Y may intersect.
  • the embodiments of the present disclosure are not limited thereto, and the third electrode 51 and the fourth electrode 52 may be of other shapes.
  • the second direction X and the third direction Y may be perpendicular to each other, but the embodiments of the present disclosure are not limited thereto, and the second direction X and the third direction Y may be at other angles.
  • the cross-section of the first electrode 33 may be square, but the disclosed embodiments are not limited thereto, and the cross-section of the first electrode 33 may be other shapes, such as circular, hexagonal, and the like.
  • the cross-section of the third electrode 51 and the fourth electrode 52 may be square, but the embodiments of the present disclosure are not limited thereto, and the cross-section of the third electrode 51 and the fourth electrode 52 may be other shapes, such as circular, hexagonal, etc.
  • the third electrode 51 and the fourth electrode 52 can be connected at other positions different from the positions shown in Figure 1A.
  • the third electrode 51 is connected to the first side of the annular column formed by the second semiconductor layer 9, and the fourth electrode 52 is connected to the second side of the annular column formed by the second semiconductor layer 9, and the first side and the second side are adjacent, and so on.
  • the third electrode 51 and the fourth electrode 52 may be formed simultaneously through a single manufacturing process, but the embodiments of the present disclosure are not limited thereto and may be separately manufactured through different processes.
  • the distance between the surface of the first electrode 33 close to the substrate 1 and the substrate 1 may be smaller than the distance between the surface of the third electrode 51 close to the substrate 1 and the substrate 1, and the distance between the surface of the first electrode 33 away from the substrate 1 and the substrate 1 may be greater than the distance between the surface of the third electrode 51 away from the substrate 1 and the substrate 1.
  • the thickness of the first electrode 33 may be greater than the thickness of the third electrode 51.
  • the distance between the surface of the second electrode 34 away from the substrate 1 and the substrate 1 may be consistent with the distance between the surface of the second gate 12 away from the substrate 1 and the substrate 1.
  • the first semiconductor layer 6 and the second semiconductor layer 9 may be physically connected or not.
  • the end of the first semiconductor layer 6 is in contact with the side wall of the second semiconductor layer 9.
  • the end of the first semiconductor layer 6 is not in contact with the side wall of the second semiconductor layer 9, and the insulating layer between the two can be used to isolate them when the film layer is manufactured.
  • the first transistor is a read transistor
  • the second transistor is a write transistor.
  • the read transistor is turned on and the write transistor needs to be turned off.
  • the contact between the end of the first semiconductor layer 6 and the side wall of the second semiconductor layer 9 does not have a significant impact on the operation of the first transistor.
  • the two may be isolated in terms of spatial structure.
  • the length of the second semiconductor layer 9 may be equal to the length of the second gate 12.
  • the embodiments of the present disclosure are not limited thereto.
  • the length of the second semiconductor layer 9 may be less than or equal to the length of the second gate 12, less than or equal to the length of the second gate insulating layer 10, and the length of the second semiconductor layer 9 is greater than or equal to the length of the third electrode 51, and the length of the second semiconductor layer 9 is greater than or equal to the length of the fourth electrode 52.
  • the solution provided in this embodiment can shorten the channel length and reduce leakage.
  • the length of the second semiconductor layer 9 may be equal to the length of the second gate insulating layer 10
  • the length of the second gate insulating layer 10 may be equal to the length of the second gate 12 .
  • a length of the second gate insulating layer 10 may be smaller than a length of the second gate electrode 12 , and may be greater than or equal to a length of the second semiconductor layer 9 .
  • the first semiconductor layer 6 and the second semiconductor layer 9 may be metal oxide semiconductor layers, or semiconductor layers containing silicon.
  • the metal in the metal oxide semiconductor layer may include, but is not limited to, at least one of indium, tin, zinc, aluminum, and gallium.
  • the metal oxide semiconductor layer may include, but is not limited to, at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide.
  • the size of the channel between the third electrode 51 and the fourth electrode 52 can be controlled by the overlapping length between the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 on the plane perpendicular to the substrate 1.
  • the overlapping length between the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 is d, and the channel size can be controlled by controlling the thickness of the third electrode 51 and the fourth electrode 52 along the direction perpendicular to the substrate 1.
  • the channel size is controlled by changing the size of the through hole where the gate is located (the mask needs to be changed) or increasing the distance between the source and the drain (which will cause the transistor volume to increase).
  • This embodiment can more conveniently control the size of the channel, with small process changes and less impact on the size of the transistor.
  • an embodiment of the present disclosure provides a memory cell, including: a read transistor and a write transistor disposed on a substrate, wherein:
  • the read transistor may be a first transistor, and the read transistor includes a first gate 11, a first semiconductor layer 6, a first source electrode (which may be a second electrode 34), and a first drain electrode (which may be a first electrode 33); the first semiconductor layer 6 surrounds the first gate 11;
  • the write transistor may be a second transistor, the write transistor comprising a second gate 12, a second semiconductor layer 9, a second source electrode (which may be a third electrode 51), and a second drain electrode (which may be a fourth electrode 52); the second semiconductor layer 9 surrounds the second gate 12; the second source electrode of the write transistor is connected to the first gate 11 of the read transistor;
  • the channel of the second semiconductor layer 9 of the write transistor is a horizontal channel.
  • the second gate 12 extends in a direction perpendicular to the substrate 1 and has a sidewall, the second semiconductor layer 9 surrounds the sidewall, and the second semiconductor layer 9 includes a second source contact region 91;
  • the first gate 11 extends in a direction parallel to the substrate 1 and has a sidewall and two ends.
  • the first semiconductor layer 6 at least surrounds the sidewall. One of the two ends extends to the second source contact region 91 of the second semiconductor layer 9 and contacts the second semiconductor layer 9.
  • the sidewall of the second semiconductor layer 9 further includes a second drain contact region 92; the second source contact region 91 and the second drain contact region 92 are located in different regions of the sidewall of the second semiconductor layer 9, and the orthographic projections of the second source contact region 91 and the second drain contact region 92 in a plane perpendicular to the substrate 1 have an overlapping region, so that the channel between the second source contact region 91 and the second drain contact region 92 is parallel to the substrate 1;
  • the sidewall of the first semiconductor layer 6 may have a first source contact region 61 and a first drain contact region 62 , and a channel between the first source contact region 61 and the first drain contact region 62 is parallel to the substrate.
  • Fig. 2 is a schematic diagram of an equivalent circuit of a memory cell according to an embodiment of the present disclosure.
  • the first transistor can be used as a read transistor
  • the second transistor can be used as a write transistor
  • the first electrode 33 can be connected to a read bit line
  • the second electrode 34 can be connected to a read word line
  • the second gate 12 can be connected to a write word line
  • the fourth electrode 52 can be connected to a write bit line.
  • a voltage is applied to the write word line (i.e., the second gate 12), the channel is turned on, and the third electrode 51 and the fourth electrode 52 are connected.
  • the read and write process is as follows: 1) When writing "1", a read voltage is applied to the write bit line (i.e., the fourth electrode 52), and a charge is injected into the storage node (the storage node is between the first gate 11 and the third electrode 51, as indicated by the arrow in Figure 2), and the first transistor is turned on; when reading "1", a read voltage is applied to the read word line (i.e., the second electrode 34) in the read tube.
  • the peripheral circuit Since there is no charge in the storage node, no or very small current flows between the read bit line (i.e., the first electrode 33) and the read word line (i.e., the second electrode 34), and the peripheral circuit amplifies and identifies the current to complete the process of reading "0".
  • the technical solution of this embodiment is explained below by showing the preparation process of the substrate in this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology.
  • the "photolithography process” mentioned in this embodiment includes coating of film layer, mask exposure and development, which is a mature preparation process in the relevant technology.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.
  • thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film” does not require a patterning process or a photolithography process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” also requires a patterning process or a photolithography process during the entire production process, it is called a “thin film” before the patterning process and a "layer” after the patterning process. The "layer” after the patterning process or the photolithography process contains at least one "pattern".
  • the preparation process of the storage unit may include:
  • a first insulating film, a first metal film, and a second insulating film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4, as shown in FIG. 3 .
  • the substrate 1 can be made of glass, silicon, flexible materials, etc.
  • the flexible material can be made of polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film.
  • the substrate 1 can be a single-layer structure or a multi-layer stacked structure.
  • the substrate of the stacked structure can include: flexible material/inorganic material/flexible material.
  • the inorganic material can be any one or more of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON).
  • the substrate 1 can be a semiconductor substrate; for example, it can include at least one single semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art.
  • a single semiconductor material for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.
  • III-V compound semiconductor material for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.
  • the first insulating film and the second insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9.
  • they may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • the first insulating film and the second insulating film may be made of the same material or different materials.
  • the first metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a first slot P1 and a second slot P2, as shown in FIG4.
  • the first slot P1 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the second slot P2 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4.
  • the first metal layer 3 may include a first sub-portion 31 extending along the second direction X, a second sub-portion 32 extending along the third direction Y, and a first electrode 33 extending along the third direction Y, and the first sub-portion 31 connects the second sub-portion 32 and the first electrode 33.
  • the cross-sections of the first insulating layer 2 , the first metal layer 3 , and the second insulating layer 4 may be H-shaped.
  • first slot P1 and the second slot P2 may have the same size and shape, but the embodiments of the present disclosure are not limited thereto, and the first slot P1 and the second slot P2 may have different sizes and shapes.
  • the pattern of the first metal layer 3 is only an example and may be a pattern of other shapes.
  • the current second sub-portion 32 is divided into two parts along the extension direction of the first sub-portion 31 , and only one of the parts may be retained as the second sub-portion 32 .
  • a third insulating film is deposited to form a third insulating layer 5 , and the third insulating layer 5 fills the first groove P1 and the second groove P2 , as shown in FIG. 5 .
  • the third insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • the third insulating film and the first insulating film and the second insulating film may be made of the same material or different materials.
  • the subsequent fourth insulating film is similar and will not be described in detail.
  • a through hole 41 penetrating the first insulating layer 2, the first metal layer 3 and the second insulating layer 4 is formed, and on a plane parallel to the substrate 1, the orthographic projection of the through hole 41 may overlap with the orthographic projection of the first sub-portion 31, and the orthographic projection of the through hole 41 may overlap with the orthographic projection of the second sub-portion 32, as shown in FIG6.
  • the cross-section of the through hole 41 shown in FIG6 on a plane parallel to the substrate 1 is a quadrilateral, but the embodiments of the present disclosure are not limited thereto, and the cross-section of the through hole 41 on a plane parallel to the substrate 1 may be other shapes, such as a circle, a pentagon, a hexagon, etc.
  • the first sub-portion 31, the second sub-portion 32, and the connection between the first electrode 33 and the first sub-portion 31 in the first metal layer 3 are selectively etched away.
  • the first electrode 33 remains in the first metal layer 3, and the first electrode 33 is provided with a third groove P3 facing the first sub-portion 31 (the first sub-portion 31 has been etched away), as shown in FIGS. 7A and 7B.
  • a first channel 42 formed by the area where the selectively etched first sub-portion 31 is located, a second channel 43 formed by the area where the second sub-portion 32 is located, and the through hole 41 are formed.
  • the first channel 42 is connected to the through hole 41
  • the second channel 43 is connected to the through hole 41.
  • a first semiconductor film and a first gate oxide film are sequentially deposited to form a first semiconductor layer 6 and a first gate insulating layer 7, as shown in FIGS. 8A, 8B, and 8C, wherein FIG. 8C is a cross-sectional view of FIG. 8B along the BB direction, and only shows the first semiconductor layer 6 and the first gate insulating layer 7.
  • the first semiconductor layer 6 and the first gate insulating layer 7 serve as the channel walls of the channel, and the first semiconductor layer 6 surrounds the first gate insulating layer 7.
  • the first gate oxide film may be a High-K dielectric material.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, and hafnium oxide.
  • the first semiconductor film as a channel layer may be a film layer containing silicon, or a metal oxide semiconductor, wherein the metal oxide semiconductor includes but is not limited to at least one of the following materials: IGZO, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO).
  • ITO Indium Tin Oxide
  • IZO indium zinc oxide
  • the subsequent second semiconductor film is similar and will not be repeated.
  • the first semiconductor film and the first gate oxide film may be deposited by an atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • FIG. 9C is a cross-sectional view of FIG. 9B along the BB direction, and only shows the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8. At this time, the first gate insulating layer 7 surrounds the second metal layer 8.
  • the second metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the second metal film may be the same as or different from the first metal film.
  • Figure 10C is a cross-sectional view of Figure 10B along the BB direction, and only shows the first semiconductor layer 6, the first gate insulating layer 7 and the second metal layer 8.
  • the second metal layer 8 located in the first channel 42 serves as the third electrode 51 of the second transistor
  • the second metal layer 8 located in the second channel 43 serves as the fourth electrode 52 of the second transistor, and the third electrode 51 and the fourth electrode 52 are disconnected from each other.
  • a second semiconductor film, a second gate oxide film and a third metal film are sequentially deposited on the sidewalls of the through hole 41 obtained by the above etching to form a second semiconductor layer 9, a second gate insulating layer 10 and a second gate 12 respectively, and the second gate insulating layer 10 surrounds the second gate 12, the second semiconductor layer 9 surrounds the second gate insulating layer 10, and the second gate 12 completely fills the area surrounded by the second gate insulating layer 10.
  • Figure 11C is a cross-sectional view of Figure 11B along the BB direction, and only shows the first semiconductor layer 6, the first gate insulating layer 7, the second semiconductor layer 9, the second gate insulating layer 10, the second metal layer 8 (third electrode 51, fourth electrode 52), and the second gate 12.
  • the second gate oxide film may be a High-K dielectric material.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, and hafnium oxide.
  • the materials of the second gate oxide film and the first gate oxide film may be the same or different.
  • the second semiconductor thin film may be made of the same material as the first semiconductor thin film.
  • the third metal film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).
  • the third metal film may be the same as or different from the first metal film and the second metal film.
  • the subsequent fourth metal film is similar and will not be described in detail.
  • a slot structure 44 as shown in FIG. 12 is etched, but the first semiconductor layer 6 and the portion included in the first semiconductor layer 6 are not etched.
  • the slot structure 44 penetrates each film layer on the substrate 1, and on a plane perpendicular to the substrate 1, the orthographic projection of the slot structure 44 is located outside the orthographic projection of the first electrode 33, outside the orthographic projection of the through hole 41, and outside the orthographic projection of the fourth electrode 52.
  • a fourth metal film is deposited in the slot structure 44 to form a fourth metal layer 34' filling the slot structure 44, as shown in FIG. 13A and FIG. 13B.
  • a fourth slot P4 and a fifth slot P5 penetrating the fourth metal layer 34' are formed, as well as a second electrode 34, as shown in FIG14A. Similar to the first slot P1 and the second slot P2, the fourth slot P4 and the fifth slot P5 are respectively located on both sides of the fourth metal layer 34', the length of the second electrode 34 along the third direction Y is less than the length of the first electrode 33 along the third direction Y, and the second electrode 34 surrounds the first semiconductor layer 6, as shown in FIG14B.
  • FIG14C is a cross-sectional view of FIG14B along the BB direction, and it can be seen that the main structures of the first transistor and the second transistor are basically prepared.
  • a fourth insulating film is deposited to form a fourth insulating layer 55 , and the fourth insulating layer 55 fills the fourth groove P4 and the fifth groove P5 , as shown in FIG. 15 .
  • the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7 may exist in the second channel 43.
  • the embodiment of the present disclosure is not limited thereto, and the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7 may not exist in the second channel 43 (except for the area intersecting with the through hole 41), that is, the first gate insulating layer 7 and the first semiconductor layer 6 in the second channel 43 may be removed.
  • the first gate insulating layer 7 and the first semiconductor layer 6 in the second channel 43 may be retained.
  • a patterning process can be used to form an H-shaped first metal layer 3.
  • a second insulating film is deposited to form a second insulating layer 4, and there is no need to form the first groove P1 and the second groove P2 by groove formation, and there is no need to deposit a third insulating film.
  • FIG16 is a schematic cross-sectional view of a memory cell provided by another exemplary embodiment.
  • the memory cell includes a first transistor and a second transistor.
  • the first transistor may include a first electrode 33, a second electrode 34, and a first gate 11, as well as a first gate insulating layer 7 surrounding the first gate 11 and a first semiconductor layer 6 surrounding the first gate insulating layer 7;
  • the second transistor may include a third electrode 51, a fourth electrode 54, and a second gate 12, as well as a second semiconductor layer 9 extending along a first direction Z, and a second gate insulating layer 10 isolating the second semiconductor layer 9 and the second gate 12.
  • the thickness of the fourth electrode 52 may be greater than the thickness of the third electrode 51.
  • the present disclosure also provides an electronic device, including the storage unit described in any of the above embodiments.
  • the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include a memory in a computer, etc., which is not limited here.
  • FIG17A is a schematic plan view of a 3D memory provided by an embodiment of the present disclosure
  • FIG17B is a schematic cross-sectional view of a 3D memory provided by an embodiment of the present disclosure.
  • this embodiment provides a 3D memory, which may include multiple layers of memory cells stacked in a direction perpendicular to a substrate 1, wherein:
  • Each layer of the storage unit may include: a read transistor and a write transistor; the read transistor may be a first transistor, and the write transistor may be a second transistor;
  • the read transistor includes a first gate 11, a first semiconductor layer 6, a first source electrode (which may be a second electrode 34) and a first drain electrode (which may be a first electrode 33), and the first gate 11 may extend in a direction parallel to the substrate 1;
  • the write transistor includes a second gate 12, a second semiconductor layer 9, a second source electrode (which may be a third electrode 51) and a second drain electrode (which may be a fourth electrode 52), and the second gate 12 may extend in a direction perpendicular to the substrate 1;
  • the second source electrode of the write transistor is connected to the first gate electrode 11 of the read transistor; the first semiconductor layer 6 surrounds the first gate electrode 11, and the second semiconductor layer 9 surrounds the second gate electrode 12; and the channel of the second semiconductor layer 9 of the write transistor is a horizontal channel.
  • the second semiconductor layer of the write transistor surrounds the second gate, and the source contact area and the drain contact area on the second semiconductor layer are arranged so that the channel direction between the source and the drain generally extends in a direction parallel to the substrate.
  • the second transistor is not stacked with the first transistor, and the structure between the first transistor and the second transistor is more compact, which can reduce the size of the memory cell in the direction perpendicular to the substrate, and can facilitate the manufacture of a 3D stack of 2T0C memory cells with a compact structure, simplify the process, and reduce costs.
  • the read transistor and the write transistor in the same layer are distributed on the substrate 1 at intervals along a direction parallel to the substrate 1 .
  • the first gate electrode 11 of the read transistor and the second source electrode of the write transistor may be an integral structure, but are not limited thereto and may be two independent electrodes.
  • the first gate 11 may extend along a second direction parallel to the substrate 1;
  • the first semiconductor layer 6 may include a first source contact region 61 and a first drain contact region 62
  • the second semiconductor layer 9 may include a second source contact region 91 and a second drain contact region 92 ;
  • Each layer of the memory cell may further include: a first bit line 330 extending along a third direction parallel to the substrate 1, and a second bit line 520, wherein the third direction intersects the second direction; the first bit line 330 is connected to the first drain contact region 62 of the first semiconductor layer 6, and the second bit line 520 is connected to the second drain contact region 92 of the second semiconductor layer 9;
  • Each layer of the memory cell may further include: a first word line 340 and a second word line 120 extending in a direction perpendicular to the substrate 1 respectively;
  • the first word lines 340 are respectively connected to the first source contact regions 61 of the first semiconductor layers 6 of the memory cells at different layers, and the second word lines 120 are respectively connected to the second gates 12 of the memory cells at different layers.
  • the second gates 12 of the memory cells at different layers may be part of the second word lines 120.
  • the solution provided in this embodiment can use the second gate connection of each stacked write transistor as a word line.
  • the word line extending in the vertical direction makes the structure process of 2T0C simple and saves space.
  • the first word line 340 surrounds the sidewall of each first semiconductor layer 6 of the memory cells of different layers and is connected to the first source contact region 61 of the sidewall of each first semiconductor layer 6 .
  • the first gate 11 may have a sidewall, a first end, and a second end. The first end is connected to the second source contact region 91 of the second semiconductor layer 9 , and the first bit line 330 is connected to the second end.
  • the second semiconductor layer 9 of the write transistors at different layers may be an integrated structure.
  • write transistors in different layers may share a ring-shaped second semiconductor layer 9 extending in a direction perpendicular to the substrate 1 .
  • the write transistor may further include a second gate insulating layer 10 surrounding the second gate 12 , and the second semiconductor 9 surrounds the second gate insulating layer 10 .
  • write transistors in different layers may share a ring-shaped second gate insulating layer 10 extending in a direction perpendicular to the substrate 1 .
  • the projections of the first gates 11 of different layers on the substrate 1 may be located in the same area, the projections of the first source electrodes of different layers on the substrate 1 may be located in the same area, the projections of the first drain electrodes of different layers on the substrate 1 may be located in the same area, the projections of the second gates 12 of different layers on the substrate 1 may be located in the same area, the projections of the second source electrodes of different layers on the substrate 1 may be located in the same area, and the projections of the second drain electrodes of different layers on the substrate 1 may be located in the same area.
  • the structures of the read transistor and the write transistor in the above 3D memory may refer to the structures of the first transistor and the second transistor in the above-mentioned embodiments, which will not be described in detail here.
  • an embodiment of the present disclosure provides a method for preparing a 3D memory, wherein the 3D memory includes multiple layers of memory cells, a first word line, and a second word line stacked in a direction perpendicular to a substrate, wherein each layer of the memory cells includes: a read transistor and a write transistor, wherein the read transistor includes a first gate, a first semiconductor layer, a first source electrode, and a first drain electrode; and the write transistor includes a second gate, a second semiconductor layer, a second source electrode, and a second drain electrode.
  • the preparation method may include:
  • Step 1801 providing a substrate, alternately depositing an insulating film and a metal film on the substrate, and patterning to form a stacked structure including alternately arranged insulating layers and metal layers, wherein the metal layer includes a first sub-portion and a second sub-portion connected to each other, and a first drain electrode of the read transistor;
  • Step 1802 etching the stack structure to form a through hole penetrating the stack structure, etching the first sub-portion to form a first channel, etching the second sub-portion to form a second channel, the first channel and the second channel being connected to the through hole;
  • Step 1803 depositing a semiconductor film, a gate insulating film, and a metal film completely filling the channel on the sidewalls of the channel formed by the first channel, the second channel, and the through hole in sequence, and etching the gate insulating film and the metal film in the through hole to form a first semiconductor layer, a second source electrode, a first gate electrode, and a second drain electrode located in the first channel;
  • Step 1804 depositing a semiconductor film on the sidewall of the through hole to form a second semiconductor layer of the write transistor, the second semiconductor layer comprising a second source contact region and a second drain contact region that are spaced apart, the second source electrode contacts the second source contact region, and the second drain electrode contacts the second drain contact region; the channel between the second source contact region and the second drain contact region is a horizontal channel;
  • Step 1805 depositing a metal film in the through hole to completely fill the through hole to form the second word line, and the second gate of the write transistor at a different layer is a part of the second word line;
  • Step 1806 patterning to form the first word line extending in a direction perpendicular to the substrate, wherein the first source electrodes of the read transistors at different layers are part of the first word line.
  • the 3D memory prepared by the preparation method of the 3D memory provided by the embodiment of the present disclosure has a gate of the second transistor of a vertical structure and a channel of a horizontal channel that is not stacked with the first transistor, which can reduce the size of the memory cell in the vertical substrate direction, and can facilitate the manufacture of a 3D stack of compact 2T0C memory cells, simplify the process, and reduce costs.
  • the 3D memory provided by the present embodiment can change the channel size by adjusting the thickness of the source or drain, and the process is simple and has little effect on the size of the transistor.
  • the preparation method of the embodiment of the present disclosure can be implemented using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.

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Abstract

存储单元、3D存储器及其制备方法、电子设备，涉及半导体技术领域，所述存储单元包括：设置在衬底（1）上的第一晶体管和第二晶体管，第一晶体管包括设置在衬底上的第一栅极（11）、第一电极（33）、第二电极（34）、第一半导体层（6）；第二晶体管包括设置在衬底（1）上的第三电极（51）、第四电极（52）、沿垂直于衬底（1）的方向延伸的第二栅极（12），以及，环绕所述第二栅极（12）侧壁的第二半导体层（9），所述第二半导体层（9）包括间隔设置的第二源接触区域（91）和第二漏接触区域（92），所述第二源接触区域（91）和第二漏接触区域（92）之间的沟道为水平沟道。

Description

存储单元、3D存储器及其制备方法、电子设备
本申请要求于2022年10月18日提交中国专利局、申请号为202211269945.4、发明名称为“一种存储单元、3D存储器及其制备方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域，尤指一种存储单元、3D存储器及其制备方法、电子设备。
背景技术
目前，常见的动态随机存取存储器(Dynamic Random Access Memory，DRAM)存储单元结构为1T1C类型，即一个晶体管源极接一个电容的结构。该结构利用电容来存储数据，但由于读取时会消耗电容器的电量，且本身电容也会漏电，因此需要不断地刷新电容中的电荷，功耗较大。另外，由于制造电容的工艺占用面积较大，尺寸微缩也成为难题。
双晶体管无电容存储单元(2Transistor 0Capacitor，2T0C)使用两个晶体管作为单元结构，利用栅电容存储电荷并改变晶体管跨导存储信息。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种存储单元，所述存储单元包括：设置在衬底上的第一晶体管和第二晶体管，其中：
所述第一晶体管包括设置在所述衬底上的第一栅极、第一电极、第二电极、第一半导体层，所述第一栅极沿平行于所述衬底的方向延伸；
所述第二晶体管包括设置在所述衬底上的第三电极、第四电极、沿垂直于衬底的方向延伸的第二栅极，以及，环绕所述第二栅极侧壁的第二半导体层，所述第一栅极与所述第二半导体层连接；所述第二半导体层包括间隔设置的第二源接触区域和第二漏接触区域，所述第三电极与所述第二半导体层的所述第二源接触区域接触，所述第四电极与所述第二半导体层的所述第二漏接触区域接触，所述第二源接触区域和第二漏接触区域之间的沟道为水平沟道。在一示例性实施例中，在垂直于所述衬底的平面上，所述第一栅极的正投影与所述第三电极的正投影存在交叠，所述第三电极的正投影与所述第四电极的正投影存在交叠，所述第一晶体管的第一栅极和所述第二晶体管的第三电极为一体结构。。
在一示例性实施例中，所述第一栅极与所述第二半导体层的第二源接触区域连接。
在一示例性实施例中，在垂直于所述衬底的平面上，所述第一电极的正投影与所述第一栅极的正投影存在交叠。
在一示例性实施例中，所述第二半导体层的第二漏接触区域与所述第二半导体层的第二源接触区域位于所述第二半导体层的侧壁相向且间隔设置。
在一示例性实施例中，所述第二电极环绕且连接所述第一半导体层，在垂直于所述衬底的平面上，所述第二电极的截面具有环形的开口，且所述第一半导体层位于所述第二电极的开口内。
在一示例性实施例中，所述第一电极设置在所述第二电极远离所述第二栅极一侧。
在一示例性实施例中，所述第一半导体层包括侧壁和两个端部，所述第一半导体层包括第一源接触区域和第一漏接触区域，所述第一源接触区域位于所述第一半导体层的侧壁且环绕所述第一半导体层，所述第一漏接触区域位于所述第一半导体层的侧壁且环绕所述第一半导体层，或者位于所述两个端部中远离所述第二栅极的端部。
在一示例性实施例中，所述第一电极沿第三方向延伸，所述第一栅极沿第二方向延伸，所述第三电极沿第二方向延伸，所述第四电极沿第三方向延 伸，所述第二方向和所述第三方向交叉且平行于所述衬底。
在一示例性实施例中，在平行于所述衬底的平面上，所述第一电极的正投影和所述第二电极的正投影无交叠；所述第三电极的正投影和所述第四电极的正投影无交叠。
在一示例性实施例中，在垂直于所述衬底的截面上，所述第一电极、所述第二电极、所述第三电极位于所述第二栅极的第一侧，所述第四电极位于所述第二栅极的第二侧，且所述第一侧和所述第二侧为相对的两侧。
在一示例性实施例中，所述第一电极靠近所述衬底一侧的表面与所述衬底的距离小于所述第三电极靠近所述衬底一侧的表面与所述衬底的距离，所述第一电极远离所述衬底一侧的表面与所述衬底的距离大于所述第三电极远离所述衬底一侧的表面与所述衬底的距离。
在一示例性实施例中，所述第三电极和所述第四电极的膜层为同一导电膜层的不同区域，且间隔设置，所述同一导电膜层与所述衬底大约平行。
在一示例性实施例中，所述第二晶体管还包括：设置在所述第二栅极和所述第二半导体层之间环绕所述第二栅极侧壁的第二栅绝缘层，沿垂直于所述衬底的方向，所述第二半导体层的长度小于等于所述第二栅绝缘层的长度，且，大于等于所述第三电极的长度，且，大于等于所述第四电极的长度。
在一示例性实施例中，所述第一半导体层和第二半导体层的材料包括金属氧化物半导体材料。
在一示例性实施例中，所述金属氧化物半导体材料中的金属包括：铟、锡、锌、铝、镓中的至少之一。
本公开实施例提供一种存储单元，包括：设置在衬底上的读晶体管和写晶体管，其中，
所述读晶体管包含第一栅极、第一半导体层、第一源电极、第一漏电极；所述第一半导体层环绕所述第一栅极；所述第一栅极沿平行于所述衬底的方向延伸；
所述写晶体管包含第二栅极、第二半导体层、第二源电极、第二漏电极；所述第二半导体层环绕所述第二栅极；所述第二栅极沿垂直于所述衬底的方 向延伸，所述写晶体管的第二源电极连接所述读晶体管的第一栅极；
所述写晶体管的第二半导体层的沟道为水平沟道。
在一示例性实施例中，所述读晶体管和写晶体管在所述衬底上沿着平行于所述衬底的方向间隔分布。
在一示例性实施例中，所述第二栅极沿着垂直衬底的方向延伸且具有侧壁，所述第二半导体层环绕所述侧壁，所述第二半导体层包括第二源接触区域；
所述第一栅极沿着平行于所述衬底的方向延伸且具有侧壁和两个端部，所述第一半导体层至少环绕所述侧壁，所述两个端部的其中一个端部延伸到所述第二半导体层的第二源接触区域与所述第二半导体层接触。
在一示例性实施例中，所述第二半导体层的侧壁还包括第二漏接触区域；所述第二源接触区域和所述第二漏接触区域位于所述第二半导体层的侧壁的不同区域，且所述第二源接触区域和第二漏接触区域在垂直衬底的平面内的正投影具有重叠区域，使得所述第二源接触区域和所述第二漏接触区域之间的沟道平行于所述衬底；
所述第一半导体层的侧壁具有第一源接触区域和第一漏接触区域，所述第一源接触区域和第一漏接触区域之间的沟道平行于所述衬底。
本公开实施例提供一种3D存储器，包括多层沿垂直于衬底的方向堆叠的存储单元，其中，
每层所述存储单元包括：读晶体管和写晶体管；
所述读晶体管包含第一栅极、第一半导体层，第一源电极和第一漏电极，所述第一栅极沿平行于所述衬底的方向延伸；所述写晶体管包含第二栅极、第二半导体层，第二源电极和第二漏电极，所述第二栅极沿垂直于所述衬底的方向延伸；
所述写晶体管的第二源电极与所述读晶体管的第一栅极相连；所述第一半导体层环绕所述第一栅极，所述第二半导体层环绕所述第二栅极；所述写晶体管的第二半导体层的沟道为水平沟道。
在一示例性实施例中，同层的所述读晶体管和写晶体管在所述衬底上沿 着平行于所述衬底的方向间隔分布。
在一示例性实施例中，所述读晶体管的第一栅极与所述写晶体管的第二源电极为一体结构。
在一示例性实施例中，所述第一栅极沿着平行于所述衬底的第二方向延伸；
所述第一半导体层包括第一源接触区域和第一漏接触区域，所述第二半导体层包括第二源接触区域和第二漏接触区域；
每层所述存储单元还包括：沿着平行于所述衬底的第三方向延伸的第一位线，和第二位线，所述第三方向与所述第二方向交叉；所述第一位线与所述第一半导体层的第一漏接触区域连接，所述第二位线与所述第二半导体层的第二漏接触区域连接；
每层所述存储单元还包括：分别沿着垂直于所述衬底的方向延伸的第一字线和第二字线；
所述第一字线分别与不同层的所述存储单元的第一半导体层的第一源接触区域连接，所述第二字线分别与不同层的所述存储单元的第二栅极连接。
在一示例性实施例中，所述第一字线环绕不同层的所述存储单元的每个第一半导体层的侧壁且与每个第一半导体层的侧壁的第一源接触区域连接。
在一示例性实施例中，所述第一栅极具有侧壁、第一端部和第二端部，所述第一端部与所述第二半导体层的第二源接触区域连接，所述第一位线与所述第二端部连接。
本公开实施例提供一种3D存储器的制备方法，所述3D存储器包括多层沿垂直于衬底的方向堆叠的存储单元、第一字线和第二字线，每层所述存储单元包括：读晶体管和写晶体管，所述读晶体管包含第一栅极、第一半导体层，第一源电极和第一漏电极；所述写晶体管包含第二栅极、第二半导体层，第二源电极和第二漏电极，所述制备方法包括：
提供衬底；
在所述衬底上依次交替沉积绝缘薄膜和金属薄膜，进行构图形成包括交替设置的绝缘层和金属层的堆叠结构，所述金属层包括相连的第一子部和第 二子部，以及，所述读晶体管的第一漏电极；
刻蚀所述堆叠结构以形成贯穿所述堆叠结构的通孔，刻蚀所述第一子部形成第一通道，刻蚀所述第二子部形成第二通道，所述第一通道、所述第二通道与所述通孔贯通；
在所述第一通道、第二通道和所述通孔构成的通道的侧壁依次沉积半导体薄膜、栅绝缘薄膜和完全填充所述通道的金属薄膜，刻蚀所述通孔内的所述栅绝缘薄膜和金属薄膜以形成位于所述第一通道的第一半导体层、第二源电极、第一栅极和位于所述第二通道的第二漏电极；
在所述通孔的侧壁沉积半导体薄膜以形成所述写晶体管的第二半导体层，所述第二半导体层包括间隔设置的第二源接触区域和第二漏接触区域，所述第二源电极与所述第二源接触区域接触，所述第二漏电极与所述第二漏接触区域接触；所述第二源接触区域和所述第二漏接触区域之间的沟道为水平沟道；
在所述通孔内沉积金属薄膜完全填充所述通孔以形成所述第二字线，不同层的所述写晶体管的第二栅极为所述第二字线的一部分；
构图形成沿着垂直于所述衬底的方向延伸的所述第一字线，不同层的所述读晶体管的第一源电极为所述第一字线的一部分。
本公开实施例提供一种电子设备，包括上述任一实施例所述的存储单元。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对技术方案的限制。
图1A为一示例性实施例提供的存储单元示意图；
图1B为图1A所示存储单元AA方向的截面图；
图2为一示例性实施例提供的存储单元的等效电路图；
图3为一示例性实施例提供的形成第三绝缘薄膜后的示意图；
图4为一示例性实施例提供的形成开槽后的示意图；
图5为一示例性实施例提供的填充所述开槽后的示意图；
图6为一示例性实施例提供的形成通孔后的示意图；
图7A为一示例性实施例提供的形成通道后的示意图；
图7B为一示例性实施例提供的第一金属层的示意图；
图8A为一示例性实施例提供的形成第一半导体层和第一栅绝缘层后的示意图；
图8B为图8A的局部示意图；
图8C为图8B沿BB方向的截面示意图；
图9A为一示例性实施例提供的形成第二金属层后的示意图；
图9B为图9A的局部示意图；
图9C为图9B沿BB方向的截面示意图；
图10A为一示例性实施例提供的去除通孔内的第二金属层后的示意图；
图10B为图10A的局部示意图；
图10C为图10B沿BB方向的截面示意图；
图11A为一示例性实施例提供的形成栅极后的示意图；
图11B为图11A的局部示意图；
图11C为图11B沿BB方向的截面示意图；
图12为一示例性实施例提供的形成插槽44后的示意图；
图13A为一示例性实施例提供的形成第四金属层34’后的示意图；
图13B为图13A的局部示意图；
图14A为一示例性实施例提供的形成插槽后的示意图；
图14B为图14A的局部示意图；
图14C为图14B沿BB方向的截面示意图；
图15为一示例性实施例提供的形成第五绝缘层后的示意图
图16为一示例性实施例提供的存储单元的截面示意图；
图17A为一示例性实施例提供的3D存储器沿平行于衬底方向的截面示意图；
图17B为一示例性实施例提供的3D存储器沿垂直于衬底方向的截面示意图；
图18为一示例性实施例提供的3D存储器制备方法流程图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
因此，本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
本公开中，电极可以是源电极，或者，可以是漏电极，同一晶体管的两个电极其中之一为源电极，另一为漏电极。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开实施例中的“A和B为一体结构”可以是指在微观结构上无明显的断层或间隙等明显的分界界面。一般地，在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构。
本申请实施例针对2T0C的存储单元，提供一种新型结构的2T0C，在空间上更加有利于高密度存储单元的设计，在工艺上更有利于产业化的存储单元，以及3D存储器。
图1A为一示例性实施例提供的一个存储单元同时包含字线、位线的立 体结构示意图。图1B为图1A所示存储单元在AA方向的截面图。如图1A所示，本实施例提供一种存储单元，可以包括：设置在衬底1上的第一晶体管和第二晶体管，所述第一晶体管可以包括设置在所述衬底1上的第一栅极11、第一半导体层6、第一电极33和第二电极34，所述第二晶体管可以包括设置在所述衬底1上的第三电极51、第四电极52和沿第一方向Z(垂直于衬底1的方向)延伸的第二栅极12，以及，环绕所述第二栅极12侧壁的第二半导体层9，所述第一栅极11与所述第二半导体层9连接；所述第二半导体层9包括间隔设置的第二源接触区域91和第二漏接触区域92，所述第三电极51与所述第二源接触区域91接触，所述第四电极52与所述第二漏接触区域92接触，所述第二源接触区域91和第二漏接触区域92之间的沟道为水平沟道。
本申请提供的新型结构的2T0C设计方案，第二晶体管的栅极为垂直结构且沟道为水平沟道与第一晶体管不堆叠，可以减小垂直衬底方向存储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺，降低成本。所述不堆叠可以理解为在衬底上间隔分布，比如，在平行于衬底的方向上间隔分布。
本实施例提供的方案，第二晶体管的第二半导体层9环绕所述第二栅极12，第二半导体层9上的源接触区域91和漏接触区域92的设置使得第二晶体管的第三电极51和第四电极52之间的沟道方向总体上沿着平行于衬底1的方向延伸，比如一种实施方式为，第三电极51和第四电极52在平行于第一方向的正投影存在交叠。该存储器的结构设计为一种新型结构，使得第一晶体管和第二晶体管之间结构更加紧凑，另外，在制作3D叠层存储单元时，可以将每个叠层的第二晶体管的栅极连接作为字线，垂直方向延伸的字线使得2T0C的结构工艺简单且节约空间。
本申请实施例所述的水平沟道可以理解为非垂直沟道的一种，所述水平沟道可以是沟道的长度方向或载流子的传输方向在与衬底平行的平面内的实施例。
在一些实施方式中，该水平沟道可以为平面型(panlar channel)沟道，而非垂直沟道，平面型沟道是指沟道的载流子的延伸方向大体上在平行于衬 底的方向而非垂直衬底的方向。
在平面内延伸的沟道，可以是直线型沟道也可以为环形或弧形沟道。具体根据源电极和漏电极之间的半导体层的形状决定。
在一些实施方式中，第二晶体管的和第一晶体管的沟道可以为上述的水平沟道。
本申请第二晶体管为栅极沿垂直方向延伸且沟道为水平沟道，可以方便在垂直方向制作堆叠的3D结构时，一次性形成沿垂直方向延伸的通孔，在所述通孔的侧壁依次一次性形成各层存储单元的沟道膜层和一次性形成各层存储单元的栅极绝缘层，然后在通孔内填充栅极或字线，该字线的不同区域用作不同层晶体管的栅极。
第一晶体管为第一栅极11沿水平方向延伸且沟道沿水平方向，便于在垂直方向将堆叠的多个晶体管相邻的第一晶体管之间隔开，实现结构紧凑的第一晶体管和第二晶体管构成的存储单元，以有效实现器件的微缩。
所述沟道与衬底1平行可以是大约平行，在实际应用中视有效源电极和漏电极之间的相对位置而定，比如，源电极和漏电极的纵截面图中电极的上表面、下表面至少之一的外轮廓在一个平面上，且该平面大约与衬底主表面平行。
在一示例性实施例中，所述第二半导体层9在所述第二栅极12的侧壁上延伸形成沿着垂直所述衬底1方向延伸的环形的半导体层。在一示例性实施例中，针对一个晶体管，所述第二半导体层9环绕栅极的侧壁的各区域。示例性的，所述第二半导体层9为环形，在第二栅极12的每个位置的横截面，第二半导体层9为环形，且环形大小与第二栅极12横截面外轮廓形状相适应。或者，所述第二半导体层9可以为部分环绕型。比如，在垂直于所述衬底1的方向，所述半导体层9可能有间隙。在一示例性实施例中，所述第一方向Z可以与所述衬底1交叉。本文中，与衬底1交叉是指与衬底1的上表面(即设置有第一晶体管和第二晶体管的表面)交叉，与衬底1平行是指与衬底1的上表面平行，与衬底1垂直是指与衬底1的上表面垂直。此时，可以垂直堆叠形成多个存储单元。但本公开实施例不限于此，第一方向Z可以与所述 衬底1平行。后续实施例中以第一方向Z与衬底1交叉为例进行说明，但下述说明可以应用到第一方向Z与衬底1平行的方案中，将垂直于衬底1替换为平行于第一方向Z，平行于衬底1替换为垂直于第一方向Z即可。
在一示例性实施例中，所述第二晶体管还可以包括设置在所述第二栅极12和第二半导体层9之间且环绕所述第二栅极12侧壁的第二栅绝缘层10，所述第二半导体层9通过所述第二栅绝缘层10与所述第二栅极12隔离。所述第三电极51和所述第四电极52通过所述第二栅绝缘层10与所述第二栅极12绝缘。
在一示例性实施例中，在垂直于所述衬底1的平面上，所述第一栅极11的正投影可以与所述第三电极51的正投影存在交叠。
在一示例性实施例中，在垂直于所述衬底1的平面上，所述第一栅极11的正投影与所述第三电极51的正投影可以存在交叠，所述第三电极51的正投影与所述第四电极52的正投影可以存在交叠，所述第一晶体管的第一栅极11连接所述第二晶体管的第三电极51。。
在一示例性实施例中，所述第一栅极11与所述第三电极51可以为一体结构，即第一栅极11和第三电极51使用相同材料通过同一制备工艺同时形成。但本公开实施例不限于此，第一栅极11和第三电极51可以非一体结构，第一栅极11和第三电极51可以为独立的电极。
示例性的，第一栅极11和第三电极51为一个沿着同一方向延伸的一个相同的电极，该电极作为第一栅极11和第三电极51。比如，第一栅极11在平行衬底1的方向延伸且端部延伸到第二半导体层的源接触区域，与所述源接触区域连接。
在一示例性实施例中，在垂直于所述衬底1的平面上，所述第一电极33的正投影与所述第一栅极11的正投影可以存在交叠。
在一示例性实施例中，所述第二半导体层9的第二漏接触区域92与所述第二半导体层9的第二源接触区域91位于所述第二半导体层9的侧壁相向且间隔设置。
在一示例性实施例中，所述第一晶体管还可以包括环绕所述第一栅极11 的第一栅绝缘层7，环绕所述第一栅绝缘层7的第一半导体层6。所述第一电极33连接所述第一半导体层6。所述第一半导体层6形成容纳腔，所述第一栅极11设置在所述容纳腔内，所述第一栅绝缘层7隔离所述第一半导体层6和所述第一栅极11。
所述第一半导体层6形成容纳腔可以是仅具有一个开口的腔，或者，可以是具有两个开口的腔体，该腔体的横截面为环形。
在一示例性实施例中，所述第二电极34环绕且连接所述第一半导体层6，在垂直于所述衬底1的平面上，所述第二电极34的截面具有环形的开口，且所述第一半导体层6位于所述第二电极34的开口内。
在一示例性实施例中，所述第一电极33可以设置在所述第二电极34远离所述第二栅极12一侧；以及，可以设置在所述第一栅极11远离所述第二栅极12一侧。
在一示例性实施例中，所述第一半导体层6可以包括侧壁和两个端部，所述第一半导体层6包括第一源接触区域61和第一漏接触区域62，所述第一源接触区域61位于所述第一半导体层6的侧壁且环绕所述第一半导体层6，所述第一漏接触区域62位于所述第一半导体层6的侧壁且环绕所述第一半导体层6，或者位于所述两个端部中远离所述第二栅极12的端部。
在一示例性实施例中，在垂直于所述衬底1的截面上，所述第一电极33、所述第二电极34、所述第三电极51可以位于所述第二栅极12的第一侧，所述第四电极52可以位于所述第二栅极12的第二侧，且所述第一侧和所述第二侧为相对的两侧。
在一示例性实施例中，所述第一电极33可以沿第三方向Y延伸。
在一示例性实施例中，所述第二电极34沿第三方向Y的长度可以小于所述第一电极33沿第三方向Y的长度。本实施提供的方案，在形成存储单元阵列时，可以使得不同存储单元的第二电极34之间断开。但本公开实施例不限于此，所述第二电极34沿第三方向Y的长度可以等于或大于所述第一电极33沿第三方向Y的长度。
在一示例性实施例中，所述第二电极34可以沿第一方向Z延伸。
在一示例性实施例中，在垂直于衬底1的平面上，所述第一电极33的正投影与所述第一栅极11的正投影可以存在交叠。
在一示例性实施中，在平行于所述衬底1的平面上，所述第一电极33的正投影和所述第二电极34的正投影可以无交叠，所述第三电极51的正投影、所述第四电极52的正投影可以无交叠。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述第三电极51靠近所述衬底1一侧的表面与所述衬底1的第一距离，和所述第四电极52靠近所述衬底1一侧的表面与所述衬底1的第二距离可以相同。但本公开实施例不限于此，第一距离和第二距离可以不同。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述第三电极51的第一厚度，和所述第四电极52的第二厚度可以相同。但本公开实施例不限于此，第一厚度和第二厚度可以不同。
在一示例性实施例中，所述第三电极51靠近所述衬底1一侧的表面与所述衬底1的距离可以等于所述第四电极52靠近所述衬底1一侧的表面与所述衬底1的距离，所述第三电极51远离所述衬底1一侧的表面与所述衬底1的距离可以等于所述第四电极52远离所述衬底1一侧的表面与所述衬底1的距离。
在一示例性实施例中，所述第三电极51和所述第四电极52的膜层可以为同一导电膜层的不同区域，且间隔设置，所述同一导电膜层与所述衬底1大约平行。
在一示例性实施例中，在平行于所述衬底1的平面上，所述第二栅极12的正投影可以位于所述第三电极51的正投影外，所述第二栅极12的正投影可以位于所述第四电极52的正投影外。
在一示例性实施例中，所述第一方向Z可以垂直于所述衬底1。
在一示例性实施例中，如图1B所示，在垂直于所述衬底1的截面上，所述第三电极51位于所述第二栅极12的第一侧，所述第四电极52位于所述第二栅极12的第二侧，且所述第一侧和所述第二侧为相对的两侧。但本公开实施例不限于此，第三电极51和第四电极52可以是其他位置。
在一示例性实施例中，所述第三电极51可以沿第二方向X延伸，所述第四电极52可以沿第三方向Y延伸，所述第二方向X可以平行于所述衬底1，所述第三方向Y可以平行于所述衬底1，且所述第二方向X和所述第三方向Y可以交叉。但本公开实施例不限于此，第三电极51和第四电极52可以是其他形状。
在一示例性实施例中，所述第二方向X和所述第三方向Y可以垂直，但本公开实施例不限于此，第二方向X和第三方向Y之间可以是其他角度。
在一示例性实施例中，在垂直于所述衬底1的方向，所述第一电极33的截面可以是方形，本公开实施例不限于此，所述第一电极33的截面可以是其他形状，比如，圆形、六边形等等。
在一示例性实施例中，在垂直于所述衬底1的方向，所述第三电极51和第四电极52的截面可以是方形，本公开实施例不限于此，所述第三电极51和第四电极52的截面可以是其他形状，比如，圆形、六边形等等。
在一示例性实施例中，所述第三电极51和第四电极52可以连接在与图1A所示的位置不同的其他位置，比如，第三电极51连接在第二半导体层9构成的环形柱体的第一侧，第四电极52连接在第二半导体层9构成的环形柱体的第二侧，且第一侧和第二侧相邻，等等。
在一示例性实施例中，所述第三电极51和所述第四电极52可以通过一次制备工艺同时形成，但本公开实施例不限于此，可以通过不同工艺分别制备。
在一示例性实施例中，所述第一电极33靠近所述衬底1一侧的表面与所述衬底1的距离可以小于所述第三电极51靠近所述衬底1一侧的表面与所述衬底1的距离，所述第一电极33远离所述衬底1一侧的表面与所述衬底1的距离可以大于所述第三电极51远离所述衬底1一侧的表面与所述衬底1的距离。沿垂直于衬底1的方向，所述第一电极33的厚度可以大于所述第三电极51的厚度。
在一示例性实施例中，所述第二电极34远离所述衬底1一侧的表面与所述衬底1的距离可以和所述第二栅极12远离所述衬底1一侧的表面与所述衬 底1的距离一致。
图1B中，所述第一半导体层6和所述第二半导体层9可以物理连接或不连接。在图1B中，所述第一半导体层6的端部与所述第二半导体层9的侧壁接触。但是在一些实施例需要隔开时，第一半导体层6的端部与所述第二半导体层9的侧壁不接触，在制作膜层时可以通过二者之间的绝缘层隔离。
2T0C结构，第一晶体管为读晶体管，第二晶体管为写晶体管，一般地，读晶体管开启，写晶体管需要关闭，此时，第一半导体层6的端部与所述第二半导体层9的侧壁接触对第一晶体管的工作不产生较大影响。
在一些实施例中，为了避免第一半导体层6的端部与所述第二半导体层9的侧壁接触带来的其他效果，则可以将二者在空间结构上隔离。
图1A中，沿垂直于所述衬底1的方向，所述第二半导体层9的长度可以等于所述第二栅极12的长度。但本公开实施例不限于此，在一示例性实施例中，沿垂直于所述衬底1的方向，所述第二半导体层9的长度可以小于等于所述第二栅极12的长度，小于等于所述第二栅绝缘层10的长度，且，所述第二半导体层9的长度大于等于所述第三电极51的长度，以及，所述第二半导体层9的长度大于等于所述第四电极52的长度。本实施例提供的方案，可以缩短沟道长度，减少漏电。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述第二半导体层9的长度可以等于所述第二栅绝缘层10的长度，所述第二栅绝缘层10的长度可以等于所述第二栅极12的长度。
在一示例性实施例中，沿垂直于所述衬底1的方向，所述第二栅绝缘层10的长度可以小于所述第二栅极12的长度，以及，可以大于等于所述第二半导体层9的长度。
在一示例性实施例中，所述第一半导体层6和第二半导体层9可以为金属氧化物半导体层，或为含硅的半导体层。。
在一示例性实施例中，所述金属氧化物半导体层中的金属可以包括但不限于：铟、锡、锌、铝、镓中的至少之一。
在一示例性实施例中，所述金属氧化物半导体层可以包括但不限于：氧 化铟、氧化锡、铟锌类氧化物、锡锌类氧化物、铝锌类氧化物、铟镓类氧化物、铟镓锌类氧化物、铟铝锌类氧化物、铟锡锌类氧化物、锡镓锌类氧化物、铝镓锌类氧化物、锡铝锌类氧化物中的至少一种。
如图1B所示，本实施例提供的方案，第三电极51和第四电极52之间的沟道的尺寸可以通过在垂直于所述衬底1的平面上，所述第三电极51的正投影与所述第四电极52的正投影之间的交叠长度进行控制。图1B中，所述第三电极51的正投影与所述第四电极52的正投影之间的交叠长度为d，可以通过控制第三电极51和第四电极52沿垂直于衬底1方向的厚度来控制沟道尺寸，相比源极环绕栅极，漏极环绕栅极的晶体管，通过改变栅极所在的通孔的尺寸(需更改掩膜版)或者增大源极和漏极之间的距离来控制沟道尺寸(会导致晶体管体积增大)，本实施例可以更为方便的控制沟道的尺寸，工艺改动小，且对晶体管的尺寸影响较小。
如图1A和图1B所示，本公开实施例提供一种存储单元，包括：设置在衬底上的读晶体管和写晶体管，其中：
读晶体管可以是第一晶体管，所述读晶体管包含第一栅极11、第一半导体层6、第一源电极(可以是第二电极34)、第一漏电极(可以是第一电极33)；所述第一半导体层6环绕所述第一栅极11；
写晶体管可以是第二晶体管，所述写晶体管包含第二栅极12、第二半导体层9、第二源电极(可以是第三电极51)、第二漏电极(可以是第四电极52)；所述第二半导体层9环绕所述第二栅极12；所述写晶体管的第二源电极连接所述读晶体管的第一栅极11；
所述写晶体管的第二半导体层9的沟道为水平沟道。
在一示例性实施例中，所述第二栅极12沿着垂直衬底1的方向延伸且具有侧壁，所述第二半导体层9环绕所述侧壁，所述第二半导体层9包括第二源接触区域91；
所述第一栅极11沿着平行于所述衬底1的方向延伸且具有侧壁和两个端部，所述第一半导体层6至少环绕所述侧壁，所述两个端部的其中一个端部延伸到所述第二半导体层9的第二源接触区域91与所述第二半导体层9接触。
在一示例性实施例中，所述第二半导体层9的侧壁还包括第二漏接触区域92；所述第二源接触区域91和所述第二漏接触区域92位于所述第二半导体层9的侧壁的不同区域，且所述第二源接触区域91和第二漏接触区域92在垂直衬底1的平面内的正投影具有重叠区域，使得所述第二源接触区域91和所述第二漏接触区域92之间的沟道平行于所述衬底1；
所述第一半导体层6的侧壁可以具有第一源接触区域61和第一漏接触区域62，所述第一源接触区域61和第一漏接触区域62之间的沟道平行于所述衬底。
图2为本公开实施例存储单元等效电路示意图。如图2所示，在一示例性实施例中，第一晶体管可以作为读取管，第二晶体管可以作为写入管，第一电极33可以连接读取位线，第二电极34可以连接读取字线，第二栅极12可以连接写入字线，第四电极52可以连接写入位线。
给写入字线(即第二栅极12)施加电压，沟道导通，第三电极51和第四电极52之间联通。读写过程如下：1)写入“1”时，写入位线(即第四电极52)施加读取电压，向存储节点(第一栅极11和第三电极51之间为存储节点，如附图2中箭头所指的位置)注入电荷，第一晶体管导通；读取“1”时，在读取管中读取字线(即第二电极34)施加读取电压，由于存储节点中存有一定电荷，在读取位线与读取字线之间有电流通过，或者，可以理解为附图中的第一电极33与第二电极34之间有电流通过，再由外围电路放大识别后，完成读取“1”过程。(2)写入“0”时，写入位线(即第四电极52)给低于阈值电压的电压抽取电荷，第一晶体管不导通；读取“0”时，在读取管中读取字线(即第二电极34)施加读取电压，由于存储节点中无电荷，读取位线(即第一电极33)与读取字线(即第二电极34)之间，没有或者较小电流通过，再由外围电路放大识别后完成读取“0”过程。
下面通过本实施例显示基板的制备过程说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工 艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
在一示例性实施例中，存储单元的制备过程可以包括：
1)在衬底1上依次沉积第一绝缘薄膜、第一金属薄膜、第二绝缘薄膜，形成第一绝缘层2、第一金属层3和第二绝缘层4，如图3所示。
在一示例性实施例中，所述衬底1可以使用玻璃、硅、柔性材料等制备。所述柔性材料可以采用聚酰亚胺(PI)，聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。在示例性实施例中，衬底1可以是单层结构，或者是多层的叠层结构，叠层结构的衬底可以包括：柔性材料/无机材料/柔性材料，所述无机材料比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)中的任意一种或多种。所述衬底1可以为半导体衬底；比如可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。
在一示例性实施例中，所述第一绝缘薄膜和第二绝缘薄膜可以是low-K介质层，即介电常数K<3.9的介质层。比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。所述第一绝缘薄膜和第二绝缘薄膜可以是相同的材料或者不同的材料。
在一示例性实施例中，所述第一金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。
2)对所述第一绝缘层2、第一金属层3、第二绝缘层4通过构图工艺进行构图，形成第一开槽P1和第二开槽P2，如图4所示。所述第一开槽P1贯通所述第一绝缘层2、第一金属层3和第二绝缘层4，所述第二开槽P2贯 通所述第一绝缘层2、第一金属层3和第二绝缘层4。所述第一金属层3可以包括沿第二方向X延伸的第一子部31和沿第三方向Y延伸的第二子部32、沿第三方向Y延伸的第一电极33，所述第一子部31连接所述第二子部32和第一电极33。
在一示例性实施例中，在平行于所述衬底1的平面上，所述第一绝缘层2、所述第一金属层3和所述第二绝缘层4的截面可以为H形。
在一示例性实施例中，所述第一开槽P1和第二开槽P2的大小和形状可以相同，但本公开实施例不限于此，第一开槽P1和所述第二开槽P2的大小和形状可以不同。
本实施例中，第一金属层3的图案仅为示例，可以是其他形状的图案，比如，沿第一子部31的延伸方向将当前第二子部32进行分割为两个部分，可以只保留其中一个部分作为第二子部32。
3)在形成有前述图案的衬底1上，沉积第三绝缘薄膜，形成第三绝缘层5，所述第三绝缘层5填充所述第一开槽P1和第二开槽P2，如图5所示。
在一示例性实施例中，所述第三绝缘薄膜可以是low-K介质层，即介电常数K<3.9的介质层，比如可以是硅氮化物(SiNx)、硅氧化物(SiOx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。所述第三绝缘薄膜和第一绝缘薄膜、第二绝缘薄膜可以是相同的材料或者不同的材料。后续第四绝缘薄膜类似，不再赘述。
4)在形成有前述图案的衬底1上，形成贯穿所述第一绝缘层2、第一金属层3和第二绝缘层4的通孔41，在平行于所述衬底1的平面上，所述通孔41的正投影可以与所述第一子部31的正投影存在交叠，所述通孔41的正投影可以与所述第二子部32的正投影存在交叠，如图6所示。图6所示的通孔41在平行于所述衬底1的平面上的截面为四边形，但本公开实施例不限于此，通孔41在平行于所述衬底1的平面上的截面可以是其他形状，比如圆形、五边形、六边形等等。
5)选择性刻蚀掉第一金属层3中的第一子部31、第二子部32，以及，第一电极33与第一子部31的连接处，此时，第一金属层3只剩下第一电极 33，且第一电极33设置有朝向第一子部31(第一子部31已被刻蚀掉)的第三开槽P3，如图7A和图7B所示，，此时形成了由被选择性刻蚀掉的第一子部31所在的区域形成的第一通道42、第二子部32所在的区域形成的第二通道43和所述通孔41，所述第一通道42与所述通孔41贯通，所述第二通道43与所述通孔41贯通。
6)在步骤5形成的通道(即通孔41、第一通道42和第二通道43)的侧壁，依次沉积第一半导体薄膜和第一栅极氧化物薄膜形成第一半导体层6和第一栅绝缘层7，如图8A、8B和8C所示，其中，图8C为图8B沿BB方向的截面图，且仅示出了第一半导体层6和第一栅绝缘层7。此时第一半导体层6和第一栅绝缘层7作为所述通道的通道壁，所述第一半导体层6环绕所述第一栅绝缘层7。
在一示例性实施例中，所述第一栅极氧化物薄膜可以为High-K介质材料。High-K介质材料可以包括但不限于以下至少之一：氧化硅，氧化铝，氧化铪。
在一示例性实施例中，所述第一半导体薄膜作为沟道层，可以是含有硅的膜层，或金属氧化物半导体，其中，所述金属氧化物半导体包括但不限于以下至少之一材料形成：IGZO、氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)。使用IGZO作为半导体层时，具备低漏电，刷新时间短的优势。后续第二半导体薄膜类似，不再赘述。
在一示例性实施例中，可以通过原子层沉积(Atomic Layer Deposition，ALD)方法沉积所述第一半导体薄膜和所述第一栅极氧化物薄膜。
6)在所述通道(即通孔41、第一通道42和第二通道43)内沉积第二金属薄膜，形成第二金属层8，所述第二金属层8完全填充所述通道，如图9A、图9B和图9C所示。图9C为图9B沿BB方向的截面图，且仅示出了第一半导体层6、第一栅绝缘层7和第二金属层8。此时，第一栅绝缘层7环绕所述第二金属层8。
在一示例性实施例中，所述第二金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。 所述第二金属薄膜可以和所述第一金属薄膜相同或不同。
7)选择性地光刻和刻蚀所述通孔41中的第二金属层8和第一栅绝缘层7，保留通道中其他位置的第二金属层8(与衬底1平行的第一通道42和第二通道43中的第二金属层8)和第一栅绝缘层7，如图10A、图10B和图10C所示，图10C为图10B沿BB方向的截面图，且仅示出了第一半导体层6、第一栅绝缘层7和第二金属层8。位于第一通道42的第二金属层8作为第二晶体管的第三电极51，位于第二通道43的第二金属层8作为第二晶体管的第四电极52，且第三电极51和第四电极52彼此断开。
8)在上述刻蚀所得的通孔41的侧壁依次沉积第二半导体薄膜、第二栅极氧化物薄膜和第三金属薄膜，分别形成第二半导体层9、第二栅绝缘层10和第二栅极12，且所述第二栅绝缘层10环绕所述第二栅极12，所述第二半导体层9环绕所述第二栅绝缘层10，所述第二栅极12完全填充所述第二栅绝缘层10环绕的区域。如图11A、图11B和图11C所示，图11C为图11B沿BB方向的截面图，且仅示出了第一半导体层6、第一栅绝缘层7、第二半导体层9、第二栅绝缘层10、第二金属层8(第三电极51、第四电极52)、第二栅极12。
在一示例性实施例中，所述第二栅极氧化物薄膜可以为High-K介质材料。High-K介质材料可以包括但不限于以下至少之一：氧化硅，氧化铝，氧化铪。所述第二栅极氧化物薄膜和所述第一栅极氧化物薄膜的材料可以相同或不同。
在一示例性实施例中，所述第二半导体薄膜可以和所述第一半导体薄膜使用相同的材料。
在一示例性实施例中，所述第三金属薄膜可以包括但不限于以下至少之一：钨(W)、铝(Al)、钼(Mo)、钌(Ru)、氮化钛(TiN)和钽(Ta)。所述第三金属薄膜可以和所述第一金属薄膜、第二金属薄膜相同或不同。后续第四金属薄膜类似，不再赘述。
9)在形成有前述图案的衬底1上，刻蚀如图12所示的插槽结构44，但不刻蚀第一半导体层6及第一半导体层6所包含的部分。所述插槽结构44 贯穿所述衬底1上的每个膜层，在垂直于所述衬底1的平面上，所述插槽结构44的正投影位于所述第一电极33的正投影外，以及，位于所述通孔41的正投影外，以及，位于所述第四电极52的正投影外。
10)在所述插槽结构44内沉积第四金属薄膜，形成填充所述插槽结构44的第四金属层34’，如图13A和图13B所示。
11)在形成上述图案的衬底1上，形成贯穿所述第四金属层34’的第四开槽P4和第五开槽P5，以及，第二电极34，如图14A所示，类似第一开槽P1和第二开槽P2，第四开槽P4和第五开槽P5分别位于第四金属层34’的两侧，第二电极34沿第三方向Y的长度小于第一电极33沿第三方向Y的长度，第二电极34环绕第一半导体层6，如图14B所示。图14C为图14B沿BB方向的截面图，可以看到，第一晶体管和第二晶体管的主体结构基本制备完毕。
12)在形成上述图案的衬底1上，沉积第四绝缘薄膜，形成第四绝缘层55，所述第四绝缘层55填充所述第四开槽P4和第五开槽P5，如图15所示。
采用上述制备过程制备的存储单元中，第二通道43中，可以存在环绕第四电极52的第一栅绝缘层7和环绕第一栅绝缘层7的第一半导体层6。但本公开实施例不限于此，第二通道43中，可以不存在环绕第四电极52的第一栅绝缘层7和环绕第一栅绝缘层7的第一半导体层6(除与通孔41相交的区域外)，即可以去除第二通道43中的第一栅绝缘层7和第一半导体层6。为工艺方便，可以保留第二通道43中的第一栅绝缘层7和第一半导体层6。
在一示例性实施例中，仅制备一个存储单元时，可以省略上述步骤11)和步骤12)。
上述制备过程仅为示例，本公开实施例不限于此，可以通过其他方式进行制备。比如，可以在沉积第一金属薄膜后，通过构图工艺进行构图，形成H形的第一金属层3。后续再沉积第二绝缘薄膜形成第二绝缘层4，无需开槽形成第一开槽P1和第二开槽P2以及无需沉积第三绝缘薄膜。
图16为另一示例性实施例提供的存储单元的截面示意图。如图16所示，本实施例中，所述存储单元包括第一晶体管和第二晶体管。所述第一晶体管 可以包括第一电极33、第二电极34和第一栅极11，以及，环绕所述第一栅极11的第一栅绝缘层7，环绕所述第一栅绝缘层7的第一半导体层6；所述第二晶体管可以包括第三电极51、第四电极54和第二栅极12，以及，沿第一方向Z延伸的第二半导体层9，隔离所述第二半导体层9和第二栅极12的第二栅绝缘层10，在垂直于所述衬底1的方向上，所述第四电极52的厚度可以大于所述第三电极51的厚度。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的存储单元。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
图17A为本公开实施例提供的一种3D存储器的平面示意图，图17B为本公开实施例提供的一种3D存储器的截面示意图。如图17A和17B所示，本实施例提供一种3D存储器，可以包括多层沿垂直于衬底1的方向堆叠的存储单元，其中，
每层所述存储单元可以包括：读晶体管和写晶体管；读晶体管可以是第一晶体管，写晶体管可以是第二晶体管；
所述读晶体管包含第一栅极11、第一半导体层6，第一源电极(可以是第二电极34)和第一漏电极(可以是第一电极33)，所述第一栅极11可以沿平行于所述衬底1的方向延伸；所述写晶体管包含第二栅极12、第二半导体层9，第二源电极(可以是第三电极51)和第二漏电极(可以是第四电极52)，所述第二栅极12可以沿垂直于所述衬底1的方向延伸；
所述写晶体管的第二源电极与所述读晶体管的第一栅极11相连；所述第一半导体层6环绕所述第一栅极11，所述第二半导体层9环绕所述第二栅极12；所述写晶体管的第二半导体层9的沟道为水平沟道。
本实施例提供的3D存储器，写晶体管的第二半导体层环绕所述第二栅极，第二半导体层上的源接触区域漏接触区域的设置使得源极和漏极之间的沟道方向总体上沿着平行于衬底的方向延伸，第二晶体管与第一晶体管不堆叠，第一晶体管和第二晶体管之间结构更加紧凑，可以减小垂直衬底方向存 储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺，降低成本。
在一示例性实施例中，同层的所述读晶体管和写晶体管在所述衬底1上沿着平行于所述衬底1的方向间隔分布。
在一示例性实施例中，所述读晶体管的第一栅极11与所述写晶体管的第二源电极可以为一体结构，但不限于此，可以为两个独立的电极。
在一示例性实施例中，所述第一栅极11可以沿着平行于所述衬底1的第二方向延伸；
所述第一半导体层6可以包括第一源接触区域61和第一漏接触区域62，所述第二半导体层9可以包括第二源接触区域91和第二漏接触区域92；
每层所述存储单元还可以包括：沿着平行于所述衬底1的第三方向延伸的第一位线330，和第二位线520，所述第三方向与所述第二方向交叉；所述第一位线330与所述第一半导体层6的第一漏接触区域62连接，所述第二位线520与所述第二半导体层9的第二漏接触区域92连接；
每层所述存储单元还可以包括：分别沿着垂直于所述衬底1的方向延伸的第一字线340和第二字线120；
所述第一字线340分别与不同层的所述存储单元的第一半导体层6的第一源接触区域61连接，所述第二字线120分别与不同层的所述存储单元的第二栅极12连接。不同层的所述存储单元的第二栅极12可以是所述第二字线120的一部分。
本实施例提供的方案，可以每个叠层的写晶体管的第二栅极连接作为字线，垂直方向延伸的字线使得2T0C的结构工艺简单且节约空间。
在一示例性实施例中，所述第一字线340环绕不同层的所述存储单元的每个第一半导体层6的侧壁且与每个第一半导体层6的侧壁的第一源接触区域61连接。
在一示例性实施例中，所述第一栅极11可以具有侧壁、第一端部和第二端部，所述第一端部与所述第二半导体层9的第二源接触区域91连接，所述第一位线330与所述第二端部连接。
在一示例性实施例中，不同层的写晶体管的所述第二半导体层9可以为一体结构。
在一示例性实施例中，不同层的写晶体管可以共用一个沿着垂直于衬底1方向延伸的环状的第二半导体层9。
在一示例性实施例中，所述写晶体管还可以包括环绕所述第二栅极12的第二栅绝缘层10，所述第二半导体9环绕所述第二栅绝缘层10。
在一示例性实施例中，不同层的写晶体管可以共用一个沿着垂直于衬底1方向延伸的环状的第二栅绝缘层10。
在一示例性实施例中，不同层的所述第一栅极11在衬底1上的投影可以位于相同区域，不同层的所述第一源电极在衬底1上的投影可以位于相同区域、不同层的所述第一漏电极在衬底1上的投影可以位于相同区域，不同层的所述第二栅极12在衬底1上的投影可以位于相同区域，不同层的所述第二源电极在衬底1上的投影可以位于相同区域、不同层的所述第二漏电极在衬底1上的投影可以位于相同区域。
上述3D存储器中读晶体管和写晶体管的结构可参考前述多个实施例中的第一晶体管和第二晶体的结构，此处不再赘述。
如图18所示，本公开实施例提供一种3D存储器的制备方法，所述3D存储器包括多层沿垂直于衬底的方向堆叠的存储单元、第一字线和第二字线，每层所述存储单元包括：读晶体管和写晶体管，所述读晶体管包含第一栅极、第一半导体层，第一源电极和第一漏电极；所述写晶体管包含第二栅极、第二半导体层，第二源电极和第二漏电极，所述制备方法可以包括：
步骤1801，提供衬底，在所述衬底上依次交替沉积绝缘薄膜和金属薄膜，进行构图形成包括交替设置的绝缘层和金属层的堆叠结构，所述金属层包括相连的第一子部和第二子部，以及，所述读晶体管的第一漏电极；
步骤1802，刻蚀所述堆叠结构以形成贯穿所述堆叠结构的通孔，刻蚀所述第一子部形成第一通道，刻蚀所述第二子部形成第二通道，所述第一通道、所述第二通道与所述通孔贯通；
步骤1803，在所述第一通道、第二通道和所述通孔构成的通道的侧壁依 次沉积半导体薄膜、栅绝缘薄膜和完全填充所述通道的金属薄膜，刻蚀所述通孔内的所述栅绝缘薄膜和金属薄膜以形成位于所述第一通道的第一半导体层、第二源电极、第一栅极和位于所述第二通道的第二漏电极；
步骤1804，在所述通孔的侧壁沉积半导体薄膜以形成所述写晶体管的第二半导体层，所述第二半导体层包括间隔设置的第二源接触区域和第二漏接触区域，所述第二源电极与所述第二源接触区域接触，所述第二漏电极与所述第二漏接触区域接触；所述第二源接触区域和所述第二漏接触区域之间的沟道为水平沟道；
步骤1805，在所述通孔内沉积金属薄膜完全填充所述通孔以形成所述第二字线，不同层的所述写晶体管的第二栅极为所述第二字线的一部分；
步骤1806，构图形成沿着垂直于所述衬底的方向延伸的所述第一字线，不同层的所述读晶体管的第一源电极为所述第一字线的一部分。
本公开实施例提供的3D存储器的制备方法制备的3D存储器，第二晶体管的栅极为垂直结构且沟道为水平沟道与第一晶体管不堆叠，可以减小垂直衬底方向存储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺，降低成本。且本实施例提供的3D存储器，可以通过调节源极或漏极的厚度改变沟道尺寸，工艺简便，对晶体管的尺寸影响小。本公开实施例的制备方法利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (29)

  1. 一种存储单元，包括：设置在衬底上的第一晶体管和第二晶体管，其中：
    所述第一晶体管包括设置在所述衬底上的第一栅极、第一电极、第二电极、第一半导体层，所述第一栅极沿平行于所述衬底的方向延伸；
    所述第二晶体管包括设置在所述衬底上的第三电极、第四电极、沿垂直于衬底的方向延伸的第二栅极，以及，环绕所述第二栅极侧壁的第二半导体层，所述第一栅极与所述第二半导体层连接；所述第二半导体层包括间隔设置的第二源接触区域和第二漏接触区域，所述第三电极与所述第二半导体层的所述第二源接触区域接触，所述第四电极与所述第二半导体层的所述第二漏接触区域接触，所述第二源接触区域和第二漏接触区域之间的沟道为水平沟道。
  2. 根据权利要求1所述的存储单元，其中，所述第一晶体管和第二晶体管在所述衬底上沿着平行于所述衬底的方向间隔分布。
  3. 根据权利要求1所述的存储单元，其中，在垂直于所述衬底的平面上，所述第一栅极的正投影与所述第三电极的正投影存在交叠，所述第三电极的正投影与所述第四电极的正投影存在交叠，所述第一晶体管的第一栅极和所述第二晶体管的第三电极为一体结构。
  4. 根据权利要求1所述的存储单元，其中，所述第一栅极与所述第二半导体层的第二源接触区域连接。
  5. 根据权利要求1所述的存储单元，其中，在垂直于所述衬底的平面上，所述第一电极的正投影与所述第一栅极的正投影存在交叠。
  6. 根据权利要求4所述的存储单元，其中，所述第二半导体层的第二漏接触区域与所述第二半导体层的第二源接触区域位于所述第二半导体层的侧壁相向且间隔设置。
  7. 根据权利要求6所述的存储单元，其中，所述第二电极环绕且连接所述第一半导体层，在垂直于所述衬底的平面上，所述第二电极的截面具有环形的开口，且所述第一半导体层位于所述第二电极的开口内。
  8. 根据权利要求7所述的存储单元，其中，所述第一电极设置在所述第二电极远离所述第二栅极一侧。
  9. 根据权利要求7所述的存储单元，其中，所述第一半导体层包括侧壁和两个端部，所述第一半导体层包括第一源接触区域和第一漏接触区域，所述第一源接触区域位于所述第一半导体层的侧壁且环绕所述第一半导体层，所述第一漏接触区域位于所述第一半导体层的侧壁且环绕所述第一半导体层，或者位于所述两个端部中远离所述第二栅极的端部。
  10. 根据权利要求5所述的存储单元，其中，所述第一电极沿第三方向延伸，所述第一栅极沿第二方向延伸，所述第三电极沿第二方向延伸，所述第四电极沿第三方向延伸，所述第二方向和所述第三方向交叉且平行于所述衬底。
  11. 根据权利要求7所述的存储单元，其中，在平行于所述衬底的平面上，所述第一电极的正投影和所述第二电极的正投影无交叠；所述第三电极的正投影和所述第四电极的正投影无交叠。
  12. 根据权利要求7所述的存储单元，其中，在垂直于所述衬底的截面上，所述第一电极、所述第二电极、所述第三电极位于所述第二栅极的第一侧，所述第四电极位于所述第二栅极的第二侧，且所述第一侧和所述第二侧为相对的两侧。
  13. 根据权利要求5至12任一所述的存储单元，其中，所述第一电极靠近所述衬底一侧的表面与所述衬底的距离小于所述第三电极靠近所述衬底一侧的表面与所述衬底的距离，所述第一电极远离所述衬底一侧的表面与所述衬底的距离大于所述第三电极远离所述衬底一侧的表面与所述衬底的距离。
  14. 根据权利要求2至12任一所述的存储单元，其中，所述第三电极和所述第四电极的膜层为同一导电膜层的不同区域，且间隔设置，所述同一导电膜层与所述衬底大约平行。
  15. 根据权利要求2至12任一所述的存储单元，其中，所述第二晶体管还包括：设置在所述第二栅极和所述第二半导体层之间环绕所述第二栅极侧壁的第二栅绝缘层，沿垂直于所述衬底的方向，所述第二半导体层的长度小 于等于所述第二栅绝缘层的长度，且，大于等于所述第三电极的长度，且，大于等于所述第四电极的长度。
  16. 根据权利要求6、7、8、11或12所述的存储单元，其中，所述第一半导体层和第二半导体层的材料包括金属氧化物半导体材料。
  17. 根据权利要求16所述的存储单元，其中，所述金属氧化物半导体材料中的金属包括：铟、锡、锌、铝、镓中的至少之一。
  18. 一种存储单元，包括：设置在衬底上的读晶体管和写晶体管，
    所述读晶体管包含第一栅极、第一半导体层、第一源电极、第一漏电极；所述第一半导体层环绕所述第一栅极；所述第一栅极沿平行于所述衬底的方向延伸；
    所述写晶体管包含第二栅极、第二半导体层、第二源电极、第二漏电极；所述第二半导体层环绕所述第二栅极；所述第二栅极沿垂直于所述衬底的方向延伸，所述写晶体管的第二源电极连接所述读晶体管的第一栅极；
    所述写晶体管的第二半导体层的沟道为水平沟道。
  19. 根据权利要求18所述的存储单元，其特征在于，所述读晶体管和写晶体管在所述衬底上沿着平行于所述衬底的方向间隔分布。
  20. 根据权利要求18所述的存储单元，其中，
    所述第二栅极沿着垂直衬底的方向延伸且具有侧壁，所述第二半导体层环绕所述侧壁，所述第二半导体层包括第二源接触区域；
    所述第一栅极沿着平行于所述衬底的方向延伸且具有侧壁和两个端部，所述第一半导体层至少环绕所述侧壁，所述两个端部的其中一个端部延伸到所述第二半导体层的第二源接触区域与所述第二半导体层接触。
  21. 根据权利要求20所述的存储单元，其中，所述第二半导体层的侧壁还包括第二漏接触区域；所述第二源接触区域和所述第二漏接触区域位于所述第二半导体层的侧壁的不同区域，且所述第二源接触区域和第二漏接触区域在垂直衬底的平面内的正投影具有重叠区域，使得所述第二源接触区域和所述第二漏接触区域之间的沟道平行于所述衬底；
    所述第一半导体层的侧壁具有第一源接触区域和第一漏接触区域，所述第一源接触区域和第一漏接触区域之间的沟道平行于所述衬底。
  22. 一种3D存储器，包括多层沿垂直于衬底的方向堆叠的存储单元，其中，
    每层所述存储单元包括：读晶体管和写晶体管；
    所述读晶体管包含第一栅极、第一半导体层，第一源电极和第一漏电极，所述第一栅极沿平行于所述衬底的方向延伸；所述写晶体管包含第二栅极、第二半导体层，第二源电极和第二漏电极，所述第二栅极沿垂直于所述衬底的方向延伸；
    所述写晶体管的第二源电极与所述读晶体管的第一栅极相连；所述第一半导体层环绕所述第一栅极，所述第二半导体层环绕所述第二栅极；所述写晶体管的第二半导体层的沟道为水平沟道。
  23. 根据权利要求22所述的3D存储器，其中，同层的所述读晶体管和写晶体管在所述衬底上沿着平行于所述衬底的方向间隔分布。
  24. 根据权利要求22所述的3D存储器，其中，所述读晶体管的第一栅极与所述写晶体管的第二源电极为一体结构。
  25. 根据权利要求22所述的3D存储器，其中，所述第一栅极沿着平行于所述衬底的第二方向延伸；
    所述第一半导体层包括第一源接触区域和第一漏接触区域，所述第二半导体层包括第二源接触区域和第二漏接触区域；
    每层所述存储单元还包括：沿着平行于所述衬底的第三方向延伸的第一位线，和第二位线，所述第三方向与所述第二方向交叉；所述第一位线与所述第一半导体层的第一漏接触区域连接，所述第二位线与所述第二半导体层的第二漏接触区域连接；
    每层所述存储单元还包括：分别沿着垂直于所述衬底的方向延伸的第一字线和第二字线；
    所述第一字线分别与不同层的所述存储单元的第一半导体层的第一源接触区域连接，所述第二字线分别与不同层的所述存储单元的第二栅极连接。
  26. 根据权利要求25所述的3D存储器，其中，所述第一字线环绕不同层的所述存储单元的每个第一半导体层的侧壁且与每个第一半导体层的侧壁的第一源接触区域连接。
  27. 根据权利要求25所述的3D存储器，其中，所述第一栅极具有侧壁、第一端部和第二端部，所述第一端部与所述第二半导体层的第二源接触区域连接，所述第一位线与所述第二端部连接。
  28. 一种3D存储器的制备方法，其特征在于，所述3D存储器包括多层沿垂直于衬底的方向堆叠的存储单元、第一字线和第二字线，每层所述存储单元包括：读晶体管和写晶体管，所述读晶体管包含第一栅极、第一半导体层，第一源电极和第一漏电极；所述写晶体管包含第二栅极、第二半导体层，第二源电极和第二漏电极，所述制备方法包括：
    提供衬底；
    在所述衬底上依次交替沉积绝缘薄膜和金属薄膜，进行构图形成包括交替设置的绝缘层和金属层的堆叠结构，所述金属层包括相连的第一子部和第二子部，以及，所述读晶体管的第一漏电极；
    刻蚀所述堆叠结构以形成贯穿所述堆叠结构的通孔，刻蚀所述第一子部形成第一通道，刻蚀所述第二子部形成第二通道，所述第一通道、所述第二通道与所述通孔贯通；
    在所述第一通道、第二通道和所述通孔构成的通道的侧壁依次沉积半导体薄膜、栅绝缘薄膜和完全填充所述通道的金属薄膜，刻蚀所述通孔内的所述栅绝缘薄膜和金属薄膜以形成位于所述第一通道的第一半导体层、第二源电极、第一栅极和位于所述第二通道的第二漏电极；
    在所述通孔的侧壁沉积半导体薄膜以形成所述写晶体管的第二半导体层，所述第二半导体层包括间隔设置的第二源接触区域和第二漏接触区域，所述第二源电极与所述第二源接触区域接触，所述第二漏电极与所述第二漏接触区域接触；所述第二源接触区域和所述第二漏接触区域之间的沟道为水平沟道；
    在所述通孔内沉积金属薄膜完全填充所述通孔以形成所述第二字线，不 同层的所述写晶体管的第二栅极为所述第二字线的一部分；
    构图形成沿着垂直于所述衬底的方向延伸的所述第一字线，不同层的所述读晶体管的第一源电极为所述第一字线的一部分。
  29. 一种电子设备，包括如权利要求1至17任一所述的存储单元，或者18至21任一所述的存储单元，或者包括如权利要求22至27任一所述的3D存储器。
PCT/CN2022/137319 2022-10-18 2022-12-07 存储单元、3d存储器及其制备方法、电子设备 WO2024082394A1 (zh)

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