WO2023221354A1 - 存储器、动态随机存取存储器和电子设备 - Google Patents

存储器、动态随机存取存储器和电子设备 Download PDF

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Publication number
WO2023221354A1
WO2023221354A1 PCT/CN2022/121069 CN2022121069W WO2023221354A1 WO 2023221354 A1 WO2023221354 A1 WO 2023221354A1 CN 2022121069 W CN2022121069 W CN 2022121069W WO 2023221354 A1 WO2023221354 A1 WO 2023221354A1
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memory
semiconductor layer
semiconductor
layer
memory cell
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PCT/CN2022/121069
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English (en)
French (fr)
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王祥升
王桂磊
赵超
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北京超弦存储器研究院
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Publication of WO2023221354A1 publication Critical patent/WO2023221354A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor devices, and in particular, to a memory, a dynamic random access memory and an electronic device.
  • DRAM Dynamic Random Access Memory
  • 1T1C Dynamic Random Access Memory
  • the industry generally uses a structure of one transistor and one capacitor as a DRAM unit.
  • This 1T1C component combination makes DRAM storage bits the electronic component with the highest density and the lowest unit manufacturing cost, and has an irreplaceable position in computer access devices.
  • DRAM components With the rapid development of semiconductor technology, DRAM components are rapidly developing towards high density and high quality.
  • the integration density of semiconductor devices has been continuously increased, and the design size standards of semiconductor devices have also been continuously reduced.
  • the world's top three DRAM companies are now entering the 1a technology node. Their gate length has reached 15nm (close to the 7nm of logic), making it difficult to further shrink, and it is also difficult to prepare capacitors to meet process requirements.
  • Embodiments of the present disclosure provide a 3D memory, including:
  • the memory unit includes a transistor and a capacitor arranged sequentially along the second direction.
  • the transistor includes a semiconductor layer and a gate.
  • the semiconductor layer extends along the second direction into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in the second direction include a source region, a channel region and a drain region, the source region and the drain region are respectively close to both ends of the semiconductor layer, the The channel region is located between the source region and the drain region, and the semiconductor layer includes a first semiconductor layer and a cylindrical second semiconductor layer disposed on the sidewall of the first semiconductor layer,
  • the gate electrode surrounds the sidewall of the second semiconductor layer in the channel region; the electrode and dielectric layer of the capacitor surround the sidewall of the second semiconductor layer in the drain region.
  • the 3D memory may further include: a plurality of bit lines extending along the first direction, two adjacent memory cells along the second direction being distributed in a mirror image, and the two adjacent memory cells are distributed in a mirror image.
  • the source regions of the cell's transistors are connected to a common bit line.
  • the 3D memory may further include: a plurality of word lines extending in the third direction and arranged at intervals in the first direction, wherein the substrate is provided with a memory cell column in the third direction.
  • each of the word lines is formed by a gate connection of a transistor of a memory cell in a memory cell column arranged along the third direction.
  • the plurality of word lines spaced apart along the first direction may have different lengths and form a ladder shape.
  • the material of the word line may include at least one of indium and tin.
  • the material of the first semiconductor layer may be selected from any one or more of Group IVA semiconductor materials.
  • the material of the first semiconductor layer is single crystal silicon.
  • the material of the second semiconductor layer may be a metal oxide semiconductor material, and the metal in the metal oxide includes at least one of indium, zinc, tungsten, tin, titanium, zirconium, hafnium, and gallium. one.
  • the memory cell column may further include an interlayer isolation layer.
  • the interlayer isolation layer is disposed between the gates of the transistors of two adjacent memory cells in the memory cell column. The gates of the transistors of two adjacent memory cells are isolated.
  • the 3D memory may further include one or more memory cell isolation pillars extending along a first direction, and one of the memory cell isolation pillars is provided every two memory cell columns in the second direction. .
  • the memory cell isolation pillar may be made of silicon oxide.
  • the 3D memory may further include an internal support layer disposed between two adjacent semiconductor layers along the first direction and configured to provide support for the semiconductor layer.
  • the inner support layer may be located on the sidewalls of the storage unit isolation pillars.
  • the material of the inner support layer may be silicon nitride (SiN).
  • An embodiment of the present disclosure also provides a memory, including:
  • a plurality of repeating units are distributed in an array, and each two adjacent repeating units are separated by isolation columns; wherein the repeating units include at least one layer of memory units, and each layer of the repeating units includes two of the repeating units.
  • One or more laterally extending semiconductor pillars are provided between the two isolation pillars, and the plurality of laterally extending semiconductor pillars are spaced apart along the direction perpendicular to the substrate;
  • the semiconductor pillar has sidewalls and two ends, the two ends being located in the isolation pillar such that the semiconductor pillar is supported by the isolation pillar;
  • a first annular semiconductor layer and a second annular semiconductor layer are spaced apart laterally in different areas of the sidewalls of the semiconductor pillars; the first annular semiconductor layer and the second annular semiconductor layer are respectively wrapped with spaced apart A first gate and a second gate, wherein the first gate and the first ring-shaped semiconductor layer are insulated by an insulating layer, and the second gate and the second ring-shaped semiconductor layer are insulated by an insulating layer. .
  • first memory unit includes the first capacitor and the first transistor
  • second The memory unit includes the second capacitor and the second transistor
  • the first capacitance electrode of the first capacitor and the second capacitance electrode of the second capacitor respectively wrap different areas of the side walls of the semiconductor pillar;
  • the first capacitor, the first transistor, the second transistor, and the second capacitor are laterally spaced and distributed in sequence.
  • Embodiments of the present disclosure also provide a dynamic random access memory, which includes the 3D memory as described above, or includes the memory as described above.
  • the present disclosure also provides an electronic device, including the dynamic random access memory as described above.
  • the electronic device may include a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
  • FIG. 1A is a schematic front cross-sectional structural diagram of a 3D memory in one direction according to an exemplary embodiment of the present disclosure
  • Figure 1B is an enlarged view of the transistor of the 3D memory shown in Figure 1A;
  • Figure 1C is an enlarged view of the capacitor of the 3D memory shown in Figure 1A;
  • Figure 1D is a schematic top structural view of the 3D memory shown in Figure 1A;
  • FIG. 2 is a distribution state diagram in the side view direction of a plurality of word lines spaced apart along the first direction of a 3D memory according to another exemplary embodiment of the present disclosure
  • Figure 3A is a schematic front cross-sectional structural diagram in one direction of a 3D memory according to another exemplary embodiment of the present disclosure
  • Figure 3B is a schematic top structural view of the 3D memory shown in Figure 3A;
  • Figure 4 is a process flow diagram of a memory manufacturing method according to an embodiment of the present disclosure.
  • 5A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • 5B is a schematic top structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • 6A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • 6B is a schematic top structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • FIG. 7A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • FIG. 7B is a schematic top structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • FIG. 8A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • FIG. 8B is a schematic top structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • 9A is a schematic front cross-sectional structural view and a schematic top structural view of an intermediate product obtained in the intermediate steps of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • 9B is a schematic front cross-sectional structural view and a schematic top structural view of an intermediate product obtained in the intermediate steps of the memory manufacturing method according to an exemplary embodiment of the present disclosure
  • Embodiments of the present disclosure provide a 3D memory.
  • the 3D memory provided by the embodiment of the present disclosure includes:
  • the memory unit includes a transistor and a capacitor arranged sequentially along the second direction.
  • the transistor includes a semiconductor layer and a gate.
  • the semiconductor layer extends along the second direction into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in the second direction include a source region, a channel region and a drain region, the source region and the drain region are respectively close to both ends of the semiconductor layer, the The channel region is located between the source region and the drain region, and the semiconductor layer includes a first semiconductor layer and a cylindrical second semiconductor layer disposed on the sidewall of the first semiconductor layer,
  • the gate electrode surrounds the sidewall of the second semiconductor layer in the channel region; the electrode and dielectric layer of the capacitor surround the sidewall of the second semiconductor layer in the drain region.
  • the 3D memory may further include: a plurality of bit lines extending along the first direction, and two adjacent memory cells along the second direction are distributed in a mirror image. The source regions of the transistors of the memory cells are connected to a common bit line.
  • the 3D memory may further include: a plurality of word lines extending in the third direction and spaced apart in the first direction, wherein the substrate is provided with one memory unit in the third direction. columns, each of the word lines is formed by a gate connection of a transistor of a memory cell of a memory cell column arranged along a third direction.
  • DRAM which is a 3D memory unit formed through a superlattice structure.
  • the multi-layer superlattice on the substrate is used to form multi-layer memory cells.
  • Each layer of memory cells can be memory cells distributed in an array.
  • the memory cells at the same position in each layer in the two-dimensional plane form a vertical direction.
  • a column of storage units is referred to as a storage unit column.
  • FIG. 1A is a schematic front cross-sectional structural diagram of a 3D memory in one direction according to an exemplary embodiment of the present disclosure
  • FIG. 1B is an enlarged view of a transistor of the 3D memory shown in FIG. 1A
  • FIG. 1C is a capacitor of the 3D memory shown in FIG. 1A an enlarged view
  • Figure 1D is a schematic top view of the structure of the 3D memory shown in Figure 1A.
  • the 3D memory may include:
  • a substrate 100 a plurality of memory cell columns 200 formed by stacked memory cells in a direction perpendicular to the substrate (the first direction in Figure A1), and a plurality of bit lines 300 (Bit lines) extending along the first direction. Line, BL), the two memory cell columns 200 in Figure 1A share a bit line 300.
  • a plurality of word lines 400 (Word Line, WL) extending in a third direction in a plane parallel to the upper surface of the substrate.
  • Figure 1A shows a three-layer memory unit formed by a three-layer superlattice. Each layer of memory unit corresponds to There is one word line 400, and there are a total of six word lines 400 in Figure 1A or Figure 1B.
  • each of the memory cell columns 200 includes a plurality of memory cells 1 stacked on one side of the substrate 100 along a first direction.
  • 100 is arranged along the second direction and the third direction to form a multi-layer array, the second direction and the third direction intersect and form a plane parallel to the main plane of the substrate;
  • the memory unit 1 includes a multi-layer array along the second direction and the third direction.
  • the transistor 10 and the capacitor 20 are arranged in sequence; the transistor 10 includes a semiconductor layer 11 and a gate 12.
  • the semiconductor layer 11 is strip-shaped and extends along the second direction.
  • the strip-shaped semiconductor layer 11 has two ends and side walls.
  • the sidewall includes a source region 111, a channel region 112 and a drain region 113 in sequence along the second direction, and the source region 111 and the drain region 113 are respectively close to the semiconductor.
  • the channel region 112 is located between the source region 111 and the drain region 113.
  • the semiconductor layer includes a first semiconductor layer 114 and a second semiconductor layer 115.
  • the first semiconductor layer 114 is strip-shaped with sidewalls, the cross-section of the first semiconductor layer 114 is rectangular, circular, oval, etc., the second semiconductor layer 115 surrounds the sidewalls of the first semiconductor layer 114, and the gate electrode 12
  • the sidewalls of the second semiconductor layer 115 surrounding the channel region 112; the electrodes and dielectric layers of the capacitor 20 surround the sidewalls of the second semiconductor layer 115 of the drain region 113.
  • the second semiconductor layer 115 may be cylindrical and disposed on the sidewall of the first semiconductor layer 114 , for example, may be disposed on the outer wall of the first semiconductor layer 114 , that is, the semiconductor layer may include a first semiconductor layer 114 and a cylindrical second semiconductor layer 115 disposed on the side wall of the first semiconductor layer.
  • the first semiconductor layers of the source region 111 , the channel region 112 and the drain region 113 are all surrounded by the second semiconductor layer, which is not shown in the upper figure of FIG. 1A
  • the second semiconductor layer at one end of the channel region 112 and the drain region 113 corresponding to the capacitor is related to the selection of the cross-sectional position in the upper diagram of FIG. 1A .
  • Every two adjacent memory units along the second direction are collectively regarded as a repeating unit.
  • Each repeating unit contains two structurally mirror-symmetric memory units.
  • two transistors are arranged adjacently, and capacitors located on a semiconductor layer are located at both ends.
  • a bit line 300 distributed along the vertical substrate direction is arranged between the two adjacent transistors.
  • the transistors and capacitors are mirror-symmetrically distributed about the bit lines.
  • the source regions 111 of the transistors 10 of each memory cell 1 in two adjacent memory cell columns 200 are connected to the same bit line 300 .
  • One or more memory cell columns 200 are disposed on the substrate 100 in the third direction; when the substrate 100 is disposed with one memory cell column 200 in the third direction, each of the word lines 400 is formed along the third direction.
  • the gate electrodes 12 of the transistors 10 of a memory cell 1 in each layer of a memory cell column 200 arranged in three directions are formed by connecting; or when the substrate 100 is provided with multiple memory cell columns 200 in a third direction, each The word lines 400 are formed by connecting together the gate electrodes 12 of the transistors 10 of a plurality of memory cells 1 arranged along the third direction and located in the same layer.
  • first direction is defined as the direction perpendicular to the plane where the substrate is located, that is, the direction in which the height of the 3D memory is located;
  • second direction is defined as the direction perpendicular to the plane of the substrate.
  • the "direction” is perpendicular to the direction in which the width of the substrate lies;
  • the “third direction” is defined as the direction perpendicular to the "first direction” and in which the length of the substrate lies; the second direction and the third direction
  • the intersecting and formed planes are parallel to the main plane of the substrate.
  • the "first direction”, “second direction” and “third direction” may be as shown in Figures 1A and 1D.
  • each memory cell column is formed by a plurality of memory cells stacked on one side of the substrate along the first direction.
  • the present disclosure treats one or more memory cells belonging to the same layer as a group.
  • the group of memory cells is stacked in a direction perpendicular to the substrate, and memory cell groups of different stacks form a column extending along the direction perpendicular to the substrate.
  • the plurality of groups form an array, that is to say, the memory unit groups of each layer form an array, or multiple columns formed by multiple stacked memory unit groups form an array. It can also be expressed as: multiple memory cell columns are arranged along the second direction and the third direction to form an array.
  • the 3D memory of the embodiment of the present disclosure adopts a lateral semiconductor layer (ie, a semiconductor layer extending along the second direction) and a lateral capacitor, so that the transistors and capacitors can form a three-dimensional stack structure, and the memory cells formed by the transistors and capacitors can be stacked together.
  • increasing the storage density of the 3D memory moreover, the sources of the transistors of multiple memory cells in two adjacent memory cell columns in the second direction share a bit line, which can also reduce the size of the 3D memory and further increase the
  • the storage density of 3D memory reduces the production cost per Gb and provides a new technology research and development direction under the shrinkage bottleneck of dynamic random access memory.
  • the semiconductor layer 11 may be a semiconductor pillar.
  • one memory unit column may include 2 to 100 memory units.
  • it may include 2, 3 (as shown in FIGS. 1A and 1B ), 4, 5, 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage units.
  • the substrate may be provided with 2 to 1000 memory cell columns along the second direction.
  • 2 (as shown in FIG. 1A and FIG. 1D), 4, or 6 may be provided.
  • the substrate can be provided with 1 to 100 memory cell columns along the third direction, for example,
  • the settings include 1, 2, 3 (as shown in Figure 1A and Figure 1D), 4, 5, 12, 14, 16, 18, 20, 30, 40, 50 , 60, 70, 80, 90, 100 storage unit columns.
  • the substrate may be a semiconductor substrate, for example, a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, silicon on sapphire (Silicon on Sapphire).
  • SOI semiconductor on insulator
  • SOS silicon on sapphire
  • SOG Silicon On Glass
  • silicon epitaxial layer or other semiconductor or optoelectronic material based on the base semiconductor such as silicon-germanium (Si 1-x Ge x , where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP).
  • the substrate may be doped or may be undoped.
  • the lengths of the plurality of word lines arranged at intervals along the first direction may be different, so that the plurality of word lines arranged along the first direction and located at different layers may form a ladder shape.
  • FIG. 2 is a distribution state diagram in a side view direction of a plurality of word lines spaced apart along a first direction of a 3D memory according to another exemplary embodiment of the present disclosure.
  • the plurality of word lines 400 spaced apart along the first direction have different extending lengths in the third direction, so that the plurality of word lines 400 arranged along the first direction and located at different layers can present a ladder shape.
  • the material of the word line may be a material compatible with the semiconductor layer.
  • the material of the word line may include at least one of indium and tin.
  • the material of the word line may be indium tin oxide ( Indium tin oxide, ITO), etc.
  • the material of the bit line may be selected from any one or more of tungsten, molybdenum (Mo), cobalt (Co) and other metal materials with similar properties.
  • the material of the first semiconductor layer may be selected from any one or more of Group IVA semiconductor materials, for example, it may be single crystal silicon.
  • the second semiconductor layer may be in the shape of a cylinder or a square cylinder.
  • the material of the second semiconductor layer may be an oxide semiconductor material, for example, it may be a metal oxide semiconductor material, and the metal in the metal oxide may include indium, zinc, tungsten, tin, At least one of titanium, zirconium, hafnium, and gallium.
  • the material of the second semiconductor layer can be selected from the group consisting of indium gallium zinc oxide (IGZO), zinc stannate (ZTO), and indium zinc oxide.
  • Oxide Indium Zinc Oxide, IZO, zinc oxide (ZnO x ), indium tungsten oxide (InWO), indium zinc tin oxide (Indium Zinc Tin Oxide, IZTO), indium oxide (InO x , for example, In 2 O 3 ), tin oxide (SnO x , for example, SnO 2 ), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide ( Six In y Zn z O a ), aluminum zinc tin oxide (Al x Zn y S
  • the semiconductor layer adopts a double-layer structure formed by a first semiconductor layer and a second semiconductor layer.
  • An oxide semiconductor film can be grown on a single crystal of the first semiconductor layer (for example, single crystal silicon) as the second semiconductor layer, which can be fully utilized.
  • the oxide semiconductor film has extremely small leakage characteristics, thereby increasing the switching ratio of the memory device.
  • the thickness of the second semiconductor layer may be 5 nm to 15 nm.
  • the height of the semiconductor layer along the first direction can be set according to actual electrical requirements, for example, it can be 10 nm to 50 nm.
  • the capacitor 20 may include a first electrode plate 21 and a second electrode plate 22 (both the first electrode plate and the second electrode plate belong to the electrodes of the capacitor). ), the dielectric layer 23 disposed between the first electrode plate 21 and the second electrode plate 22, the second semiconductor layer 115 of the drain region 113 is connected to the first electrode plate 21 . As shown in FIG. 1D , the outer plates 22 of multiple capacitors 20 arranged along the third direction may be connected together, but their first electrode plates 21 are separated.
  • the first electrode plate may be an inner electrode plate
  • the second electrode plate may be an outer electrode plate
  • one transistor 10 may correspond to one capacitor 20 , that is, the memory unit 1 may have a 1T1C structure.
  • two capacitors adjacent along the first direction may share a second electrode plate.
  • the materials of the first electrode plate and the second electrode plate may be independently selected from titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), etc., with similar properties. Any one or more types of other metallic materials.
  • the thickness of the first electrode plate may be 5 nm to 15 nm, and the thickness of the second electrode plate may be 5 nm to 15 nm.
  • the material of the dielectric layer may be a high dielectric constant (K) material, for example, it may be selected from hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide. Any one or more of ZrO and strontium titanate (SrTiO 3 , STO).
  • the thickness of the dielectric layer may be 5 nm to 15 nm.
  • the memory cell column 200 may further include an interlayer isolation layer 2 , and the interlayer isolation layer 2 is disposed adjacent to the memory cell column 200 . Between the gate electrodes 12 of the transistors 10 of the two memory cells 1, the gate electrodes 12 of the transistors 10 of the two adjacent memory cells 1 are isolated.
  • the interlayer isolation layer may be made of silicon oxide, for example, SiO 2 .
  • the interlayer isolation layer may be an interlayer isolation tape.
  • the transistor may further include a gate dielectric layer (also called a gate insulating layer, not shown in the figure).
  • the gate dielectric layer is disposed between the channel region and the gate. between extremes.
  • the material of the gate dielectric layer may be selected from any one of silicon dioxide, hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide ZrO, or more. Various.
  • the thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.
  • the material of the gate may be selected from any one or more of ITO or other low-temperature semiconductor materials.
  • the 3D memory may further include one or more memory cell isolation pillars 500 extending along the first direction.
  • one of the memory cell isolation pillars 500 may be provided every two memory cell columns 200 in the second direction.
  • the material of the memory cell isolation pillar may be silicon oxide, for example, it may be selected from spin-on deposition (SOD) silicon oxide film, high density plasma (HDP) ) silicon oxide film and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide film any one or more.
  • SOD spin-on deposition
  • HDP high density plasma
  • HARP High Aspect Ratio Process
  • the 3D memory may further include an internal support layer 600 disposed between two adjacent semiconductor layers 11 along the first direction, configured as Support is provided for the semiconductor layer 11 .
  • the internal support layer 600 may also be located on both sides of the memory cell isolation pillar 500 .
  • the internal support layers 600 are provided on both sides of the memory cell isolation pillar 500, firm support can be provided for the semiconductor layer 11.
  • the material of the internal support layer may be a thin film material with a supporting function, for example, it may be SiN.
  • FIG. 3A is a schematic front cross-sectional structural view of a 3D memory in one direction according to another exemplary embodiment of the present disclosure.
  • FIG. 3B is a schematic top structural view of the 3D memory shown in FIG. 3A .
  • the empty space between the semiconductor layer, the bit line, and the word line may be filled with an isolation material 700 .
  • the isolation material may be selected from any one or more of SOD silicon oxide film, HDP silicon oxide film, and HARP silicon oxide film.
  • An embodiment of the present disclosure also provides a memory, including:
  • a plurality of repeating units are distributed in an array, and each two adjacent repeating units are separated by isolation columns; wherein the repeating units include at least one layer of memory units, and each layer of the repeating units includes two of the repeating units.
  • One or more laterally extending semiconductor pillars are provided between the two isolation pillars, and the plurality of laterally extending semiconductor pillars are spaced apart along the direction perpendicular to the substrate;
  • the semiconductor pillar has sidewalls and two ends, the two ends being located in the isolation pillar such that the semiconductor pillar is supported by the isolation pillar;
  • first annular semiconductor layers for example, the first semiconductor layer in the 3D memory provided by the embodiments of the present application
  • second annular semiconductor layers for example, the first annular semiconductor layers implemented by the present application.
  • the second semiconductor layer in the 3D memory provided by the example); the first ring-shaped semiconductor layer and the second ring-shaped semiconductor layer are respectively wrapped with first gates and second gates arranged at intervals, wherein the A gate electrode and the first annular semiconductor layer are insulated by an insulating layer, and the second gate electrode and the second annular semiconductor layer are insulated by an insulating layer;
  • first memory unit includes the first capacitor and the first transistor
  • second The memory unit includes the second capacitor and the second transistor
  • the first capacitance electrode of the first capacitor and the second capacitance electrode of the second capacitor respectively wrap different areas of the side walls of the semiconductor pillar;
  • the first capacitor, the first transistor, the second transistor, and the second capacitor are distributed in order at lateral intervals.
  • An embodiment of the present disclosure also provides a method of manufacturing a memory. As mentioned above, the memory provided by the embodiments of the present disclosure (including the 3D memory provided by the embodiments of the present disclosure) can be obtained by this manufacturing method.
  • FIG. 4 is a process flow diagram of a memory manufacturing method according to an embodiment of the present disclosure. As shown in Figure 4, the manufacturing method may include:
  • a plurality of epitaxial layers composed of the sacrificial layer and the first initial semiconductor layer are stacked and arranged along the first direction in the order of the sacrificial layer and the first initial semiconductor layer on one side of the substrate;
  • S20 Define memory cell regions in the plurality of epitaxial layers, etch memory cell isolation trenches along the first direction, and fill memory cell isolation pillars in the memory cell isolation trenches;
  • S30 Remove the sacrificial layer, and the remaining first initial semiconductor layer forms a first semiconductor layer, and a cylindrical second semiconductor layer is provided on the side wall of the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer Form a plurality of semiconductor layers with a strip structure arranged in arrays along the first direction and the third direction and extending along the second direction.
  • the semiconductor layer includes source regions and drain regions located at both ends in the second direction. a channel region between the source region and the drain region;
  • S40 Set a gate of the second semiconductor layer surrounding the channel region on the sidewall of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate. ; And, there is one semiconductor layer arranged in the third direction, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that there are multiple semiconductor layers arranged in the third direction.
  • the gate electrodes on the semiconductor layer are connected together in the third direction to form a word line;
  • S50 Set a capacitor surrounding one end of the second semiconductor layer in the drain region on the side wall of the second semiconductor layer in the drain region away from the channel region.
  • the electrodes and dielectric of the capacitor The quality layers are all surrounding the sidewalls of the second semiconductor layer in the drain region;
  • S60 Open bit line trenches penetrating the semiconductor layers in the bit line areas of the plurality of semiconductor layers arranged along the first direction, and the bit line trenches in the bit line trenches and the bit line trenches of the plurality of semiconductor layers arranged along the first direction.
  • Bit line material is filled in between to form a bit line extending along the first direction, and the bit line is connected to the source regions of the plurality of semiconductor layers in contact with the bit line, so that the source regions of the plurality of semiconductor layers are The source regions share a bit line.
  • step S20 may include:
  • S21 Define memory cell regions in the plurality of epitaxial layers, and etch memory cell isolation trenches along the first direction;
  • S22 Perform side etching on the portion corresponding to the memory cell isolation trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support layer;
  • step S40 may include:
  • S41 Sequentially arrange the gate dielectric layer and the gate electrode of the second semiconductor layer surrounding the channel region on the sidewalls of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of gate dielectric layers composed of the semiconductor layer and the gate electrode.
  • S42 Set the extension lengths of the multiple word lines arranged along the first direction in the third direction to be different, so that the multiple word lines arranged along the first direction and located at different layers present a ladder shape;
  • S43 Set an interlayer isolation layer between two adjacent semiconductor layers along the first direction to isolate the gates on the two adjacent semiconductor layers along the first direction.
  • step S40 may include:
  • S41 Sequentially arrange the gate dielectric layer and the gate electrode of the second semiconductor layer surrounding the channel region on the sidewalls of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of gate dielectric layers composed of the semiconductor layer and the gate electrode.
  • step S40 may include:
  • S41 Sequentially arrange the gate dielectric layer and the gate electrode of the second semiconductor layer surrounding the channel region on the sidewalls of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of gate dielectric layers composed of the semiconductor layer and the gate electrode.
  • S42 Set the extension lengths of the multiple word lines arranged along the first direction in the third direction to be different, so that the multiple word lines arranged along the first direction and located at different layers present a ladder shape;
  • step S40 may include:
  • S41 Sequentially arrange the gate dielectric layer and the gate electrode of the second semiconductor layer surrounding the channel region on the sidewalls of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of gate dielectric layers composed of the semiconductor layer and the gate electrode.
  • S43 Set an interlayer isolation layer between two adjacent semiconductor layers along the first direction to isolate the gates on the two adjacent semiconductor layers along the first direction;
  • step S40 may include:
  • S41 Sequentially arrange the gate dielectric layer and the gate electrode of the second semiconductor layer surrounding the channel region on the sidewalls of the second semiconductor layer in the channel region of the semiconductor layer to obtain a plurality of gate dielectric layers composed of the semiconductor layer and the gate electrode.
  • S42 Set the extension lengths of the multiple word lines arranged along the first direction in the third direction to be different, so that the multiple word lines arranged along the first direction and located at different layers present a ladder shape;
  • An interlayer isolation layer is provided between two adjacent semiconductor layers along the first direction to isolate the gate electrodes on the two adjacent semiconductor layers along the first direction.
  • step S50 may include: sequentially arranging one end of the second semiconductor layer surrounding the drain region on a sidewall of an end of the second semiconductor layer in the drain region of the semiconductor layer away from the channel region.
  • the first electrode plate, the dielectric layer and the second electrode plate are used to obtain a capacitor surrounding one end of the second semiconductor layer in the drain region.
  • the manufacturing method further includes: after step S60,
  • S70 Fill the empty space between the semiconductor layer, the bit line and the word line with an isolation material.
  • FIGS. 5A to 9B are schematic front cross-sectional structural views and a schematic top structural view of an intermediate product obtained in an intermediate step of the memory manufacturing method according to an exemplary embodiment of the present disclosure.
  • the memory manufacturing method may include:
  • a plurality of epitaxial layers composed of the sacrificial layer 800 and the first initial semiconductor layer 114' are stacked in the order of the sacrificial layer 800 and the first initial semiconductor layer 114' on one side of the substrate 100 along the first direction, as shown in the figure. 5A and the intermediate product shown in Figure 5B;
  • S21 Define memory cell regions 1' in the plurality of epitaxial layers, and etch memory cell isolation trenches 500' along the first direction;
  • S22 Perform side etching on the portion corresponding to the memory cell isolation trench 500' and the sacrificial layer 800 along the second direction to obtain an internal support trench 600', and fill the internal support layer in the internal support trench 600'. 600;
  • S30 Remove the sacrificial layer 800, and the remaining first initial semiconductor layer 114' forms the first semiconductor layer 114.
  • a cylindrical second semiconductor layer 115 is provided on the side wall of the first semiconductor layer 114.
  • the first semiconductor layer 114 and the second semiconductor layer 115 to form a plurality of semiconductor layers 11 arranged in arrays along the first direction and the third direction and extending along the second direction.
  • the semiconductor layer 11 includes source regions 111 at both ends in the second direction. and the drain region 113 and the channel region 112 located between the source region 111 and the drain region 113 to obtain an intermediate product as shown in Figures 7A and 7B;
  • a gate dielectric layer (not shown in the figure) and a gate surrounding the second semiconductor layer 115 of the channel region 112 are sequentially provided.
  • electrode 12 to obtain a plurality of transistors 10 formed by the semiconductor layer 11 and the gate electrode 12; and, there is one semiconductor layer 11 arranged in the third direction, so that the gate electrode 12 on this semiconductor layer 11 serves as a word Line 400; or, there are multiple semiconductor layers 11 arranged in the third direction, so that the gate electrodes 12 on the multiple semiconductor layers 11 arranged in the third direction are connected together in the third direction to form the word line 400;
  • S42 Set the extension lengths of the plurality of word lines 400 arranged along the first direction in the third direction to be different, so that the plurality of word lines 400 arranged along the first direction and located at different layers present a ladder shape;
  • S50 Sequentially set the first electrode surrounding one end of the second semiconductor layer 115 of the drain region 113 on the sidewall of the end of the second semiconductor layer 115 of the drain region 113 of the semiconductor layer 11 away from the channel region 112
  • the plate 21, the dielectric layer 23 and the second electrode plate 22 are used to obtain the capacitor 20 surrounding one end of the second semiconductor layer 115 of the drain region 113, and the intermediate product shown in Figure 9A and Figure 9B is obtained;
  • a bit line trench 300' penetrating the semiconductor layer 11 is opened in the bit line region of the plurality of semiconductor layers 11 arranged along the first direction.
  • Bit line materials are filled between the bit line trenches of the semiconductor layer 11 to form a bit line 300 extending along the first direction.
  • the bit line 300 and the sources of the plurality of semiconductor layers 11 in contact with the bit line 300 are The regions 111 are connected so that the source regions 111 of the plurality of semiconductor layers 11 share the one bit line 300, thereby obtaining a 3D memory as shown in Figures 1A to 1D;
  • S70 Fill the empty space between the semiconductor layer 11, the bit line 300 and the word line 400 with the isolation material 700 to obtain the 3D memory as shown in FIG. 3A and FIG. 3B.
  • the material of the sacrificial layer may be any one or more of other conductive materials with similar properties such as SiGe.
  • the thickness of the sacrificial layer may be 30 nm to 50 nm, for example, it may be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.
  • a super lattice film stack of sacrificial layer/first initial semiconductor layer can be grown on the substrate through epitaxial equipment, to obtain a plurality of sacrificial layers and a first initial semiconductor layer.
  • An epitaxial layer composed of an initial semiconductor layer.
  • the same layer of patterned photo mask can be used to perform patterning and etching through light exposure to form trenches arranged along the third direction and extending along the second direction to combine multiple sacrifices.
  • the layer/first initial semiconductor layer forms an isolation in the third direction to obtain a memory cell region.
  • the memory cell isolation trench can be obtained by reactive-ion etching (RIE).
  • RIE reactive-ion etching
  • step S22 the portion of the memory cell isolation trench corresponding to the sacrificial layer may be side-etched by wet etching.
  • the internal support layer in step S22, can be filled in the internal support layer groove through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, such as , SiN can be filled in the internal support layer groove through the ALD process to form the internal support layer.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the memory cell isolation pillars can be filled in the memory cell isolation trench through SOD, HDP or HARP process.
  • the memory cell isolation pillars can be filled in the memory cell isolation trench through SOD, HDP or HARP process. Silicon oxide films are filled to form memory cell isolation pillars.
  • the sacrificial layer in step S30, can be etched away while retaining the first initial semiconductor layer by selecting an ultra-high sacrificial layer/first initial semiconductor layer etching ratio.
  • the etching method can Either dry etching or wet etching.
  • a cylindrical second semiconductor layer may be provided on the side wall of the first semiconductor layer through an ALD process.
  • a staircase word line (staircase WL) can be obtained by trim etch.
  • the interlayer isolation layer in step S43, can be set through ALD or chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • ALD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • SiO 2 can be filled through ALD or CVD process to form the interlayer isolation layer.
  • the isolation material in step S70, can be filled in the blank space through SOD, HDP or HARP process.
  • an SOD silicon oxide film and an HDP silicon oxide film can be formed in the blank space through SOD, HDP or HARP process. and any one or more of HARP silicon oxide films.
  • Embodiments of the present disclosure also provide a dynamic random access memory (DRAM), which includes the 3D memory as described in the embodiments of the present application, or includes the memory as described in the embodiments of the present application.
  • DRAM dynamic random access memory
  • An embodiment of the present disclosure also provides an electronic device, including the dynamic random access memory as described above.
  • the electronic device may include a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
  • connection and “arrangement” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection;
  • connection and “setting” can mean direct connection, indirect connection through an intermediary, or internal connection between two components.
  • connection and “setting” can mean direct connection, indirect connection through an intermediary, or internal connection between two components.

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Abstract

一种存储器、动态随机存取存储器和电子设备，所述存储器可以为3D存储器，包括：衬底；多个在垂直于衬底的第一方向上分布的存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置的多个存储单元；所述存储单元包括晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层包括第一半导体层和设置在所述第一半导体层的侧壁的筒状的第二半导体层，晶体管和电容器的其他结构与说明书的定义相同。

Description

[根据细则37.2由ISA制定的发明名称]　存储器、动态随机存取存储器和电子设备
本公开要求于2022年5月17日提交中国专利局、申请号为2022105420884、发明名称为“一种半导体器件结构及其制造方法、DRAM和电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开涉及半导体器件领域，尤指一种存储器、动态随机存取存储器和电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，每年的产值占整个半导体行业的30％左右。目前，业界普遍采用一个晶体管搭配一个电容器的结构作为一个DRAM单元。这种1T1C元件组合使DRAM的存储位元成为了密度最高、单位制造成本最低的电子元件，在计算机存取器件中具有不可替代的地位。随着半导体技术的飞速发展，DRAM元件正快速地向高密度、高质量的方向发展。为了快速提高存储器的集成度和可扩展性，半导体器件的集成密度被不断增加，半导体器件的设计尺寸标准也随之不断减小。然而，现在世界前三大DRAM公司正在进入1a技术节点，其栅极长度已经到达15nm(和逻辑的7nm接近)，较难再进一步微缩，而且电容的制备也较难达到工艺要求。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本公开的保护范围。
本公开实施例提供了一种3D存储器，包括：
衬底；
衬底；
多个在垂直于所述衬底的第一方向上分布的存储单元列，每个所述存储单元列均包括沿所述第一方向堆叠设置的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列；所述第二方向和第三方向交叉且构成的平面与所述衬底的主平面平行；
所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述半导体层包括第一半导体层和设置在所述第一半导体层的侧壁的筒状的第二半导体层，所述栅极环绕在所述沟道区的第二半导体层的侧壁；所述电容器的电极和介电质层环绕在所述漏极区的第二半导体层的侧壁。
在本公开实施例中，所述3D存储器还可以包括：多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区均与一条共用的位线连接。
在本公开实施例中，所述3D存储器还可以包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述衬底在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极连接形成。
在本公开实施例中，沿第一方向间隔排列的多条字线的长度可以不同，形成阶梯状。
在本公开实施例中，所述字线的材料可以包含铟和锡至少之一。
在本公开实施例中，所述第一半导体层的材料可以选自第IVA族半导体材料中的任意一种或更多种，例如，所述第一半导体层的材料为单晶硅。
在本公开实施例中，所述第二半导体层的材料可以为金属氧化物半导体材料，所述金属氧化物中的金属包含铟、锌、钨、锡、钛、锆、铪、镓中的至少之一。
在本公开实施例中，所述存储单元列还可以包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
在本公开实施例中，所述3D存储器还可以包括一个或多个沿第一方向延伸的存储单元隔离柱，在第二方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
在本公开实施例中，所述存储单元隔离柱的材料可以为氧化硅。
在本公开实施例中，所述3D存储器还可以包括内部支撑层，所述内部支撑层设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
在本公开实施例中，所述内部支撑层可以位于所述存储单元隔离柱的侧壁上。
在本公开实施例中，所述内部支撑层的材料可以为氮化硅(SiN)。
本公开实施例还提供一种存储器，包括：
多个阵列分布的重复单元，每相邻两个所述重复单元之间通过隔离柱隔离；其中，所述重复单元中包含至少一层存储单元，每层所述重复单元包含位于两个所述隔离柱之间的第一存储单元和第二存储单元；其中，所述两个存储单元包含第一晶体管和第二晶体管；
两个所述隔离柱之间设置有一条或多条横向延伸的半导体柱，所述多条横向延伸的半导体柱沿着垂直衬底的方向间隔分布；
所述半导体柱具有侧壁和两个端部，所述两个端部位于所述隔离柱中使得所述半导体柱由所述隔离柱支撑；
所述半导体柱的侧壁不同区域在横向上间隔分布有第一环形半导体层和第二环形半导体层；分别在所述第一环形半导体层和所述第二环形半导体层上包裹有间隔设置的第一栅极和第二栅极，其中所述第一栅极与所述第一环形半导体层通过绝缘层相绝缘，所述第二栅极与所述第二环形半导体层通过绝缘层相绝缘。
其中，还包括所述半导体柱的侧壁不同区域在横向上间隔分布有第一电 容器和第二电容器，所述第一存储单元包含所述第一电容器与所述第一晶体管，所述第二存储单元包含所述第二电容器与所述第二晶体管；
所述第一电容器的第一电容电极和所述第二电容器的第二电容电极分别包裹所述半导体柱的侧壁的不同区域；
其中，
所述第一电容器、所述第一晶体管、所述第二晶体管、所述第二电容器横向间隔依次分布。
本公开实施例还提供一种动态随机存取存储器，包括如上所述的3D存储器，或者，包括如上所述的存储器。
本公开还提供一种电子设备，包括如上所述的动态随机存取存储器。
在本公开实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本公开而了解。本公开的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1A为本公开示例性实施例的3D存储器的一个方向的主视剖面结构示意图；
图1B为图1A所示的3D存储器的晶体管的放大图；
图1C为图1A所示的3D存储器的电容器的放大图；
图1D为图1A所示的3D存储器的俯视结构示意图；
图2为本公开另一示例性实施例的3D存储器的沿第一方向间隔排列的多条字线在侧视方向上的分布状态图；
图3A为本公开另一示例性实施例的3D存储器的一个方向的主视剖面 结构示意图；
图3B为图3A所示的3D存储器的俯视结构示意图；
图4为本公开实施例的存储器的制造方法的工艺流程图；
图5A为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图5B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的俯视结构示意图；
图6A为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图6B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的俯视结构示意图；
图7A为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图7B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的俯视结构示意图；
图8A为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图8B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的俯视结构示意图；
图9A为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图和俯视结构示意图；
图9B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图和俯视结构示意图；
附图中的标记符号的含义为：
100-衬底；200-存储单元列；300-位线；300’-位线槽；400-字线；500-存储单元隔离柱；500’-存储单元隔离槽；600-内部支撑层；600’-内部支撑槽；700-隔离材料；800-牺牲层；1-存储单元；1’-存储单元区；10-晶体管；11- 半导体层；111-源极区；112-沟道区；113-漏极区；114-第一半导体层；114’-第一初始半导体层；115-第二半导体层；12-栅极；20-电容器；21-第一电极板；22-第二电极板；23-介电质层；2-层间隔离层。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本公开的描述中，“第一”、“第二”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
本公开实施例提供了一种3D存储器。
本公开实施例提供的所述3D存储器包括：
衬底；
多个在垂直于所述衬底的第一方向上分布的存储单元列，每个所述存储单元列均包括沿所述第一方向堆叠设置的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列；所述第二方向和第三方向交叉且构成的平面与所述衬底的主平面平行；
所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述半导体层包括第一半导体层和设置在所述第一半导体层的侧壁的筒状的第二半导体层，所述栅极环绕在所述沟道区的第二半导体层的侧壁；所述电容器的电极和介电质层环绕在所述漏极区的第二半导体层的侧壁。
在本示例性实施例中，所述3D存储器还可以包括：多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区均与一条共用的位线连接。
在本示例性实施例中，所述3D存储器还可以包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述衬底在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极连接形成。
具体可以应用于DRAM领域，为通过超晶格结构形成的3D存储单元。
具体的，衬底上的多层超晶格用于形成多层存储单元，每层存储单元可以是阵列分布的存储单元，各层中在二维平面中相同位置的存储单元构成一个垂直方向的一列存储单元，简称存储单元列。
以下将以两个存储单元列为例说明本申请。图1A为本公开示例性实施例的3D存储器的一个方向的主视剖面结构示意图，图1B为图1A所示的3D存储器的晶体管的放大图；图1C为图1A所示的3D存储器的电容器的放大图；图1D为图1A所示的3D存储器的俯视结构示意图。如图1A至图1D所示，所述3D存储器可以包括：
衬底100、多个在垂直于衬底的方向上(图A1中的第一方向)叠层分布的由存储单元形成的存储单元列200、多条沿第一方向延伸的位线300(Bit Line,BL)，图1A中两个存储单元列200共用一条位线300。
多条在平行于衬底上表面的平面内沿第三方向延伸的字线400(Word Line,WL)，其中，图1A为三层超晶格形成的三层存储单元，每层存储单元对应有一条字线400，图1A或图1B中共有6条字线400。
如图1所示，每个所述存储单元列200均包括沿第一方向堆叠设置在所述衬底100一侧的多个存储单元1，所述多个存储单元列200在所述衬底100上沿第二方向和第三方向排列形成多层阵列，所述第二方向和第三方向交叉且构成的平面与所述衬底的主平面平行；所述存储单元1包括沿着第二方向依次设置的晶体管10和电容器20；所述晶体管10包括半导体层11和栅极12，所述半导体层11为条状且沿第二方向延伸，条状半导体层11具有两端和侧壁，并且在所述侧壁上沿着所述第二方向上依次包括源极区111、沟道区112和漏极区113，所述源极区111和所述漏极区113分别靠近所述半导体层11的两端，所述沟道区112位于所述源极区111和所述漏极区113之间，所述半导体层包括第一半导体层114和第二半导体层115，第一半导体层114 为条状具有侧壁，第一半导体层114的横截面为矩形、圆形、椭圆形等，所述第二半导体层115环绕所述第一半导体层114的侧壁，所述栅极12环绕在所述沟道区112的第二半导体层115侧壁；所述电容器20的电极和介电质层环绕在所述漏极区113的第二半导体层115的侧壁。
在本示例性实施例中，如图1A所示，第二半导体层115可以为筒状的，设置在第一半导体层114的侧壁上，例如，可以设置在第一半导体层114的外壁上，即所述半导体层可以包括第一半导体层114和设置在所述第一半导体层侧壁上的筒状的第二半导体层115。
在本示例性实施例中，所述源极区111、所述沟道区112和所述漏极区113的第一半导体层均被所述第二半导体层环绕，图1A上图中未示出沟道区112和电容器对应的漏极区113一端的第二半导体层，这与图1A上图的剖面位置的选择有关。
沿第二方向上每相邻两个存储单元整体作为一个重复单元，第二方向上有2n个存储单元时，有n个重复单元，每个重复单元包含两个结构上镜像对称的存储单元。一个重复单元中，两个晶体管相邻设置，位于一个半导体层上的电容器位于两端，两个相邻设置的晶体管之间设置有沿垂直衬底方向分布的位线300，两个存储单元中的晶体管和电容器关于所述位线镜像对称分布。
在第一方向上，相邻的两个存储单元列200的各存储单元1的晶体管10的源极区111均与同一条的位线300连接。
所述衬底100上在第三方向上设置有一个或多个存储单元列200；当所述衬底100在第三方向上设置有一个存储单元列200时，每条所述字线400由沿第三方向排列的一个存储单元列200的各个层的一个存储单元1的晶体管10的栅极12连接形成；或者，当所述衬底100在第三方向上设置有多个存储单元列200时，每条所述字线400由沿第三方向排列的多个存储单元1的位于同一层的晶体管10的栅极12连接在一起形成。
在本公开的描述中，“第一方向”定义为与所述衬底所在的平面垂直的方向，即所述3D存储器的高度所在的方向；“第二方向”定义为与所述“第一方向”垂直并且所述衬底的宽度所在的方向；“第三方向”定义为与所述 “第一方向”垂直并且所述衬底的长度所在的方向；所述第二方向和第三方向交叉且构成的平面与所述衬底的主平面平行。“第一方向”、“第二方向”和“第三方向”可以如图1A和图1D所示。
在本公开的描述中，每个存储单元列均由沿第一方向堆叠设置在衬底一侧的多个存储单元形成，本公开将属于同一层的一个或多个存储单元作为一个组，该该组存储单元在垂直衬底的方向叠层设置，不同叠层的存储单元组构成沿着垂直衬底方向延伸的列。
所述的多个组构成一个阵列，也就是说每个层的存储单元组构成一个阵列，或多个叠层的存储单元组形成的多列构成一个阵列。还可以表述为：多个存储单元列沿第二方向和第三方向排列形成阵列。
本公开实施例的3D存储器通过采用横向半导体层(即沿第二方向延伸的半导体层)和横向电容器，使得晶体管和电容器可以形成立体堆叠结构，并且由晶体管和电容器形成的存储单元可以堆叠在一起，增加了3D存储器的存储密度；而且，在第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极共用一条位线，也可以减小3D存储器的尺寸，进一步增加3D存储器的存储密度，从而减少单位Gb的制作成本，为动态随机存取存储器微缩瓶颈下，提供了一种新的技术研发方向。在本公开实施例中，半导体层11可以为半导体柱。
在本公开实施例中，一个存储单元列可以包括2个至100个存储单元，例如，可以包括2个、3个(如图1A和图1B所示)、4个、5个、10个、13个、15个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元。
在本公开实施例中，所述衬底沿第二方向上可以设置有2个至1000个存储单元列，例如，可以设置有2个(如图1A和图1D所示)、4个、6个、8个、10个、12个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个、200个、300个、400个、500个、600个、700个、800个、900个、1000个存储单元列；所述衬底沿第三方向上可以设置有1个至100个存储单元列，例如，可以设置有1个、2个、3个(如图1A和图1D所示)、4个、5个、12个、14个、16个、18个、20个、30个、 40个、50个、60个、70个、80个、90个、100个存储单元列。
在本公开实施例中，所述衬底可以为半导体衬底，例如，可以为单晶硅衬底，还可以为绝缘体上半导体(Semiconductor on Insulator,SOI)衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层或其它半导体或光电材料，例如硅-锗(Si 1-xGe x，其中x可以是例如0.2与0.8之间的摩尔分数)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP)。所述衬底可经掺杂或可未经掺杂。
在本公开实施例中，沿第一方向间隔排列的多条字线的长度可以不同，使得沿第一方向排列的位于不同层的多条字线可以形成阶梯状。
图2为本公开另一示例性实施例的3D存储器的沿第一方向间隔排列的多条字线在侧视方向上的分布状态图。如图2所示，沿第一方向间隔排列的多条字线400在第三方向上的延伸长度不同，使得沿第一方向排列的位于不同层的多条字线400可以呈现出阶梯状。
在本公开实施例中，所述字线的材料可以为与所述半导体层兼容的材料，例如，所述字线的材料可以包含铟和锡至少之一，还例如，可以为氧化铟锡(Indium tin oxide,ITO)等。
在本公开实施例中，所述位线的材料可以选自钨、钼(Mo)、钴(Co)等具有相似性质的其他金属材料中的任意一种或更多种。
在本公开实施例中，所述第一半导体层的材料可以选自第IVA族半导体材料中的任意一种或更多种，例如，可以为单晶硅。
在本公开实施例中，所述第二半导体层可以为圆筒状或方筒状。
在本公开实施例中，所述第二半导体层的材料可以为氧化物半导体材料，例如，可以为金属氧化物半导体材料，所述金属氧化物中的金属可以包含铟、锌、钨、锡、钛、锆、铪、镓中的至少之一，又例如，所述第二半导体层的材料可以选自铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO)、锡酸锌(ZTO)、铟锌氧化物(Indium Zinc Oxide,IZO)、锌氧化物(ZnO x)、铟钨氧化物(InWO)、铟锌锡氧化物(Indium Zinc Tin Oxide,IZTO)、铟氧 化物(InO x，例如，In 2O 3)、锡氧化物(SnO x，例如，SnO 2)、钛氧化物(TiO x)、锌氮氧化物(Zn xO yN z)、镁锌氧化物(Mg xZn yO z)、锆铟锌氧化物(Zr xIn yZn zO a)、铪铟锌氧化物(Hf xIn yZn zO a)、铝锡铟锌氧化物(Al xSn yIn zZn aO d)、硅铟锌氧化物(Si xIn yZn zO a)、铝锌锡氧化物(Al xZn ySn zO a)、镓锌锡氧化物(Ga xZn ySn zO a)、锆锌锡氧化物(Zr xZn ySn zO a)和铟镓硅氧化物(InGaSiO x)中的任意一种或更多种。
半导体层采用由第一半导体层和第二半导体层形成的双层结构，可以在第一半导体层(例如，单晶硅)的单晶上生长氧化物半导体薄膜作为第二半导体层，可以充分利用氧化物半导体薄膜极小漏电的特性，从而增大存储器件的开关比。
在本公开实施例中，所述第二半导体层的厚度可以为5nm至15nm。
在本公开实施例中，所述半导体层沿第一方向上的高度可以根据实际的电性需求来设置，例如，可以为10nm至50nm。
在本公开实施例中，如图1A和图1C所示，所述电容器20可以包括第一电极板21、第二电极板22(第一电极板、第二电极板都属于所述电容器的电极)、设置在所述第一电极板21和所述第二电极板22之间的介电质层23，所述漏极区113的第二半导体层115与所述第一电极板21相连接。如图1D所示，沿第三方向排列的多个电容器20的外极板22可以连接在一起，但其第一电极板21是分开的。
在本公开实施例中，所述第一电极板可以是内电极板，所述第二电极板可以是外电极板。
在本公开实施例中，如图1A和图1B所示，一个晶体管10可以对应一个电容器20，即所述存储单元1可以为1T1C结构。
在本公开实施例中，沿第一方向相邻的两个电容器可以共用一个第二电极板。
在本公开实施例中，所述第一电极板和所述第二电极板的材料可以各自独立地选自氮化钛(TiN)、钛铝(TiAl)、氮化钽(TaN)等具有相似性质的其他金属材料的任意一种或更多种。所述第一电极板的厚度可以为5nm至 15nm，所述第二电极板的厚度可以为5nm至15nm。
在本公开实施例中，所述介电质层的材料可以为高介电常数(K)材料，例如，可以选自二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆ZrO和钛酸锶(SrTiO 3,STO)中的任意一种或更多种。所述介电质层的厚度可以为5nm至15nm。
在本公开实施例中，如图1A和图1D所示，所述存储单元列200还可以包括层间隔离层2，所述层间隔离层2设置在所述存储单元列200中相邻的两个存储单元1的晶体管10的栅极12之间，将相邻的两个存储单元1的晶体管10的栅极12隔离开。
在本公开实施例中，所述层间隔离层的材料可以为氧化硅，例如，可以为SiO 2。
在本公开实施例中，所述层间隔离层可以为层间隔离带。
在本公开实施例中，所述晶体管还可以包括栅极介电层(又叫栅极绝缘层，图中未示)，所述栅极介电层设置在所述沟道区与所述栅极之间。
在本公开实施例中，所述栅极介电层的材料可以选自二氧化硅、二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆ZrO中的任意一种或更多种。
在本公开实施例中，所述栅极介电层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
在本公开实施例中，所述栅极的材料可以选自ITO或其他低温半导体材料中的任意一种或更多种。
在本公开实施例中，如图1A和图1D所示，所述3D存储器还可以包括一个或多个沿第一方向延伸的存储单元隔离柱500。例如，在第二方向上每间隔两个存储单元列200可以设置有一个所述存储单元隔离柱500。
在本公开实施例中，所述存储单元隔离柱的材料可以为氧化硅，例如，可以选自旋转涂敷(Spin-On Deposition,SOD)氧化硅薄膜、高密度等离子体(High Density Plasma,HDP)氧化硅薄膜和高深宽比工艺(High Aspect Ratio Process，HARP)氧化硅薄膜中的任意一种或更多种。
在本公开实施例中，如图1A所示，所述3D存储器还可以包括内部支撑 层600，所述内部支撑层600设置在沿第一方向相邻的两个半导体层11之间，配置为对所述半导体层11提供支撑。
在本公开实施例中，如图1A所示，所述内部支撑层600还可以位于所述存储单元隔离柱500两侧。当所述存储单元隔离柱500两侧设置有内部支撑层600时可以对所述半导体层11提供牢固的支撑。
在本公开实施例中，所述内部支撑层的材料可以为具有支撑作用的薄膜材料，例如，可以为SiN。
图3A为本公开另一示例性实施例的3D存储器的一个方向的主视剖面结构示意图，图3B为图3A所示的3D存储器的俯视结构示意图。如图3A和图3B所示，在本公开示例性实施例中，所述半导体层、所述位线和所述字线之间的空白空间中可以填充有隔离材料700。
在本公开实施例中，所述隔离材料可以选自SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或更多种。
本公开实施例还提供一种存储器，包括：
多个阵列分布的重复单元，每相邻两个所述重复单元之间通过隔离柱隔离；其中，所述重复单元中包含至少一层存储单元，每层所述重复单元包含位于两个所述隔离柱之间的第一存储单元和第二存储单元；其中，所述两个存储单元包含第一晶体管和第二晶体管；
两个所述隔离柱之间设置有一条或多条横向延伸的半导体柱，所述多条横向延伸的半导体柱沿着垂直衬底的方向间隔分布；
所述半导体柱具有侧壁和两个端部，所述两个端部位于所述隔离柱中使得所述半导体柱由所述隔离柱支撑；
所述半导体柱的侧壁不同区域在横向上间隔分布有第一环形半导体层(例如，本申请实施例提供的3D存储器中的第一半导体层)和第二环形半导体层(例如，本申请实施例提供的3D存储器中的第二半导体层)；分别在所述第一环形半导体层和所述第二环形半导体层上包裹有间隔设置的第一栅极和第二栅极，其中所述第一栅极与所述第一环形半导体层通过绝缘层相绝缘，所述第二栅极与所述第二环形半导体层通过绝缘层相绝缘；
其中，还包括所述半导体柱的侧壁不同区域在横向上间隔分布有第一电容器和第二电容器，所述第一存储单元包含所述第一电容器与所述第一晶体管，所述第二存储单元包含所述第二电容器与所述第二晶体管；
所述第一电容器的第一电容电极和所述第二电容器的第二电容电极分别包裹所述半导体柱的侧壁的不同区域；
其中，所述第一电容器、所述第一晶体管、所述第二晶体管、所述第二电容器横向间隔依次分布。本公开实施例还提供一种存储器的制造方法。如上所述本公开实施例提供的存储器(包括本公开实施例提供的3D存储器)可以通过该制造方法得到。
图4为本公开实施例的存储器的制造方法的工艺流程图。如图4所示，所述制造方法可以包括：
S10：在衬底一侧按照牺牲层和第一初始半导体层的顺序沿第一方向堆叠设置多个由牺牲层和第一初始半导体层组成的外延层；
S20：在所述多个外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱；
S30：去除牺牲层，剩余的第一初始半导体层形成第一半导体层，在所述第一半导体层侧壁设置筒状的第二半导体层，所述第一半导体层和所述第二半导体层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的条状结构的半导体层，所述半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
S40：在所述半导体层的沟道区的第二半导体层侧壁设置环绕所述沟道区的第二半导体层的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S50：在所述半导体层的漏极区的第二半导体层远离所述沟道区一端的侧壁设置环绕所述漏极区的第二半导体层一端的电容器，所述电容器的电极和介电质层均环绕在所述漏极区的第二半导体层的侧壁上；
S60：在沿第一方向排列的多条半导体层的位线区开设贯通所述半导体层的位线槽，在所述位线槽中和沿第一方向排列的多条半导体层的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线。
在本公开实施例中，步骤S20可以包括：
S21：在所述多个外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽；
S22：沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S23：在所述存储单元隔离槽中填充存储单元隔离柱。
在本公开实施例中，步骤S40可以包括：
S41：在所述半导体层的沟道区的第二半导体层侧壁依次设置环绕所述沟道区的第二半导体层的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
任选地，S42：将沿第一方向排列的多条字线在第三方向上的延伸长度设置为不同的，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
任选地，S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
例如，在本公开示例性实施例中，i)步骤S40可以包括：
S41：在所述半导体层的沟道区的第二半导体层侧壁依次设置环绕所述沟道区的第二半导体层的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成 字线；
或者，ii)步骤S40可以包括：
S41：在所述半导体层的沟道区的第二半导体层侧壁依次设置环绕所述沟道区的第二半导体层的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S42：将沿第一方向排列的多条字线在第三方向上的延伸长度设置为不同的，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
或者，iii)步骤S40可以包括：
S41：在所述半导体层的沟道区的第二半导体层侧壁依次设置环绕所述沟道区的第二半导体层的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开；
或者，iiii)步骤S40可以包括：
S41：在所述半导体层的沟道区的第二半导体层侧壁依次设置环绕所述沟道区的第二半导体层的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S42：将沿第一方向排列的多条字线在第三方向上的延伸长度设置为不同的，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
在本公开实施例中，步骤S50可以包括：在所述半导体层的漏极区的第二半导体层远离所述沟道区一端的侧壁依次设置环绕所述漏极区的第二半导体层一端的第一电极板、介电质层和第二电极板，得到环绕所述漏极区的第二半导体层一端的电容器。
在本公开实施例中，所述制造方法还包括：在步骤S60之后，
S70：在所述半导体层、所述位线和所述字线之间的空白空间中填充隔离材料。
图5A至图9B为本公开示例性实施例的存储器的制造方法的中间步骤得到的中间品的主视剖面结构示意图和俯视结构示意图。如图5A至图9B所示，在示例性实施例中，所述存储器的制造方法可以包括：
S10：在衬底100一侧按照牺牲层800和第一初始半导体层114’的顺序沿第一方向堆叠设置多个由牺牲层800和第一初始半导体层114’组成的外延层，得到如图5A和图5B所示的中间品；
S21：在多个所述外延层中定义出存储单元区1’，并沿第一方向刻蚀出存储单元隔离槽500’；
S22：沿第二方向对所述存储单元隔离槽500’与所述牺牲层800对应的部分进行侧边刻蚀，得到内部支撑槽600’，在所述内部支撑槽600’中填充内部支撑层600；
S23：在所述存储单元隔离槽500’中填充存储单元隔离柱500，得到如图6A和图6B所示的中间品；
S30：去除牺牲层800，剩余的第一初始半导体层114’形成第一半导体层114，在所述第一半导体层114侧壁设置筒状的第二半导体层115，所述第一半导体层114和所述第二半导体层115形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的半导体层11，所述半导体层11在第二方向上包括位于两端的源极区111和漏极区113、位于所述源极区111和所述漏极区113之间的沟道区112，得到如图7A和图7B所示的中间品；
S41：在所述半导体层11的沟道区112的第二半导体层115侧壁依次设置环绕所述沟道区112的第二半导体层115的栅极介电层(图中未示)和栅极12，得到多个由所述半导体层11和所述栅极12形成的晶体管10；以及，在第三方向上排列的半导体层11有一条，使这一条半导体层11上的栅极12作为字线400；或者，在第三方向上排列的半导体层11有多条，使在第三方向上排列的多条半导体层11上的栅极12在第三方向上连接在一起形成字线400；
S42：将沿第一方向排列的多条字线400在第三方向上的延伸长度设置为不同的，使得沿第一方向排列的位于不同层的多条字线400呈现出阶梯状；
S43：在沿第一方向上相邻的两个半导体层11之间设置层间隔离层2，从而将沿第一方向上相邻的两条半导体层11上的栅极12隔离开，得到如图8A和图8B所示的中间品；
S50：在所述半导体层11的漏极区113的第二半导体层115远离所述沟道区112一端的侧壁依次设置环绕所述漏极区113的第二半导体层115一端的第一电极板21、介电质层23和第二电极板22，得到环绕所述漏极区113的第二半导体层115一端的电容器20，得到如图9A和图9B所示的中间品；
S60：在沿第一方向排列的多条半导体层11的位线区开设贯通所述半导体层11的位线槽300’，在所述位线槽300’中和沿第一方向排列的多条半导体层11的位线槽之间填充位线材料，形成沿第一方向延伸的位线300，将所述位线300和与该位线300相接触的多条半导体层11的所述源极区111连接，使得所述多条半导体层11的所述源极区111共用该一条位线300，得到如图1A至图1D所示的3D存储器；
S70：在所述半导体层11、所述位线300和所述字线400之间的空白空间中填充隔离材料700，得到如图3A和图3B所示的3D存储器。
在本公开实施例中，所述牺牲层的材料可以为SiGe等具有相似性质的其他导电材料中的任意一种或更多种。所述牺牲层的厚度可以为30nm至50nm，例如，可以为30nm、35nm、40nm、45nm、50nm。
在本公开实施例中，步骤S10中可以通过外延设备在所述衬底上生长出牺牲层/第一初始半导体层的超晶格(super lattice)薄膜堆叠层，得到多个由牺 牲层和第一初始半导体层组成的外延层。
在本公开实施例中，步骤S21中可以利用同一层图案光罩(Photo mask)通过光照曝光进行图案化刻蚀，形成沿第三方向排列并沿第二方向延伸的沟槽从而将多个牺牲层/第一初始半导体层在第三方向上形成隔离，得到存储单元区。
在本公开实施例中，步骤S21中可以通过反应离子刻蚀(Reactive-Ion Etch,RIE)得到存储单元隔离槽。
在本公开实施例中，步骤S22中，可以通过湿法刻蚀对所述存储单元隔离槽的与所述牺牲层对应的部分进行侧边刻蚀。
在本公开实施例中，步骤S22中，可以通过原子层沉积(Atomic layer deposition,ALD)工艺或化学气相沉积(Chemical Vapor Deposition,CVD)工在所述内部支撑层槽中填充内部支撑层，例如，可以通过ALD工艺在所述内部支撑层槽中填充SiN，形成内部支撑层。
在本公开实施例中，步骤S23中可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充存储单元隔离柱，例如，可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充氧化硅薄膜从而形成存储单元隔离柱。
在本公开实施例中，步骤S30中可以通过刻蚀法、选择超高牺牲层/第一初始半导体层刻蚀比将牺牲层刻蚀掉而保留第一初始半导体层，所述刻蚀法可以为干法刻蚀或湿法刻蚀。
在本公开实施例中，步骤S30中可以通过ALD工艺在所述第一半导体层侧壁设置筒状的第二半导体层。
在本公开实施例中，步骤S42中可以通过修整刻蚀(trim etch)得到阶梯状字线(staircase WL)。
在本公开实施例中，步骤S43中可以通过ALD或化学气相沉积(Chemical Vapor Deposition,CVD)工艺设置层间隔离层，例如，可以通过ALD或CVD工艺填充SiO 2，形成层间隔离层。
在本公开实施例中，步骤S70中可以通过SOD、HDP或HARP工艺在 空白空间中填充隔离材料，例如，可以通过SOD、HDP或HARP工艺在空白空间中形成SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或更多种。
本公开实施例还提供了一种动态随机存取存储器(DRAM)，包括如上本申请实施例提供所述的3D存储器，或者，包括如上本申请实施例提供所述的存储器。
本公开实施例还提供了一种电子设备，包括如上所述的动态随机存取存储器。
在本公开实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
在本公开中的描述中，需要说明的是，术语“上”、“下”、“一侧”、“另一侧”、“一端”、“另一端”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的结构具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，除非另有明确的规定和限定，术语“连接”、“设置”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；术语“连接”、“设置”可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种3D存储器，包括：
    衬底；
    多个在垂直于所述衬底的第一方向上分布的存储单元列，每个所述存储单元列均包括沿所述第一方向堆叠设置的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列；所述第二方向和第三方向交叉且构成的平面与所述衬底的主平面平行；
    所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述半导体层包括第一半导体层和设置在所述第一半导体层的侧壁的筒状的第二半导体层，所述栅极环绕在所述沟道区的第二半导体层的侧壁；所述电容器的电极和介电质层环绕在所述漏极区的第二半导体层的侧壁。
  2. 根据权利要求1所述的3D存储器，还包括：多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区均与一条共用的位线连接。
  3. 根据权利要求1所述的3D存储器，还包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述衬底在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极连接形成。
  4. 根据权利要求3所述的3D存储器，其中，沿第一方向间隔排列的多条字线的长度不同，形成阶梯状。
  5. 根据权利要求4所述的3D存储器，其中，所述字线的材料包含铟和锡至少之一。
  6. 根据权利要求1所述的3D存储器，其中，所述第一半导体层的材料选自第IVA族半导体材料中的任意一种或更多种。
  7. 根据权利要求6所述的3D存储器，其中，所述第一半导体层的材料为单晶硅。
  8. 根据权利要求7所述的3D存储器，其中，
    所述第二半导体层的材料为金属氧化物半导体材料，所述金属氧化物中的金属包含铟、锌、钨、锡、钛、锆、铪、镓中的至少之一。
  9. 根据权利要求1至8中任一项所述的3D存储器，其中，所述存储单元列还包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
  10. 根据权利要求1至9中任一项所述的3D存储器，还包括一个或多个沿第一方向延伸的存储单元隔离柱，在第二方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
  11. 根据权利要求10所述的3D存储器，其中，
    所述存储单元隔离柱的材料为氧化硅。
  12. 根据权利要求10所述的3D存储器，还包括内部支撑层，所述内部支撑层设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
  13. 根据权利要求12所述的3D存储器，其中，
    所述内部支撑层位于所述存储单元隔离柱的侧壁上。
  14. 根据权利要求13所述的3D存储器，其中，
    所述内部支撑层的材料为氮化硅。
  15. 一种存储器，包括：
    多个阵列分布的重复单元，每相邻两个所述重复单元之间通过隔离柱隔离；其中，所述重复单元中包含至少一层存储单元，每层所述重复单元包含位于两个所述隔离柱之间的第一存储单元和第二存储单元；其中，所述两个存储单元包含第一晶体管和第二晶体管；
    两个所述隔离柱之间设置有一条或多条横向延伸的半导体柱，所述多条 横向延伸的半导体柱沿着垂直衬底的方向间隔分布；
    所述半导体柱具有侧壁和两个端部，所述两个端部位于所述隔离柱中使得所述半导体柱由所述隔离柱支撑；
    所述半导体柱的侧壁不同区域在横向上间隔分布有第一环形半导体层和第二环形半导体层；分别在所述第一环形半导体层和所述第二环形半导体层上包裹有间隔设置的第一栅极和第二栅极，其中所述第一栅极与所述第一环形半导体层通过绝缘层相绝缘，所述第二栅极与所述第二环形半导体层通过绝缘层相绝缘；
    其中，还包括所述半导体柱的侧壁不同区域在横向上间隔分布有第一电容器和第二电容器，所述第一存储单元包含所述第一电容器与所述第一晶体管，所述第二存储单元包含所述第二电容器与所述第二晶体管；
    所述第一电容器的第一电容电极和所述第二电容器的第二电容电极分别包裹所述半导体柱的侧壁的不同区域；
    其中，所述第一电容器、所述第一晶体管、所述第二晶体管、所述第二电容器横向间隔依次分布。
  16. 一种动态随机存取存储器，包括根据权利要求1至14中任一项所述的3D存储器，或者，包括根据权利要求15所述的存储器。
  17. 一种电子设备，包括根据权利要求16所述的动态随机存取存储器。
  18. 根据权利要求17所述的电子设备，包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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