WO2024077768A1 - 存储器及其制造方法 - Google Patents

存储器及其制造方法 Download PDF

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Publication number
WO2024077768A1
WO2024077768A1 PCT/CN2022/140175 CN2022140175W WO2024077768A1 WO 2024077768 A1 WO2024077768 A1 WO 2024077768A1 CN 2022140175 W CN2022140175 W CN 2022140175W WO 2024077768 A1 WO2024077768 A1 WO 2024077768A1
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silicon
layer
substrate
groove
conductive
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PCT/CN2022/140175
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English (en)
French (fr)
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田超
平延磊
周俊
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北京超弦存储器研究院
长鑫科技集团股份有限公司
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Publication of WO2024077768A1 publication Critical patent/WO2024077768A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components

Definitions

  • the present application relates to but is not limited to the field of semiconductor devices, and in particular to a memory and a method for manufacturing the same.
  • DRAM Dynamic Random Access Memory
  • VGAAFET vertical gate-all-around field effect transistors
  • An embodiment of the present application provides a memory, the memory comprising a plurality of transistors, and further comprising:
  • a plurality of silicon pillars corresponding to the plurality of transistors one by one, the silicon pillars being located on the substrate; wherein the plurality of silicon pillars are arranged in a row direction and a column direction, and a groove is provided between two adjacent columns of silicon pillars; a plurality of grooves are provided between two adjacent columns of grooves, and each of the grooves is located in the substrate between two adjacent silicon pillars in the column direction and extends in the substrate toward a region below the two adjacent silicon pillars in the column direction;
  • bit lines extending along the column direction and arranged at intervals in the row direction, each of the bit lines being located in a row of the grooves and connected to the bottom end of the silicon pillar; the bit lines being metal lines;
  • isolation layers are located between the bit lines and the inner wall of the groove, and the isolation layers are in contact with at least a portion of the substrate;
  • the substrate is a single crystal silicon substrate
  • the plurality of silicon pillars are single crystal silicon pillars
  • the isolation layer is an amorphous silicon film layer or a polycrystalline silicon film layer.
  • one isolation layer may be distributed on the inner side wall of each of the grooves.
  • each of the isolation layers may extend between each column of the silicon pillars and the substrate.
  • a hole may be provided between two adjacent silicon pillars along the column direction, each of the grooves is located in the substrate below one of the holes, and a plurality of the grooves below each column of the holes are interconnected in the column direction.
  • the metal line of the bit line may be formed of a first conductive layer, and the first conductive layer is disposed on an inner wall of the groove.
  • the metal line of the bit line may be formed by a first conductive layer and a second conductive layer, the first conductive layer being disposed on the inner wall of the groove and between the second conductive layer and the isolation layer.
  • the material of the first conductive layer may be a silicide of a conductive first conductive metal
  • the material of the second conductive layer may be a second conductive metal.
  • the first conductive metal may be selected from any one or more of titanium, cobalt and nickel.
  • the second conductive metal may be selected from any one or more of tungsten, copper and aluminum.
  • the memory may further include a first barrier layer; wherein,
  • the first barrier layer may be disposed on a surface of a top end and a surface of a side wall of the silicon pillar.
  • the memory may further include a conductive second barrier layer; wherein,
  • the second barrier layer may be disposed between the first conductive layer and the second conductive layer.
  • the present application also provides a method for manufacturing a memory, the method comprising:
  • a metal line is deposited in the groove to form a bit line, each of the bit lines extends along a column direction and contacts the isolation layer, and each of the bit lines is connected to the bottom end of a corresponding column of silicon pillars.
  • the silicon substrate may be a single crystal silicon substrate.
  • depositing an isolation layer formed of a polysilicon film layer or an amorphous silicon film layer in the groove so that the isolation layer contacts at least a portion of the silicon substrate may include:
  • a polysilicon film layer or an amorphous silicon film layer is deposited in the groove, a groove having a polysilicon film layer or an amorphous silicon film layer on the surface is formed by patterning, an isolation layer is formed through the patterned polysilicon film layer or the amorphous silicon film layer, and the isolation layer is in contact with at least a part of the silicon substrate, and
  • the inner side wall of each groove is provided with an isolation layer.
  • depositing an isolation layer formed of a polysilicon film layer or an amorphous silicon film layer in the groove so that the isolation layer contacts at least a portion of the silicon substrate may further include:
  • Each of the isolation layers is extended to below the silicon pillars arranged along a column direction, and the isolation layers below each column of the silicon pillars are connected together.
  • providing a silicon substrate, and etching on the silicon substrate to form a plurality of silicon pillars extending in a direction perpendicular to the silicon substrate may include:
  • the silicon wall is etched along a direction perpendicular to the silicon substrate to form a plurality of mutually spaced holes on each of the silicon walls.
  • the plurality of holes separate the silicon wall into a plurality of silicon pillars.
  • Each of the silicon pillars includes a source region, a channel region and a drain region in sequence.
  • forming a groove extending to below the two silicon pillars adjacent to each other in the column direction in the silicon substrate between the two silicon pillars adjacent to each other in the column direction, and making a plurality of the grooves below the silicon pillars in each column interconnected in the column direction may include:
  • the exposed silicon substrate is etched to form a groove extending downward into the silicon substrate and extending to under two adjacent silicon pillars along the column direction under each hole, and multiple grooves under each column of holes are interconnected in the column direction.
  • depositing a metal line in the groove to form a bit line may include:
  • a first conductive metal is deposited on the inner wall of the groove, and the first conductive metal is reacted with the polysilicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer formed by the silicide of the first conductive metal on the inner wall of the groove, the first conductive layer constitutes the metal line, the metal line forms the bit line, and the polysilicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer.
  • depositing a metal line in the groove to form a bit line may include:
  • a first conductive metal is deposited on the inner wall of the groove, and the first conductive metal is reacted with the polysilicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer formed by the silicide of the first conductive metal on the inner wall of the groove, and the polysilicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer; and a conductive second barrier layer is deposited on the surface of the first conductive layer, and the second conductive metal is filled in the remaining part of the groove to form a second conductive layer, the first conductive layer and the second conductive layer constitute the metal line, and the metal line forms the bit line.
  • FIG1 is a schematic diagram of a top view of a memory according to an exemplary embodiment of the present application.
  • FIG2A is a schematic diagram of a longitudinal cross-sectional structure of the memory device shown in FIG1 on the cross section a-a′;
  • FIG2B is a schematic diagram of a longitudinal cross-sectional structure of the memory device shown in FIG1 on the b-b cross section;
  • FIG3A is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of the method for manufacturing a memory according to an exemplary embodiment of the present application, on the b-b' cross section;
  • FIG3B is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of the method for manufacturing a memory according to an exemplary embodiment of the present application, on the a-a′ cross section;
  • FIG3C is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of the method for manufacturing a memory according to an exemplary embodiment of the present application, on the a-a′ cross section;
  • FIG3D is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of the method for manufacturing a memory according to an exemplary embodiment of the present application, taken along the a-a′ cross section;
  • Figure 3E is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of the method for manufacturing the memory of the exemplary embodiment of the present application on the a-a’ cross section.
  • 10-silicon pillar 10'-silicon wall; 11-source region; 12-channel region; 13-drain region; 20-bit line; 21-first conductive layer; 22-second conductive layer; 30-isolation layer; 31-first blocking layer; 32-second blocking layer; 40-substrate; 50-hole; 50'-recess; 60-groove; 70-word line; 80-dielectric layer.
  • the terms “disposed” and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • the specific meanings of the above terms in this application can be understood according to specific circumstances.
  • An embodiment of the present application provides a memory, the memory comprising a plurality of transistors, and further comprising:
  • a plurality of silicon pillars corresponding to the plurality of transistors one by one, the silicon pillars being located on the substrate; wherein the plurality of silicon pillars are arranged in a row direction and a column direction, and a groove is provided between two adjacent columns of silicon pillars; a plurality of grooves are provided between two adjacent columns of grooves, and each of the grooves is located in the substrate between two adjacent silicon pillars in the column direction and extends in the substrate toward a region below the two adjacent silicon pillars in the column direction;
  • bit lines extending along the column direction and arranged at intervals in the row direction, each of the bit lines being located in a column of the grooves and connected to the bottom end of the silicon pillar; the bit lines being metal lines;
  • isolation layers are located between the bit lines and the inner wall of the groove, and the isolation layers are in contact with at least a portion of the substrate;
  • the substrate is a single crystal silicon substrate
  • the plurality of silicon pillars are single crystal silicon pillars
  • the isolation layer is an amorphous silicon film layer or a polycrystalline silicon film layer.
  • metal is used in multiple grooves formed in the single crystal silicon substrate and the single crystal silicon in the substrate is annealed at high temperature to form metal silicide, and the metal silicide in the multiple grooves is connected together by "point to point” and other methods to form a bit line.
  • metal silicide due to the regular arrangement of the crystal directions inside the single crystal silicon, it is easy to have a channel effect in a certain crystal direction during the formation of the metal silicide. That is to say, during annealing or subsequent high temperature processes, the metal silicide will have irregular diffusion along the crystal phase (also called thermal stability problem), resulting in irregular agglomeration of the metal silicide, which affects the performance of the memory.
  • the memory of the embodiment of the present application introduces an isolation layer between the metal bit line and the single crystal silicon substrate, and the material of the isolation layer is selected from polycrystalline silicon or amorphous silicon. Since there is no regular crystal phase arrangement inside polycrystalline silicon and amorphous silicon, when the metal reacts with the silicon in polycrystalline silicon or amorphous silicon to form metal silicide to realize the interconnection of the bit lines, the problem of irregular diffusion of the metal silicide along the crystal phase will not occur, and the problem of metal silicide agglomeration that is easy to occur when the metal bit line is formed in the single crystal silicon substrate can be avoided, thereby improving the thermal stability of the memory.
  • a hole may be provided between two adjacent silicon pillars along the column direction, each of the grooves is located in the substrate below one of the holes, and a plurality of the grooves below each column of the holes are interconnected in the column direction.
  • Figure 1 is a schematic diagram of the top view structure of the memory of the exemplary embodiment of the present application
  • Figure 2A is a schematic diagram of the longitudinal cross-sectional structure of the memory shown in Figure 1 on the a-a’ section
  • Figure 2B is a schematic diagram of the longitudinal cross-sectional structure of the memory shown in Figure 1 on the b-b’ section.
  • the memory includes a plurality of transistors, and may further include: a plurality of silicon pillars 10 , a plurality of bit lines 20 , a plurality of isolation layers 30 and a substrate 40 ;
  • the substrate 40 is a single crystal silicon substrate
  • the plurality of silicon pillars 10 correspond to the plurality of transistors one by one, for example, each of the transistors may include one silicon pillar 10; the plurality of silicon pillars 10 are all disposed on the substrate 40 and are single crystal silicon pillars; the plurality of silicon pillars 10 are arranged in a row direction (i.e., the b-b' direction shown in FIG. 1 ) and a column direction (i.e., the a-a' direction shown in FIG.
  • a hole 50 is provided between two adjacent silicon pillars 10 in the column direction
  • a groove 60 is provided between two adjacent columns of silicon pillars 10
  • a plurality of grooves 50' are provided between two adjacent columns of grooves 60, each groove 50' is located in the substrate 40 between two adjacent silicon pillars 10 in the column direction, that is, each groove 50' is located in the substrate 40 below a hole 50, and extends toward the region below the two adjacent silicon pillars 10 in the column direction, and the plurality of grooves 50' below each column of holes 50 may be interconnected in the column direction;
  • a plurality of bit lines 20 are arranged at intervals in the row direction; each bit line 20 extends in the column direction and is located in a column of holes 50 extending into the substrate 40 and connected to the bottom end of the silicon pillar 10; the bit line 20 is a metal line, and the metal line can be formed of a material containing a metal element, for example, the metal line can be formed of a metal or a silicide of a metal; for example, the hole 50 extends to the bit line 20 in a direction perpendicular to the substrate 40 and exposes the bit line 20;
  • the isolation layer 30 is located between the bit line 20 and the inner wall of the groove 50'.
  • the isolation layer 30 contacts at least a portion of the substrate 40.
  • the isolation layer 30 is a polysilicon film layer or an amorphous silicon film layer.
  • an isolation layer 30 may be distributed on the inner sidewall of each groove 50'.
  • bit line 20 and the substrate 40 may not be in contact with each other at all.
  • each isolation layer 30 may extend to a region between each column of silicon pillars 10 and the substrate.
  • the bit line 20 may be formed by a plurality of bit line units connected to each other in a column direction;
  • Each bit line unit is disposed in a groove 50'.
  • the plurality of grooves 50' below each column of holes 50 are interconnected in the column direction, so that the plurality of bit line units in the plurality of grooves 50' below each column of holes 50 can be connected together in the column direction to form a bit line 20.
  • the metal line of the bit line may be formed of a first conductive layer, and the first conductive layer is disposed on an inner wall of the groove.
  • the metal line of the bit line 20 may be formed by a first conductive layer 21 and a second conductive layer 22 , wherein the first conductive layer 21 is disposed on the inner wall of the groove and between the second conductive layer 22 and the isolation layer 30 .
  • the material of the first conductive layer may be a silicide of a conductive first conductive metal
  • the material of the second conductive layer may be a second conductive metal
  • the first conductive metal may be selected from any one or more of titanium, cobalt and nickel.
  • the second conductive metal may be selected from any one or more of tungsten, copper and aluminum.
  • the first conductive layer or the second conductive layer may be a multi-layer structure formed of the plurality of materials, respectively.
  • the memory may further include a first barrier layer 31 , and the first barrier layer 31 may be disposed on the surface of the top end and the surface of the side wall of the silicon pillar 10 .
  • the memory may further include a conductive second barrier layer 32 , where the second barrier layer 32 is disposed between the first conductive layer 21 and the second conductive layer 22 .
  • the silicon pillar may include a source region 11 , a channel region 12 , and a drain region 13 in sequence, and the source region or the drain region is in contact with and connected to the bit line.
  • the source region, the channel region, and the drain region may be located on the sidewalls of the silicon pillar; illustratively, the source region, the channel region, and the drain region may extend from the sidewalls of the silicon pillar to the interior of the silicon pillar and penetrate the surfaces on opposite sides of the sidewalls of the silicon pillar.
  • the memory may further include a gate (not shown in the figure), which is arranged on the side wall of the silicon pillar and surrounds the channel region of the side wall, a gate insulation layer is arranged between the gate and the channel region, and the gate is connected to the word line.
  • a gate (not shown in the figure), which is arranged on the side wall of the silicon pillar and surrounds the channel region of the side wall, a gate insulation layer is arranged between the gate and the channel region, and the gate is connected to the word line.
  • a transistor of the memory may include a silicon pillar, a gate insulating layer disposed on a sidewall of the silicon pillar, and a gate.
  • the gates on one side of a row of silicon pillars 10 may be connected together to form a word line 70 extending along the row direction, thereby achieving connection between the gates and the word line 70 .
  • the hole may be perpendicular to the substrate, and the groove may be perpendicular to the substrate.
  • the etching selectivity of the substrate and the first barrier layer is relatively high.
  • the first barrier layer can be used to protect the side wall of the silicon column to prevent the silicon column from being etched away.
  • the etching selectivity ratio between the substrate and the first barrier layer may be ⁇ 20; for another example, the material of the substrate is single crystal silicon, and the material of the first barrier layer may be selected from any one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride.
  • the first barrier layer may be a multilayer structure formed by the multiple materials respectively.
  • the empty space of the memory for example, the empty space between the silicon pillars 10, can be filled with a dielectric layer.
  • the material of the dielectric layer can be selected from any one or more of silicon oxide, silicon nitride, silicon carbonitride oxide and silicon carbonitride.
  • the material of the second barrier layer can be selected from any one or more of titanium nitride (TiN) and tantalum nitride (TaN).
  • TiN titanium nitride
  • TaN tantalum nitride
  • the second barrier layer can be a multilayer structure formed by the multiple materials.
  • the second conductive layer When depositing the second conductive layer, generally, the second conductive layer is first deposited in the hole above the groove and in the groove, and then the second conductive layer in the hole above the groove is removed by etching back, leaving only the second conductive layer in the groove.
  • the second barrier layer can protect the silicon pillar from being etched away when etching the redundant second conductive layer in the hole.
  • the height of the silicon pillar in a direction perpendicular to the substrate can be set according to actual electrical requirements, for example, it can be 10nm to 50nm.
  • the gate may be made of titanium nitride (TiN), aluminum, or an aluminum alloy; or,
  • the material of the gate may be selected from any one or more of the conductor materials formed by the IVA group elements.
  • the material of the gate may be selected from any one or more of polysilicon, polysilicon germanium, and the like.
  • the material of the gate insulating layer may be selected from any one or more of silicon oxide (e.g., SiO 2 ), hafnium oxide (e.g., HfO 2 ), zirconium oxide (e.g., ZrO) and aluminum oxide (e.g., Al 2 O 3 ).
  • the gate insulating layer may be a single-layer structure or a multi-layer structure, for example, it may include a two-layer structure formed by silicon oxide and hafnium oxide, wherein the silicon oxide layer is in contact with the channel region, and the hafnium oxide layer is in contact with the gate.
  • the thickness of the gate insulating layer may be set according to actual electrical requirements, for example, it may be 2 nm to 5 nm.
  • the transistor of the memory may be a vertical gate-all-around (VGAA) transistor; the memory may also be a storage device comprising a transistor, such as a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), etc.
  • VGAA vertical gate-all-around
  • DRAM dynamic random access memory
  • MRAM magnetic random access memory
  • the present application also provides a method for manufacturing a memory, the method comprising:
  • a metal line is deposited in the groove to form a bit line, each of the bit lines extends along a column direction and contacts the isolation layer, and each of the bit lines is connected to the bottom end of a corresponding column of silicon pillars.
  • providing a silicon substrate, and etching on the silicon substrate to form a plurality of silicon pillars extending in a direction perpendicular to the silicon substrate may include:
  • the silicon wall is etched along a direction perpendicular to the silicon substrate to form a plurality of mutually spaced holes on each of the silicon walls.
  • the plurality of holes separate the silicon wall into a plurality of silicon pillars.
  • Each of the silicon pillars includes a source region, a channel region and a drain region in sequence.
  • forming a groove extending to below the two silicon pillars adjacent to each other in the column direction in the silicon substrate between the two silicon pillars adjacent to each other in the column direction, and making a plurality of the grooves below the silicon pillars in each column interconnected in the column direction may include:
  • the exposed silicon substrate is etched to form a groove extending downward into the silicon substrate and extending to under two adjacent silicon pillars along the column direction under each hole, and multiple grooves under each column of holes are interconnected in the column direction.
  • the manufacturing method may include:
  • a metal line is deposited in the groove to form a bit line, each of the bit lines extends along a column direction and contacts the isolation layer, and each of the bit lines is connected to the bottom end of a corresponding column of silicon pillars.
  • the silicon substrate may be a single crystal silicon substrate.
  • depositing an isolation layer formed of a polysilicon film layer or an amorphous silicon film layer in the groove so that the isolation layer contacts at least a portion of the silicon substrate may include:
  • a polysilicon film layer or an amorphous silicon film layer is deposited in the groove, a groove having a polysilicon film layer or an amorphous silicon film layer on the surface is formed by patterning, an isolation layer is formed through the patterned polysilicon film layer or the amorphous silicon film layer, and the isolation layer is in contact with at least a part of the silicon substrate, and
  • the inner side wall of each groove is provided with an isolation layer.
  • depositing an isolation layer formed of a polysilicon film layer or an amorphous silicon film layer in the groove so that the isolation layer contacts at least a portion of the silicon substrate may further include:
  • Each of the isolation layers is extended to below the silicon pillars arranged along a column direction, and the isolation layers below each column of the silicon pillars are connected together.
  • depositing a metal line in the groove to form a bit line may include:
  • a first conductive metal is deposited on the inner wall of the groove, and the first conductive metal is reacted with the polysilicon film layer or the amorphous silicon film layer in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer formed by the silicide of the first conductive metal on the inner wall of the groove, the first conductive layer constitutes the metal line, the metal line forms the bit line, and the polysilicon film layer or the amorphous silicon film layer that is not reacted by the first conductive metal forms the isolation layer.
  • depositing a metal line in the groove to form a bit line may include:
  • a conductive second barrier layer is deposited on the surface of the first conductive layer, and a second conductive metal is filled in the remaining portion of the groove to form a second conductive layer.
  • the first conductive layer and the second conductive layer constitute the metal line, and the metal line forms the bit line.
  • allowing the first conductive metal to react with the polycrystalline silicon or amorphous silicon in the isolation layer to form a conductive first conductive metal silicide may include: through an annealing process, allowing the first conductive metal to react with the polycrystalline silicon or amorphous silicon in the isolation layer to form a conductive first conductive metal silicide.
  • the method for manufacturing the memory may further include: after forming the silicide of the first conductive metal and before depositing a conductive second barrier layer on the surface of the first conductive layer, using wet etching to remove the first conductive metal that has not reacted with polycrystalline silicon or amorphous silicon.
  • the first conductive metal is titanium (Ti), and the reagent used for the wet etching can be selected from sulfuric acid or a mixed solution of sulfuric acid and hydrogen peroxide; in the mixed solution of sulfuric acid and hydrogen peroxide, the volume ratio of sulfuric acid to hydrogen peroxide is 2:1 to 10:1, with the mass fraction of sulfuric acid being approximately 98% and the mass fraction of hydrogen peroxide being approximately 30%;
  • the temperature of the wet etching can be 80°C to 170°C, for example, it can be 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C or 170°C;
  • the etching rate of titanium can be 5nm/min to 20nm/min, for example, it can be 5nm/min, 6nm/min, 8nm/min, 10nm/min, 12nm/min, 14nm/min, 16nm/min, 18nm/min or 20n
  • the wet etching temperature is 80° C. to 170° C. and the titanium etching rate is 5 nm/min to 20 nm/min, titanium that has not reacted with silicon can be better removed without corroding titanium silicide.
  • the manufacturing method of the memory may further include: while removing part of the isolation layer in the groove by patterning and retaining the isolation layer on the inner wall of the groove, trimming the isolation layer in the groove so that the isolation layer retained on the inner wall of the groove has a desired shape, for example, it may be a bowl shape, an elliptical shape, a "sigma ( ⁇ ) shape", a diamond shape, etc.
  • the silicon substrate may be a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, such as a silicon on sapphire (SOS) substrate, a silicon on glass (SOG) substrate, an epitaxial layer of silicon on a base semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1 -xGex , where x may be a molar fraction between 0.2 and 0.8, for example), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).
  • SOI semiconductor on insulator
  • Si1 -xGex silicon-germanium
  • germanium Ge
  • GaAs gallium arsenide
  • GaN gallium nitride
  • InP indium phosphide
  • the substrate may be doped or undoped.
  • FIG3A is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of a memory manufacturing method of an exemplary embodiment of the present application on the b-b' cross section
  • FIG3B to FIG3E are schematic diagrams of the longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of a memory manufacturing method of an exemplary embodiment of the present application on the a-a' cross section.
  • the memory manufacturing method may include:
  • S10 providing a substrate 40 (a silicon substrate is used in this embodiment), etching a plurality of grooves 60 on the substrate 40, each groove 60 extending in the column direction, the plurality of grooves 60 partitioning the upper portion of the substrate 40 into a plurality of silicon walls 10' spaced apart in the row direction and extending in the column direction, and filling the grooves 60 with a dielectric layer 80 to obtain an intermediate product as shown in FIG. 3A ;
  • the silicon wall 10' is etched along a direction perpendicular to the substrate 40, so that a plurality of mutually spaced holes 50 are formed on each of the silicon walls 10', and the plurality of holes 50 formed on one of the silicon walls 10' space the silicon wall 10' into a plurality of silicon pillars 10 spaced apart along a column direction, a first barrier layer 31 is deposited on the sidewall surface and the top surface of the silicon pillar 10, and the substrate 40 between two adjacent silicon pillars 10 along the column direction is exposed, to obtain an intermediate product as shown in FIG. 3B ;
  • S50 depositing a first conductive metal on the inner wall of the groove 50', and reacting the first conductive metal with the polysilicon or amorphous silicon in the isolation layer to form a conductive silicide of the first conductive metal through an annealing process, thereby forming a first conductive layer 21 formed of the silicide of the first conductive metal on the inner wall of the groove; removing the first conductive metal that has not reacted with the polysilicon or amorphous silicon by wet etching; the first conductive layer and the substrate 40 are separated by the isolation layer that has not been reacted by the first conductive metal, and an intermediate product as shown in FIG. 3E is obtained; and
  • a conductive second barrier layer is deposited on the surface of the first conductive layer, and a second conductive metal is filled in the remaining part of the groove 50' to form a second conductive layer.
  • the first conductive layer and the second conductive layer constitute the metal line, and the metal lines in two adjacent grooves along the column direction are connected to form a bit line, thereby obtaining a memory as shown in Figures 2A and 2B.
  • the manufacturing method may further include sequentially forming a gate insulating layer and a gate on the sidewall of the silicon pillar.
  • a gate insulating layer and a gate may be sequentially formed on the sidewall of the channel region of the silicon pillar.
  • the memory as described above in the embodiment of the present application can be obtained by the memory manufacturing method provided in the embodiment of the present application as described above.
  • the methods for forming the hole and the groove can be independently selected from any one or more of dry etching and wet etching.
  • the recess may be formed by etching the lower portion of the first trench sideways using any one or more of dry etching and wet etching.
  • the methods of depositing the first barrier layer, the isolation layer, the second barrier layer and the dielectric layer can be independently selected from any one of atomic layer deposition (ALD) and chemical vapor deposition (CVD).
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.
  • the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

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  • Non-Volatile Memory (AREA)

Abstract

一种存储器及其制造方法，存储器包括多个晶体管，还包括：衬底(40)；多个硅柱(10)，与多个晶体管一一对应，硅柱(10)位于衬底(40)上，多个硅柱(10)沿行方向和列方向间隔排列，相邻两列硅柱(10)之间具有沟槽(60)，相邻两列沟槽(60)之间具有多个凹槽(50')，每个凹槽(50')均位于沿列方向相邻的两个硅柱(10)之间的衬底(40)中并在衬底(40)中朝向该两个沿列方向相邻的硅柱(10)下方的区域延伸；多条位线(20)，沿着列方向延伸且在行方向间隔排列，每条位线(20)位于一列凹槽(50')中并与硅柱(10)的底端连接，位线(20)为金属线；隔离层(30)，位于位线(20)与凹槽(50')内壁之间，与衬底(40)至少部分区域接触；衬底(40)为单晶硅衬底，硅柱(10)为单晶硅硅柱，隔离层(30)为非晶硅或多晶硅膜层。

Description

存储器及其制造方法
本申请要求于2022年10月10日提交中国专利局、申请号为2022112357739、发明名称为“存储器及其制造方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请涉及但不限于半导体器件领域，尤指一种存储器及其制造方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，广泛应用在个人电脑、笔记本和消费电子产品中。DRAM将数据存储在具有电容器和阵列晶体管的存储单元中。DRAM的晶体管可以采用垂直环栅场效应晶体管(Vertical Gate-All-Around Field Effect Transistor,VGAAFET)。垂直环栅场效应晶体管的沟道完全被栅极环绕，而且在3D集成和布线上有明显优势，因此具有较大增加集成度的潜力。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本申请的保护范围。
本申请实施例提供了一种存储器，所述存储器包括多个晶体管，还包括：
衬底；
多个硅柱，与所述多个晶体管一一对应，所述硅柱位于所述衬底上；其中，多个所述硅柱沿行方向和列方向间隔排列，相邻两列硅柱之间具有沟槽；相邻两列沟槽之间具有多个凹槽，每个所述凹槽均位于沿列方向相邻的两个所述硅柱之间的所述衬底中并在所述衬底中朝向该两个沿列方向相邻的硅柱下方的区域延伸；
多条位线，沿着列方向延伸且在行方向间隔排列，每条所述位线位于一 列所述凹槽中并与所述硅柱的底端连接；所述位线为金属线；
多个隔离层，所述隔离层位于所述位线与所述凹槽的内壁之间，所述隔离层与所述衬底的至少部分区域接触；
所述衬底为单晶硅衬底，所述多个硅柱为单晶硅硅柱，所述隔离层为非晶硅膜层或多晶硅膜层。
在本申请的实施例中，每个所述凹槽的内侧壁可以均分布有一个所述隔离层。
在本申请的实施例中，每个所述隔离层可以延伸至每列所述硅柱与所述衬底之间。
在本申请的实施例中，沿列方向相邻的两个所述硅柱之间可以具有孔，每个所述凹槽均位于一个所述孔下方的所述衬底中，并且每列所述孔下方的多个所述凹槽在列方向上相互连通。
在本申请的实施例中，所述位线的金属线可以由第一导电层形成，所述第一导电层设置在所述凹槽的内壁上。
在本申请的实施例中，所述位线的金属线可以由第一导电层和第二导电层形成，所述第一导电层设置在所述凹槽的内壁上并且位于所述第二导电层与所述隔离层之间。在本申请的实施例中，所述第一导电层的材料可以为导电的第一导电金属的硅化物，所述第二导电层的材料可以为第二导电金属。
在本申请的实施例中，所述第一导电金属可以选自钛、钴和镍中的任意一种或多种。
在本申请的实施例中，所述第二导电金属可以选自钨、铜和铝中的任意一种或多种。
在本申请的实施例中，所述存储器还可以包括第一阻挡层；其中，
所述第一阻挡层可以设置在所述硅柱的顶端的表面和侧壁的表面。
在本申请的实施例中，所述存储器还可以包括导电的第二阻挡层；其中，
所述第二阻挡层可以设置在所述第一导电层与所述第二导电层之间。
本申请实施例还提供一种存储器的制造方法，所述存储器的制造方法包 括：
提供硅衬底，在所述硅衬底上刻蚀形成沿垂直于所述硅衬底的方向延伸的多个硅柱，多个所述硅柱在所述硅衬底上沿列方向和行方向间隔排列形成阵列；
在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通；
在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触；
在所述凹槽中沉积金属线形成位线，每条所述位线沿着列方向延伸，并与所述隔离层接触，并且每条所述位线与对应的一列硅柱的底端连接。
在本申请的实施例中，所述硅衬底可以为单晶硅衬底。
在本申请的实施例中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，可以包括：
在所述凹槽中沉积多晶硅膜层或非晶硅膜层，通过图形化形成表面具有多晶硅膜层或非晶硅膜层的凹槽，经过图形化的多晶硅膜层或非晶硅膜层形成隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，并且，
使每个所述凹槽的内侧壁均分布有一个所述隔离层。
在本申请的实施例中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，还可以包括：
使每个所述隔离层延伸至沿列方向排列的所述硅柱下方，并且每列所述硅柱下方的所述隔离层连接在一起。
在本申请的实施例中，所述提供硅衬底，在所述硅衬底上刻蚀形成沿垂直于所述硅衬底的方向延伸的多个硅柱，可以包括：
提供硅衬底，在所述硅衬底上刻蚀出多个沿列方向延伸的沟槽，多个所述沟槽将所述硅衬底上部间隔为沿行方向间隔排列和沿列方向延伸的多个硅 壁，在所述硅衬底上沉积一层覆盖所述沟槽的介电质层；
沿垂直于所述硅衬底的方向对所述硅壁进行刻蚀，在每个所述硅壁上形成多个相互间隔的孔，多个所述孔将所述硅壁间隔为多个硅柱，每个所述硅柱依次包括源极区、沟道区和漏极区。
在本申请的实施例中，所述在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通，可以包括：
在所述硅衬底上沉积一层覆盖所述硅柱的表面的第一阻挡层，以及露出沿列方向相邻的两个所述硅柱之间的硅衬底；
对露出的所述硅衬底进行刻蚀，在每个所述孔下方形成一个向下延伸至所述硅衬底中且延伸到沿列方向相邻的两个硅柱下方的凹槽，并使每列所述孔下方的多个所述凹槽在列方向上相互连通。
在本申请的实施例中，所述在所述凹槽中沉积金属线形成位线可以包括：
在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，所述第一导电层构成所述金属线，所述金属线形成所述位线，未被所述第一导电金属反应掉的多晶硅或非晶硅形成所述隔离层。
在本申请的实施例中，所述在所述凹槽中沉积金属线形成位线，可以包括：
在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，未被所述第一导电金属反应掉的多晶硅或非晶硅形成所述隔离层；以及，在所述第一导电层表面沉积导电的第二阻挡层，并在所述凹槽的剩余部分填充第二导电金属，形成第二导电层，所述第一导电层和所述第二导电层构成所述金属线，所述金属线形成所述位线。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说 明书中变得更加清楚，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请示例性实施例的存储器的俯视结构示意图；
图2A为图1所示的存储器在a-a’截面上的纵截面结构示意图；
图2B为图1所示的存储器在b-b截面上的纵截面结构示意图；
图3A为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在b-b’截面上的纵截面结构示意图；
图3B为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在a-a’截面上的纵截面结构示意图；
图3C为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在a-a’截面上的纵截面结构示意图；
图3D为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在a-a’截面上的纵截面结构示意图；
图3E为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在a-a’截面上的纵截面结构示意图。
10-硅柱；10’-硅壁；11-源极区；12-沟道区；13-漏极区；20-位线；21-第一导电层；22-第二导电层；30-隔离层；31-第一阻挡层；32-第二阻挡层；40-衬底；50-孔；50’-凹槽；60-沟槽；70-字线；80-介电质层。
详述
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申 请中的实施例及实施例中的特征可以相互任意组合。
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本申请的宗旨及其范围的条件下被变换为各种各样的形式。因此，本申请不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请中的附图比例可以作为实际工艺中的参考，但不限于此。例如：半导体层的宽长比、各个膜层的厚度和间距，可以根据实际需要进行调整。本申请中所描述的附图仅是结构示意图，本申请的一个方式不局限于附图所示的形状或数值等。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“垂直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本申请的描述中，“第一”、“第二”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
本申请实施例提供了一种存储器，所述存储器包括多个晶体管，还包括：
衬底；
多个硅柱，与所述多个晶体管一一对应，所述硅柱位于所述衬底上；其中，多个所述硅柱沿行方向和列方向间隔排列，相邻两列硅柱之间具有沟槽； 相邻两列沟槽之间具有多个凹槽，每个所述凹槽均位于沿列方向相邻的两个所述硅柱之间的所述衬底中并在所述衬底中朝向该两个沿列方向相邻的硅柱下方的区域延伸；
多条位线，沿着列方向延伸且在行方向间隔排列，每条所述位线位于一列所述凹槽中并与所述硅柱的底端连接；所述位线为金属线；
多个隔离层，所述隔离层位于所述位线与所述凹槽的内壁之间，所述隔离层与所述衬底的至少部分区域接触；
所述衬底为单晶硅衬底，所述多个硅柱为单晶硅硅柱，所述隔离层为非晶硅膜层或多晶硅膜层。
为了实现存储器中的位线(Bit Line,BL)互连，可以采用如下方法：在形成于单晶硅衬底中的多个凹槽内采用金属和衬底中的单晶硅通过高温退火形成金属硅化物，并将多个凹槽内的金属硅化物采用“尖对尖”等方式连接在一起，形成一条位线。但因为单晶硅内部的晶向规则排布，这就导致容易在金属硅化物的形成过程中存在某一晶向的通道效应，也就是说，在退火或后续的高温工艺过程中，金属硅化物会沿着晶相有不规则的扩散(也叫热稳定性问题)，导致出现金属硅化物不规则团聚现象，影响存储器的性能。
本申请实施例的存储器在金属位线与单晶硅衬底之间引入隔离层，并且隔离层的材料选用多晶硅或非晶硅，由于多晶硅和非晶硅内部均不存在规则的晶相排布，因此当通过金属与多晶硅或非晶硅中的硅反应形成金属的硅化物来实现位线的互连时，不会出现金属的硅化物沿着晶相不规则扩散的问题，可以避免在单晶硅衬底中形成金属位线时容易出现金属的硅化物团聚的问题，提高存储器的热稳定性。
在本申请的实施例中，沿列方向相邻的两个所述硅柱之间可以具有孔，每个所述凹槽均位于一个所述孔下方的所述衬底中，并且每列所述孔下方的多个所述凹槽在列方向上相互连通。
图1为本申请示例性实施例的存储器的俯视结构示意图；图2A为图1所示的存储器在a-a’截面上的纵截面结构示意图；图2B为图1所示的存储器在b-b’截面上的纵截面结构示意图。
如图1、图2A和图2B所示，在本申请的示例性实施例中，所述存储器包括多个晶体管，还可以包括：多个硅柱10、多条位线20、多个隔离层30和衬底40；
衬底40为单晶硅衬底；
多个硅柱10与所述多个晶体管一一对应，例如，每个所述晶体管可以包括一个硅柱10；多个硅柱10均设置在衬底40上，为单晶硅硅柱；多个硅柱10沿行方向(即图1所示的b-b’方向)和列方向(即图1所示的a-a’方向)间隔排列，沿列方向相邻的两个硅柱10之间具有孔50，相邻两列硅柱10之间具有沟槽60，相邻两列沟槽60之间具有多个凹槽50’，每个凹槽50’均位于沿列方向相邻的两个硅柱10之间的衬底40中，即每个凹槽50’均位于一个孔50下方的衬底40中，并且朝向该两个沿列方向相邻的硅柱10下方的区域延伸，每列孔50下方的多个凹槽50’在列方向上可以相互连通；
多条位线20在行方向上间隔排列；每条位线20均沿列方向延伸，并且位于延伸到衬底40中的一列孔50中并与硅柱10的底端连接；位线20为金属线，所述金属线可以由含有金属元素的材料形成，例如，所述金属线可以由金属或金属的硅化物形成；示例的，孔50在垂直衬底40的方向上延伸至位线20并露出位线20；
隔离层30位于位线20与凹槽50’的内壁之间，隔离层30与衬底40的至少部分区域接触，隔离层30为多晶硅膜层或非晶硅膜层。
在本申请的实施例中，如图2A所示，每个凹槽50’的内侧壁可以均分布有一个隔离层30。
在本申请的实施例中，如图2A所示，位线20与衬底40之间可以完全不接触。
在本申请的实施例中，如图2A所示，每个隔离层30可以延伸至每列硅柱10与衬底之间的区域中。
在本申请的实施例中，如图2A所示，位线20可以由在列方向上相互连接的多个位线单元形成；
每个位线单元均设置在一个凹槽50’中。
每列孔50下方的多个凹槽50’在列方向上相互连通，使得设置在每列孔50下方的多个凹槽50’中的多个位线单元可以沿列方向连接在一起形成一条位线20。
在本申请的实施例中，所述位线的金属线可以由第一导电层形成，所述第一导电层设置在所述凹槽的内壁上。
在本申请的实施例中，如图2A和图2B所示，位线20的金属线可以由第一导电层21和第二导电层22形成，第一导电层21设置在所述凹槽的内壁上并且位于第二导电层22与隔离层30之间。
在本申请的实施例中，所述第一导电层的材料可以为导电的第一导电金属的硅化物，所述第二导电层的材料可以为第二导电金属。
在本申请的实施例中，所述第一导电金属可以选自钛、钴和镍中的任意一种或多种。
在本申请的实施例中，所述第二导电金属可以选自钨、铜和铝中的任意一种或多种。
当所述第一导电金属或所述第二导电金属包括多种材料时，所述第一导电层或所述第二导电层可以为由多种材料分别形成的多层结构。
在本申请的实施例中，如图2A和图2B所示，所述存储器还可以包括第一阻挡层31，第一阻挡层31可以设置在硅柱10的顶端的表面和侧壁的表面。
在本申请的实施例中，如图2A和图2B所示，所述存储器还可以包括导电的第二阻挡层32，第二阻挡层32设置在第一导电层21与第二导电层22之间。
在本申请的实施例中，如图2A和图2B所示，所述硅柱可以依次包括源极区11、沟道区12和漏极区13，所述源极区或所述漏极区与所述位线接触并连接。
在本申请的实施例中，所述源极区、所述沟道区、所述漏极区可以位于所述硅柱的侧壁上；示例性地，所述源极区、所述沟道区、所述漏极区可以从所述硅柱的侧壁延伸至所述硅柱内部，并且贯穿所述硅柱侧壁的相对两侧的表面。
在本申请的实施例中，所述存储器还可以包括栅极(图中未示出)，所述栅极设置在所述硅柱的侧壁上并且环绕所述侧壁的沟道区，所述栅极与所述沟道区之间设置有栅极绝缘层，所述栅极与字线连接。
在本申请的实施例中，所述存储器的一个晶体管可以包括一个硅柱、设置在该硅柱侧壁上的栅极绝缘层和栅极。
在本申请的实施例中，如图1所示，一行硅柱10一侧的所述栅极可以连接在一起形成沿行方向延伸的字线70，从而实现所述栅极与字线70的连接。
在本申请的实施例中，所述孔可以垂直于所述衬底，所述沟槽可以垂直于所述衬底。
在本申请的实施例中，所述衬底与所述第一阻挡层的刻蚀选择比较高，可以在通过刻蚀使所述孔在延伸到所述衬底中并在所述衬底中朝向沿列方向相邻的硅柱下方的区域延伸形成所述凹槽时，采用第一阻挡层保护所述硅柱的侧壁，避免所述硅柱被刻蚀掉。
例如，所述衬底与所述第一阻挡层的刻蚀选择比可以≥20；再例如，所述衬底的材料为单晶硅，所述第一阻挡层的材料可以选自氧化硅、氮化硅、氮氧化硅和碳氮化硅中的任意一种或多种。当所述第一阻挡层包括多种材料时，所述第一阻挡层可以为由多种材料分别形成的多层结构。
在本申请的实施例中，如图1所示，所述存储器的空白空间，例如，硅柱10之间的空白空间中，可以填充有介电质层。所述介电质层的材料可以选自氧化硅、氮化硅、碳氮氧化硅和碳氮化硅中的任意一种或多种。
在本申请的实施例中，所述第二阻挡层的材料可以选自氮化钛(TiN)和氮化钽(TaN)中的任意一种或多种。当所述第二阻挡层包括多种材料时，所述第二阻挡层可以为由多种材料分别形成的多层结构。
在沉积所述第二导电层时，一般先在所述凹槽上方的所述孔和所述凹槽中沉积第二导电层，然后回刻去除所述凹槽上方的所述孔中的第二导电层，仅保留所述凹槽中的第二导电层。所述第二阻挡层可以在刻蚀所述孔中多余的第二导电层时保护所述硅柱免于被刻蚀掉。
在本申请实施例中，所述硅柱在垂直于所述衬底的方向上的高度可以根 据实际的电性需求来设置，例如，可以为10nm至50nm。
在本申请的实施例中，所述栅极的材料可以为氮化钛(TiN)、铝、含铝合金；或者，
所述栅极的材料可以选自第IVA族元素形成的导体材料中的任意一种或多种，例如，所述栅极的材料可以选自多晶硅、多晶硅锗等中的任意一种或多种。
在本申请的实施例中，所述栅极绝缘层的材料可以选自氧化硅(例如，SiO 2)、氧化铪(例如，HfO 2)、氧化锆(例如，ZrO)和氧化铝(例如，Al 2O 3)中的任意一种或多种。所述栅极绝缘层可以为单层结构或多层结构，例如，可以包括由氧化硅和氧化铪形成的两层结构，其中，氧化硅层与沟道区接触，氧化铪层与栅极接触。所述栅极绝缘层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
在本申请的实施例中，所述存储器的晶体管可以为垂直环栅(Vertical gate-all-around,VGAA)晶体管；所述存储器还可以为包含晶体管的存储器件，例如，动态随机存取存储器(Dynamic Random Access Memory,DRAM)、磁性随机存取存储器(Magnetic Random Access Memory，MRAM)等。
本申请实施例还提供一种存储器的制造方法，所述制造方法包括：
提供硅衬底，在所述硅衬底上刻蚀形成沿垂直于所述硅衬底的方向延伸的多个硅柱，多个所述硅柱在所述硅衬底上沿列方向和行方向间隔排列形成阵列；
在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通；
在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触；
在所述凹槽中沉积金属线形成位线，每条所述位线沿着列方向延伸，并与所述隔离层接触，并且每条所述位线与对应的一列硅柱的底端连接。
在本申请的实施例中，所述提供硅衬底，在所述硅衬底上刻蚀形成沿垂 直于所述硅衬底的方向延伸的多个硅柱，可以包括：
提供硅衬底，在所述硅衬底上刻蚀出多个沿列方向延伸的沟槽，多个所述沟槽将所述硅衬底上部间隔为沿行方向间隔排列和沿列方向延伸的多个硅壁，在所述硅衬底上沉积一层覆盖所述沟槽的介电质层；
沿垂直于所述硅衬底的方向对所述硅壁进行刻蚀，在每个所述硅壁上形成多个相互间隔的孔，多个所述孔将所述硅壁间隔为多个硅柱，每个所述硅柱依次包括源极区、沟道区和漏极区。
在本申请的实施例中，所述在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通，可以包括：
在所述硅衬底上沉积一层覆盖所述硅柱的表面的第一阻挡层，以及露出沿列方向相邻的两个所述硅柱之间的硅衬底；
对露出的所述硅衬底进行刻蚀，在每个所述孔下方形成一个向下延伸至所述硅衬底中且延伸到沿列方向相邻的两个硅柱下方的凹槽，并使每列所述孔下方的多个所述凹槽在列方向上相互连通。
在本申请的实施例中，所述制造方法可以包括：
提供硅衬底，在所述硅衬底上刻蚀出多个沿列方向延伸的沟槽，多个所述沟槽将所述硅衬底上部间隔为沿行方向间隔排列和沿列方向延伸的多个硅壁，在所述硅衬底上沉积一层覆盖所述沟槽的介电质层；
沿垂直于所述硅衬底的方向对所述硅壁进行刻蚀，在每个所述硅壁上形成多个相互间隔的孔，多个所述孔将所述硅壁间隔为多个硅柱，每个所述硅柱依次包括源极区、沟道区和漏极区，并在所述硅衬底上沉积一层覆盖所述硅柱的表面的第一阻挡层，以及露出沿列方向相邻的两个所述硅柱之间的硅衬底；
对露出的所述硅衬底进行刻蚀，在每个所述孔下方形成一个向下延伸至所述硅衬底中且延伸到沿列方向相邻的两个硅柱下方的凹槽，并使每列所述孔下方的多个所述凹槽在列方向上相互连通；
在所述凹槽中沉积多晶硅膜层或非晶硅膜层，通过图形化形成表面具有 多晶硅膜层或非晶硅膜层的凹槽，经过图形化的多晶硅膜层或非晶硅膜层形成隔离层，使所述隔离层与所述硅衬底的至少部分区域接触；
在所述凹槽中沉积金属线形成位线，每条所述位线沿着列方向延伸，并与所述隔离层接触，并且每条所述位线与对应的一列硅柱的底端连接。
在本申请的实施例中，所述硅衬底可以为单晶硅衬底。
在本申请的实施例中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，可以包括：
在所述凹槽中沉积多晶硅膜层或非晶硅膜层，通过图形化形成表面具有多晶硅膜层或非晶硅膜层的凹槽，经过图形化的多晶硅膜层或非晶硅膜层形成隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，并且，
使每个所述凹槽的内侧壁均分布有一个所述隔离层。
在本申请的实施例中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，还可以包括：
使每个所述隔离层延伸至沿列方向排列的所述硅柱下方，并且每列所述硅柱下方的所述隔离层连接在一起。
在本申请的实施例中，所述在所述凹槽中沉积金属线形成位线可以包括：
在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅膜层或非晶硅膜层反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，所述第一导电层构成所述金属线，所述金属线形成所述位线，未被所述第一导电金属反应掉的多晶硅膜层或非晶硅膜层形成所述隔离层。
在本申请的实施例中，所述在所述凹槽中沉积金属线形成位线可以包括：
在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅膜层或非晶硅膜层反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，未被所述第一导电金属反应掉的多晶硅膜层或非晶硅膜层形成所述隔离 层；以及，
在所述第一导电层表面沉积导电的第二阻挡层，并在所述凹槽的剩余部分填充第二导电金属，形成第二导电层，所述第一导电层和所述第二导电层构成所述金属线，所述金属线形成所述位线。
在本申请的实施例中，所述使所述第一导电金属与所述隔离层中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物可以包括：通过退火工艺，使所述第一导电金属与所述隔离层中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物。
在本申请的实施例中，所述存储器的制造方法还可以包括：在形成所述第一导电金属的硅化物之后，在所述第一导电层表面沉积导电的第二阻挡层之前，采用湿法刻蚀去除未与多晶硅或非晶硅反生反应的第一导电金属。
在本申请的实施例中，所述第一导电金属为钛(Ti)，所述湿法刻蚀采用的试剂可以选为硫酸或硫酸与双氧水的混合溶液；在硫酸与双氧水的混合溶液中，以硫酸的质量分数约为98％、双氧水的质量分数约为30％计，硫酸与双氧水的体积比为2:1至10:1；湿法刻蚀的温度可以为80℃至170℃，例如，可以为80℃、90℃、100℃、110℃、120℃、130℃、140℃、150℃、160℃或170℃；刻蚀钛的速率可以为5nm/min至20nm/min，例如，可以为5nm/min、6nm/min、8nm/min、10nm/min、12nm/min、14nm/min、16nm/min、18nm/min或20nm/min。当湿法刻蚀的温度为80℃至170℃、刻蚀钛的速率为5nm/min至20nm/min时，可以更好地去除未与硅反生反应的钛，而不会腐蚀硅化钛。
在本申请的实施例中，所述存储器的制造方法还可以包括：在通过图案化去除所述凹槽中的部分所述隔离层，保留所述凹槽内壁上的所述隔离层时，对所述凹槽中的隔离层进行修整，使所述凹槽内壁上保留下来的隔离层具有期望的形状，例如，可以为碗形、椭圆形、“西格玛(Σ)形”、菱形等。
在本申请的实施例中，所述硅衬底可以为单晶硅衬底，还可以为绝缘体上半导体(Semiconductor on Insulator,SOI)衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层或其它半导体或光电材料，例如硅-锗(Si 1-xGe x，其 中x可以是例如0.2与0.8之间的摩尔分数)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP)。所述衬底可经掺杂或可未经掺杂。
图3A为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在b-b’截面上的纵截面结构示意图；图3B至图3E为本申请示例性实施例的存储器的制造方法的中间步骤得到的中间产品在a-a’截面上的纵截面结构示意图。如图2A至图3E所示，在本申请的示例性实施例中，所述存储器的制造方法可以包括：
S10：提供衬底40(本实施例中采用硅衬底)，在衬底40上刻蚀出多个沟槽60，每个沟槽60均沿列方向延伸，多个沟槽60将衬底40上部间隔为沿行方向间隔排列并沿列方向延伸的多个硅壁10’，在沟槽60中填充介电质层80，得到如图3A所示的中间产品；
沿垂直于衬底40的方向对所述硅壁10’进行刻蚀，使得在每个所述硅壁10’上形成多个相互间隔的孔50，形成在一个所述硅壁10’上的多个孔50将所述硅壁10’间隔为沿列方向间隔排列的多个硅柱10，在硅柱10的侧壁表面和顶端表面沉积第一阻挡层31，以及露出沿列方向相邻的两个硅柱10之间的衬底40，得到如图3B所示的中间产品；
S20：对露出的衬底40进行刻蚀，在每个孔50下方形成一个向下延伸至衬底40中且延伸到沿列方向相邻的两个硅柱10下方的凹槽50’，并使每列孔50下方的多个凹槽50’在列方向上相互连通，沿行方向排列的多个凹槽50’被填充在所述沟槽60中的介电质层80间隔开而互不连通；
S30：在凹槽50’和凹槽50’上方的部分孔50中沉积多晶硅膜层或非晶硅膜层，并使多晶硅膜层或非晶硅膜层，覆盖第一阻挡层31的表面，得到如图3C所示的中间产品；
S40：去除孔50中的多晶硅膜层或非晶硅膜层和凹槽50’中的部分多晶硅膜层或非晶硅膜层，保留凹槽50’内壁上的多晶硅膜层或非晶硅膜层，并通过图形化对凹槽50’中的多晶硅膜层或非晶硅膜层进行修整，使凹槽50’内壁上保留下来的多晶硅膜层或非晶硅膜层具有期望的形状，该保留下来的多晶硅膜层或非晶硅膜层形成隔离层30，示例性地，沿列方向相邻的两个凹槽50’中的隔离层30可以相连通，得到如图3D所示的中间产品；
S50：在凹槽50’的内壁上沉积第一导电金属，通过退火工艺，第一导电金属与隔离层中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物，从而在凹槽的内壁上形成由第一导电金属的硅化物形成的第一导电层21；采用湿法刻蚀去除未与多晶硅或非晶硅反生反应的第一导电金属；第一导电层与衬底40之间通过未被第一导电金属反应掉的隔离层间隔开，得到如图3E所示的中间产品；以及
在第一导电层表面沉积导电的第二阻挡层，并在凹槽50’的剩余部分填充第二导电金属，形成第二导电层，第一导电层和第二导电层构成所述金属线，并使沿列方向相邻的两个凹槽中的所述金属线相连接形成位线，得到如图2A和图2B所示的存储器。
在本申请的实施例中，所述制造方法还可以包括在所述硅柱的侧壁上依次形成栅极绝缘层和栅极，例如，可以在所述硅柱的沟道区的侧壁上依次形成栅极绝缘层和栅极。
本申请实施例如上所述的存储器可以通过如上本申请实施例提供的存储器的制造方法得到。
在本申请的实施例中，形成所述孔和所述沟槽的方法可以各自独立地选自干法刻蚀和湿法刻蚀中的任意一种或多种。
在本申请的实施例中，所述凹槽可以采用干法刻蚀和湿法刻蚀中的任意一种或多种对所述第一沟槽的下部进行侧边刻蚀形成。
在本申请的实施例中，沉积所述第一阻挡层、所述隔离层、所述第二阻挡层和所述介电质层的方法可以各自独立地选自原子层沉积(Atomic Layer Deposition,ALD)和化学气相沉积(Chemical Vapor Deposition,CVD)中的任意一种。
本申请实施例还提供一种电子设备，所述电子设备包括如上本申请实施例提供的所述存储器。
在本申请实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请 而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种存储器，包括多个晶体管，还包括：
    衬底；
    多个硅柱，与所述多个晶体管一一对应，所述硅柱位于所述衬底上；其中，多个所述硅柱沿行方向和列方向间隔排列，相邻两列硅柱之间具有沟槽；相邻两列沟槽之间具有多个凹槽，每个所述凹槽均位于沿列方向相邻的两个所述硅柱之间的所述衬底中并在所述衬底中朝向该两个沿列方向相邻的硅柱下方的区域延伸；
    多条位线，沿着列方向延伸且在行方向间隔排列，每条所述位线位于一列所述凹槽中并与所述硅柱的底端连接；所述位线为金属线；
    多个隔离层，所述隔离层位于所述位线与所述凹槽的内壁之间，所述隔离层与所述衬底的至少部分区域接触；
    所述衬底为单晶硅衬底，所述多个硅柱为单晶硅硅柱，所述隔离层为非晶硅膜层或多晶硅膜层。
  2. 根据权利要求1所述的存储器，其中，每个所述凹槽的内侧壁均分布有一个所述隔离层。
  3. 根据权利要求2所述的存储器，其中，每个所述隔离层延伸至每列所述硅柱与所述衬底之间。
  4. 根据权利要求1至3中任一项所述的存储器，其中，沿列方向相邻的两个所述硅柱之间具有孔，每个所述凹槽均位于一个所述孔下方的所述衬底中，并且每列所述孔下方的多个所述凹槽在列方向上相互连通。
  5. 根据权利要求1至3中任一项所述的存储器，其中，所述位线的金属线由第一导电层形成，所述第一导电层设置在所述凹槽的内壁上；
    其中，所述第一导电层的材料为导电的第一导电金属的硅化物。
  6. 根据权利要求1至3中任一项所述的存储器，其中，所述位线的金属线由第一导电层和第二导电层形成，所述第一导电层设置在所述凹槽的内壁上并且位于所述第二导电层与所述隔离层之间；
    其中，所述第一导电层的材料为导电的第一导电金属的硅化物，所述第二导电层的材料为第二导电金属。
  7. 根据权利要求6所述的存储器，其中，所述第一导电金属选自钛、钴和镍中的任意一种或多种；
    所述第二导电金属选自钨、铜和铝中的任意一种或多种。
  8. 根据权利要求6或7所述的存储器，还包括第一阻挡层；其中，
    所述第一阻挡层设置在所述硅柱的顶端的表面和侧壁的表面。
  9. 根据权利要求8所述的存储器，还包括导电的第二阻挡层；其中，
    所述第二阻挡层设置在所述第一导电层与所述第二导电层之间。
  10. 一种存储器的制造方法，包括：
    提供硅衬底，在所述硅衬底上刻蚀形成沿垂直于所述硅衬底的方向延伸的多个硅柱，多个所述硅柱在所述硅衬底上沿列方向和行方向间隔排列形成阵列；
    在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通；
    在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触；
    在所述凹槽中沉积金属线形成位线，每条所述位线沿着列方向延伸，并与所述隔离层接触，并且每条所述位线与对应的一列硅柱的底端连接。
  11. 根据权利要求10所述的制造方法，其中，所述硅衬底为单晶硅衬底。
  12. 根据权利要求10或11所述的制造方法，其中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，包括：
    在所述凹槽中沉积多晶硅膜层或非晶硅膜层，通过图形化形成表面具有多晶硅膜层或非晶硅膜层的凹槽，经过图形化的多晶硅膜层或非晶硅膜层形成隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，并且，
    使每个所述凹槽的内侧壁均分布有一个所述隔离层。
  13. 根据权利要求12所述的制造方法，其中，所述在所述凹槽中沉积由多晶硅膜层或非晶硅膜层形成的隔离层，使所述隔离层与所述硅衬底的至少部分区域接触，还包括：
    使每个所述隔离层延伸至沿列方向排列的所述硅柱下方，并且每列所述硅柱下方的所述隔离层连接在一起。
  14. 根据权利要求10至13中任一项所述的制造方法，其中，所述提供硅衬底，在所述硅衬底上刻蚀形成沿垂直于所述硅衬底的方向延伸的多个硅柱，包括：
    提供硅衬底，在所述硅衬底上刻蚀出多个沿列方向延伸的沟槽，多个所述沟槽将所述硅衬底上部间隔为沿行方向间隔排列和沿列方向延伸的多个硅壁，在所述硅衬底上沉积一层覆盖所述沟槽的介电质层；
    沿垂直于所述硅衬底的方向对所述硅壁进行刻蚀，在每个所述硅壁上形成多个相互间隔的孔，多个所述孔将所述硅壁间隔为多个硅柱，每个所述硅柱依次包括源极区、沟道区和漏极区。
  15. 根据权利要求14所述的制造方法，其中，所述在沿列方向相邻的两个硅柱之间的硅衬底中形成延伸到沿列方向相邻的该两个硅柱下方的凹槽，并使每列所述硅柱下方的多个所述凹槽在列方向上相互连通，包括：
    在所述硅衬底上沉积一层覆盖所述硅柱的表面的第一阻挡层，以及露出沿列方向相邻的两个所述硅柱之间的硅衬底；
    对露出的所述硅衬底进行刻蚀，在每个所述孔下方形成一个向下延伸至所述硅衬底中且延伸到沿列方向相邻的两个硅柱下方的凹槽，并使每列所述孔下方的多个所述凹槽在列方向上相互连通。
  16. 根据权利要求10至15中任一项所述的制造方法，其中，所述在所述凹槽中沉积金属线形成位线，包括：
    在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，所述 第一导电层构成所述金属线，所述金属线形成所述位线，未被所述第一导电金属反应掉的多晶硅或非晶硅形成所述隔离层。
  17. 根据权利要求10至15中任一项所述的制造方法，其中，所述在所述凹槽中沉积金属线形成位线，包括：
    在所述凹槽的内壁上沉积第一导电金属，并使所述第一导电金属与所述凹槽中的多晶硅或非晶硅反应形成导电的第一导电金属的硅化物，从而在所述凹槽的内壁上形成由所述第一导电金属的硅化物形成的第一导电层，未被所述第一导电金属反应掉的多晶硅或非晶硅形成所述隔离层；以及，在所述第一导电层表面沉积导电的第二阻挡层，并在所述凹槽的剩余部分填充第二导电金属，形成第二导电层，所述第一导电层和所述第二导电层构成所述金属线，所述金属线形成所述位线。
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CN109273456A (zh) * 2018-09-25 2019-01-25 长江存储科技有限责任公司 三维存储器的制造方法
CN109860105A (zh) * 2019-02-15 2019-06-07 长江存储科技有限责任公司 三维存储器的制造方法及三维存储器

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CN107946193A (zh) * 2017-11-23 2018-04-20 长江存储科技有限责任公司 三维存储结构制作方法、存储结构、存储器及电子设备
CN109273456A (zh) * 2018-09-25 2019-01-25 长江存储科技有限责任公司 三维存储器的制造方法
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