WO2023221352A1 - 半导体器件及其制造方法、动态随机存取存储器和电子设备 - Google Patents

半导体器件及其制造方法、动态随机存取存储器和电子设备 Download PDF

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WO2023221352A1
WO2023221352A1 PCT/CN2022/120903 CN2022120903W WO2023221352A1 WO 2023221352 A1 WO2023221352 A1 WO 2023221352A1 CN 2022120903 W CN2022120903 W CN 2022120903W WO 2023221352 A1 WO2023221352 A1 WO 2023221352A1
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layer
semiconductor
semiconductor layer
region
memory cell
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PCT/CN2022/120903
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English (en)
French (fr)
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王祥升
王桂磊
赵超
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北京超弦存储器研究院
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to but is not limited to the field of semiconductor devices, and in particular, to a semiconductor device and a manufacturing method thereof, dynamic random access memory and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • An embodiment of the present disclosure provides a semiconductor device, including:
  • a plurality of memory cell columns each of the memory cell columns includes a plurality of memory cells stacked on one side of the substrate along a first direction, and the plurality of memory cell columns are arranged along a second direction on the substrate.
  • the memory unit includes a transistor and a capacitor, the transistor includes a semiconductor layer and a gate, the semiconductor layer extends along the second direction and includes a source region, a channel region and a drain region. , the source region and the drain region are respectively located at both ends of the semiconductor layer, the channel region is located between the source region and the drain region, and the gate surrounds the Around the channel region; the capacitor surrounds one end of the drain region away from the channel region, and the channel region of the semiconductor layer is an inversion channel region;
  • bit lines extending along the first direction, and the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns along the second direction are connected to a common bit line;
  • a plurality of word lines extending along the third direction wherein the substrate is provided with a memory cell column in the third direction, and each of the word lines is composed of a memory cell of a memory cell column arranged along the third direction.
  • the gates of the transistors are formed; alternatively, the substrate is provided with a plurality of memory cell columns in a third direction, and each of the word lines is formed by connecting together the gates of the transistors of a plurality of memory cells arranged along the third direction. .
  • the semiconductor material in the channel region of the semiconductor layer may be P-type, and the semiconductor materials in the source region and drain region of the semiconductor layer may both be N-type.
  • the semiconductor material of the channel region of the semiconductor layer may be boron-doped silicon; the semiconductor materials of the source and drain regions of the semiconductor layer may both be boron- and phosphorus-doped silicon, Moreover, in the semiconductor material in the source region and drain region of the semiconductor layer, the doping concentration of phosphorus is greater than the doping concentration of boron.
  • the plurality of word lines arranged along the first direction may have different lengths and form a ladder shape.
  • the material of the word line may be any one or more of polysilicon and polysilicon germanium.
  • the capacitor may include a first electrode plate, a second electrode plate, a dielectric layer disposed between the first electrode plate and the second electrode plate, and the drain region connected to the first electrode plate.
  • the memory cell column may further include an interlayer isolation layer.
  • the interlayer isolation layer is disposed between the gates of the transistors of two adjacent memory cells in the memory cell column. The gates of the transistors of two adjacent memory cells are isolated.
  • the material of the interlayer isolation layer may be silicon oxide.
  • the transistor may further include a gate dielectric layer disposed between the channel region and the gate.
  • the material of the gate dielectric layer may be selected from any one of silicon dioxide, hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide (ZrO). or more.
  • the semiconductor device may further include one or more memory cell isolation pillars extending along a first direction, and one of the memory cell isolation pillars may be provided every two memory cell columns in the second direction. column.
  • the memory cell isolation pillar may be made of silicon oxide.
  • the semiconductor device may further include an internal support layer disposed between two adjacent semiconductor layers along the first direction and configured to provide support for the semiconductor layer.
  • the internal support layer may be located on both sides of the memory cell isolation column.
  • the material of the inner support layer may be silicon nitride (SiN).
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, including:
  • an epitaxial layer composed of a plurality of sacrificial layers and a plurality of initial semiconductor layers is stacked in the order of the sacrificial layer and the initial semiconductor layer along the first direction, and the epitaxial layer is furthest from the substrate.
  • the first layer is the sacrificial layer;
  • the remaining initial semiconductor layer forms a plurality of initial semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction, the initial semiconductor layer
  • the layer includes source regions and drain regions at both ends and a channel region between the source region and the drain region in the second direction; changing the source region and drain of the initial semiconductor layer
  • the polarity of the semiconductor material in the region is maintained, and the sacrificial layer in the word line region is used as a mask to keep the polarity of the channel region of the initial semiconductor layer unchanged, resulting in a source region, a drain region and an inversion trench.
  • a gate electrode surrounding the channel region is arranged around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and the semiconductor layer arranged in the third direction has a , so that the gate on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gates on the multiple semiconductor layers arranged in the third direction are connected together in the third direction. form word lines;
  • a capacitor surrounding one end of the drain region is provided around an end of the drain region of the semiconductor layer away from the channel region;
  • a bit line trench penetrating the semiconductor layer is provided in the bit line region of the plurality of semiconductor layers arranged along the first direction, and between the bit line trenches and the bit line trenches of the plurality of semiconductor layers arranged along the first direction. Filling the bit line material to form a bit line extending along the first direction, connecting the bit line and the source regions of the plurality of semiconductor layers in contact with the bit line, so that the source regions of the plurality of semiconductor layers are The source areas share a bit line.
  • the sacrificial layer in the non-word line area is removed, and the sacrificial layer in the word line area is retained; the remaining initial semiconductor layer forms a plurality of initial semiconductor layers arranged in an array along the first direction and the third direction and extending along the second direction.
  • a semiconductor pillar, the initial semiconductor pillar includes a source region and a drain region at both ends and a channel region between the source region and the drain region in the second direction; changing the initial semiconductor pillar
  • the polarity of the semiconductor material in the source region and drain region, and using the sacrificial layer in the word line region as a mask to keep the polarity of the channel region of the initial semiconductor pillar unchanged, obtains a source region, Semiconductor pillars in the drain region and inversion channel region; removing the sacrificial layer in the word line region may include:
  • the remaining initial semiconductor layer forms a plurality of initial semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction, the initial semiconductor layer
  • the layer includes, in the second direction, a source region and a drain region located at both ends, and a channel region located between the source region and the drain region;
  • a doping layer containing a target element is provided around the source region and drain region of the initial semiconductor layer;
  • the target element in the doped layer to diffuse into the semiconductor material in the source region and drain region of the initial semiconductor layer, so that the polarity of the semiconductor material in the source region and drain region of the initial semiconductor layer Change; and use the sacrificial layer of the word line region as a mask to keep the polarity of the channel region of the initial semiconductor layer unchanged, to obtain a semiconductor layer having a source region, a drain region and an inversion channel region; The doped layer and the sacrificial layer of the word line region are removed.
  • the material of the sacrificial layer may be silicon germanium (SiGe).
  • the semiconductor material of the source region and the drain region of the initial semiconductor layer may both be P-type, and the semiconductor material of the source region and the drain region of the semiconductor layer may both be N-type.
  • the target element may be phosphorus
  • the material of the doping layer may be selected from any one or more of phosphorus-containing oxides and phosphorus-containing nitrides.
  • defining a memory cell region in the epitaxial layer, etching a memory cell isolation trench along a first direction, and filling the memory cell isolation trench with memory cell isolation pillars may include: :
  • the memory cell isolation grooves are filled with memory cell isolation columns.
  • a gate dielectric layer and a gate electrode surrounding the channel region are sequentially arranged around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, in a third party There is one semiconductor layer arranged upward, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gate electrodes on the multiple semiconductor layers arranged in the third direction are connected together in the third direction to form word lines.
  • a gate electrode surrounding the channel region is provided around the channel region of the semiconductor pillar, thereby obtaining a plurality of transistors formed by the semiconductor pillar and the gate electrode; and, if If there is one semiconductor pillar arranged in the third direction, then the gate on this semiconductor pillar will be used as a word line; or if there are multiple semiconductor pillars arranged in the third direction, then the multiple semiconductor pillars arranged in the third direction will be used as the word line.
  • Connecting the gates on the semiconductor pillars together in a third direction to form a word line may include: setting a plurality of word lines arranged along the first direction to different lengths, so that the plurality of word lines arranged along the first direction present a step. shape.
  • a gate electrode surrounding the channel region is provided around the channel region of the semiconductor pillar, thereby obtaining a plurality of transistors formed by the semiconductor pillar and the gate electrode; and, if If there is one semiconductor pillar arranged in the third direction, then the gate on this semiconductor pillar will be used as a word line; or if there are multiple semiconductor pillars arranged in the third direction, then multiple semiconductor pillars arranged in the third direction will be used.
  • Connecting the gate electrodes on the semiconductor pillars together in the third direction to form the word line may include: arranging an interlayer isolation layer between two semiconductor layers adjacent along the first direction, thereby connecting the two adjacent semiconductor layers along the first direction. The gates on the two semiconductor layers are isolated.
  • arranging a capacitor surrounding one end of the drain region of the semiconductor pillar away from the channel region may include: placing a capacitor on the drain region of the semiconductor layer away from the channel region A first electrode plate, a dielectric layer and a second electrode plate surrounding one end of the channel region are sequentially arranged around the drain region of the semiconductor layer, thereby obtaining a capacitor surrounding the drain region of the semiconductor layer.
  • the manufacturing method may further include: opening a bit line trench penetrating the semiconductor pillars in the bit line area of the plurality of semiconductor pillars arranged along the first direction, and placing bit line trenches in the bit line trenches and along the bit line areas.
  • the bit line slots of the plurality of semiconductor pillars arranged in the first direction are filled with bit line material to form a bit line extending along the first direction, and the bit line and the plurality of semiconductor pillars in contact with the bit line are filled with bit line material.
  • an isolation material is filled in the empty space between the semiconductor layer, the bit line and the word line.
  • Embodiments of the present disclosure also provide a dynamic random access memory (dynamic random access memory), including the semiconductor device as described above.
  • dynamic random access memory dynamic random access memory
  • An embodiment of the present disclosure also provides an electronic device, including the dynamic random access memory as described above.
  • the electronic device may include a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
  • FIG. 1A is a schematic front cross-sectional structural diagram of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 1B is a schematic top structural view of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 2A is a schematic front cross-sectional structural view of a semiconductor device according to another exemplary embodiment of the present disclosure.
  • FIG. 2B is a schematic top structural view of a semiconductor device according to another exemplary embodiment of the present disclosure.
  • Figure 3 is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure
  • FIG. 4A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 4B is a schematic top structural view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • 5A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • 5B is a schematic top structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • 6A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • 6B is a schematic top structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 7A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 7B is a schematic top structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 8A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 8B is a schematic top structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure
  • 9A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • 9B is a schematic top structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure.
  • 10A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • 10B is a schematic top structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a semiconductor device.
  • 1A is a schematic front cross-sectional structural view of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 1B is a schematic top structural view of a semiconductor device according to an exemplary embodiment of the present disclosure.
  • the semiconductor device may include: a substrate 100, a plurality of memory cell columns 200, a plurality of bit lines 300 (Bit Line, BL) extending along a first direction and a plurality of bit lines 300 extending along a third direction.
  • the word line 400 (Word Line, WL) extending in the direction.
  • Each of the memory cell columns 200 includes a plurality of memory cells 1 stacked on one side of the substrate 100 along a first direction, and the plurality of memory cell columns 200 are stacked on the substrate 100 along a second direction. and the third direction to form an array;
  • the memory unit 1 includes a transistor 10 and a capacitor 20,
  • the transistor 10 includes a semiconductor layer 11 and a gate 12,
  • the semiconductor layer 11 extends along the second direction and includes a source region 111, Channel region 112 and drain region 113, the source region 111 and the drain region 113 are respectively located at both ends of the semiconductor layer 11,
  • the channel region 112 is located between the source region 111 and the Between the drain regions 113, the gate 12 surrounds the channel region 112;
  • the capacitor 20 surrounds the end of the drain region 113 away from the channel region 112;
  • the channel region 112 is an inversion channel region.
  • the source regions 111 of the transistors 10 of the plurality of memory cells 1 in the two adjacent memory cell columns 200 along the second direction are all connected to a common bit line 300 .
  • the substrate 100 may be provided with one or more memory cell columns 200 in the third direction; when the substrate 100 is provided with one memory cell column 200 in the third direction, each of the word lines 400 is formed along the third direction.
  • the gate electrode 12 of the transistor 10 of a memory cell 1 of a memory cell column 200 arranged in three directions is formed; or when the substrate 100 is provided with multiple memory cell columns 200 in a third direction, each of the words
  • the line 400 is formed by connecting together the gate electrodes 12 of the transistors 10 of the plurality of memory cells 1 arranged in the third direction.
  • first direction is defined as the direction perpendicular to the plane of the substrate, that is, the direction in which the height of the semiconductor device is located;
  • second direction is defined as the direction perpendicular to the plane of the substrate.
  • direction is perpendicular to the direction in which the width of the substrate lies;
  • third direction is defined as the direction perpendicular to the "first direction” and in which the length of the substrate lies.
  • first direction may be as shown in Figures 1A and 1B.
  • inverted channel region 112 means that the channel region 112 of the semiconductor layer and the source region 111 of the semiconductor layer have different polarities, and the channel region 112 and the source region 111 of the semiconductor layer have different polarities.
  • the drain region 113 has different polarities, and the source region 111 and the drain region 113 have the same polarity.
  • the semiconductor material of the channel region 112 of the semiconductor layer may be P-type (also called hole type), and the semiconductor materials of the source region 111 and drain region 113 of the semiconductor layer may both be N-type (also called hole type). (called electronic type), when the semiconductor device is turned on, the polarity of the channel region 112 is reversed from P-type to N-type.
  • each memory cell column is formed by a plurality of memory cells stacked on one side of the substrate along the first direction.
  • the present disclosure treats one or more memory cells belonging to the same layer as a group.
  • the group of memory cells is stacked in a direction perpendicular to the substrate, and memory cell groups of different stacks form a column extending along the direction perpendicular to the substrate.
  • the plurality of groups form an array, that is to say, the memory unit groups of each layer form an array, or multiple columns formed by multiple stacked memory unit groups form an array. It can also be expressed as: multiple memory cell columns are arranged along the second direction and the third direction to form an array.
  • the semiconductor device of the embodiment of the present disclosure arranges the semiconductor layer of the transistor to be lateral (that is, extends along the second direction), and the capacitor is arranged between the semiconductor layers of adjacent transistors instead of being arranged on the left and right sides of the transistor. Therefore, it is more A plurality of transistors and a plurality of capacitors can be stacked in the first direction to form a memory cell column with a three-dimensional stacked structure, so that more memory cells can be placed on a limited substrate surface, improving the storage density of the semiconductor device; and, The sources of the transistors of multiple memory cells in two adjacent memory cell columns in the second direction share a bit line, which can also reduce the size of the semiconductor device and further increase the storage density of the semiconductor device, thereby reducing the unit Gb.
  • the production cost provides a new technology research and development direction for shrinking the bottleneck of semiconductor devices; in addition, the channel of the transistor of the semiconductor device in the embodiment of the present disclosure adopts an inversion channel. After the semiconductor device is turned on, the pole of the channel The characteristics can be reversed, which can bring high on-state current and thus obtain high switching ratio.
  • the semiconductor material of the channel region 112 of the semiconductor layer may be boron-doped silicon, and the semiconductor material of the channel region 112 of the semiconductor layer may be P-type; the source region of the semiconductor layer
  • the semiconductor materials of the source region 111 and the drain region 113 may both be silicon doped with boron and phosphorus, and in the semiconductor materials of the source region 111 and the drain region 113 of the semiconductor layer, the doping concentration of phosphorus is much greater than that of boron. doping concentration, and the semiconductor material of the source region 111 and the drain region 113 of the semiconductor layer is N-type.
  • the semiconductor layer may be a semiconductor pillar.
  • one memory unit column may include 2 to 100 memory units.
  • it may include 2, 3 (as shown in FIGS. 1A and 1B ), 4, 5, 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage units.
  • the substrate may be provided with 2 to 1000 memory cell columns along the second direction.
  • 2 (as shown in FIGS. 1A and 1B ), 4, or 6 may be provided.
  • the substrate can be provided with 1 to 100 memory cell columns along the third direction, for example, There are 1, 2, 3 (as shown in Figure 1A and Figure 1B), 4, 5, 12, 14, 16, 18, 20, 30, 40, 50 , 60, 70, 80, 90, 100 storage unit columns.
  • the substrate may be a semiconductor substrate, for example, a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, silicon on sapphire (Silicon on Sapphire).
  • SOI semiconductor on insulator
  • SOS silicon on sapphire
  • SOG Silicon On Glass
  • silicon epitaxial layer or other semiconductor or optoelectronic material based on the base semiconductor such as silicon-germanium (Si 1-x Ge x , where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP).
  • the substrate may be doped or may be undoped.
  • the semiconductor material in the channel region of the semiconductor layer may be P-type, and the semiconductor materials in the source region and drain region of the semiconductor layer may both be N-type.
  • the semiconductor material of the channel region of the semiconductor layer may be boron-doped silicon; the semiconductor materials of the source and drain regions of the semiconductor layer may both be boron- and phosphorus-doped silicon, Moreover, in the semiconductor material in the source region and drain region of the semiconductor layer, the doping concentration of phosphorus is greater than the doping concentration of boron.
  • the lengths of the plurality of word lines arranged along the first direction may be different, so that the plurality of word lines arranged along the first direction and located at different layers may form a ladder shape.
  • the material of the word line may be a material compatible with the semiconductor layer, for example, may be selected from any one or more of polysilicon, polysilicon germanium, and the like.
  • the material of the bit line may be selected from any one or more of tungsten, molybdenum (Mo), cobalt (Co) and other metal materials with similar properties.
  • the height of the semiconductor layer along the first direction can be set according to actual electrical requirements, for example, it can be 10 nm to 50 nm.
  • the capacitor 20 may include a first electrode plate 21 and a second electrode plate 22 . 22, the drain region 113 is connected to the first electrode plate 21.
  • the second electrode plates 22 of the plurality of capacitors 20 arranged along the third direction may be connected together, but the first electrode plates 21 thereof are separated.
  • the first electrode plate 21 may be an inner electrode plate
  • the second electrode plate 22 may be an outer electrode plate.
  • one transistor 10 may correspond to one capacitor 20 , that is, the memory unit 1 may have a 1T1C structure.
  • two capacitors 20 adjacent along the first direction may share an outer electrode plate.
  • the materials of the first electrode plate 21 and the second electrode plate 22 can be independently selected from titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), etc. Any one or more other metallic materials with similar properties.
  • the thickness of the first electrode plate 21 may be 5 nm to 15 nm, and the thickness of the second electrode plate 22 may be 5 nm to 15 nm.
  • the material of the dielectric layer 23 may be a high dielectric constant (K) material, for example, it may be selected from hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), oxide Any one or more of zirconium ZrO and strontium titanate (SrTiO 3 , STO).
  • K dielectric constant
  • the thickness of the dielectric layer 23 may be 5 nm to 15 nm.
  • the memory cell column 200 may further include an interlayer isolation layer 22 , and the interlayer isolation layer 22 is disposed adjacent to the memory cell column 200 . Between the gate electrodes 12 of the transistors 10 of the two memory cells 1, the gate electrodes 12 of the transistors 10 of the two adjacent memory cells 1 are isolated.
  • the interlayer isolation layer 2 may be made of silicon oxide, for example, SiO 2 .
  • the interlayer isolation layer 2 may be an interlayer isolation tape.
  • the transistor 10 may further include a gate dielectric layer (also called a gate insulating layer, not shown in the figure), and the gate dielectric layer is disposed between the channel region 112 and the between the gates 12.
  • a gate dielectric layer also called a gate insulating layer, not shown in the figure
  • the material of the gate dielectric layer may be selected from any one of silicon dioxide, hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide ZrO, or more. Various.
  • the thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.
  • the material of the gate 12 may be selected from any one or more of polysilicon and polysilicon germanium.
  • the semiconductor device may further include one or more memory cell isolation pillars 500 extending along the first direction.
  • one memory cell isolation column 500 may be provided every two memory cell columns 200 in the second direction.
  • the material of the memory cell isolation pillar may be silicon oxide, for example, it may be selected from spin-on deposition (SOD) silicon oxide film, high density plasma (HDP) ) silicon oxide film and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide film any one or more.
  • SOD spin-on deposition
  • HDP high density plasma
  • HARP High Aspect Ratio Process
  • the semiconductor device may further include an internal support layer 600 disposed between two adjacent semiconductor layers 11 along the first direction. , configured to provide support for the semiconductor layer 11 .
  • the internal support layer 600 may also be located on both sides of the memory cell isolation pillar 500 .
  • the internal support layers 600 are provided on both sides of the memory cell isolation pillar 500, firm support can be provided for the semiconductor layer 11.
  • the material of the internal support layer may be a thin film material with a supporting function, for example, it may be silicon nitride (SiN).
  • FIG. 2A is a schematic front cross-sectional structural view of a semiconductor device according to another exemplary embodiment of the present disclosure
  • FIG. 2B is a schematic top structural view of a semiconductor device according to another exemplary embodiment of the present disclosure.
  • the empty space between the semiconductor layer, the bit line, and the word line may be filled with an isolation material 700 .
  • the isolation material may be selected from any one or more of SOD silicon oxide film, HDP silicon oxide film, and HARP silicon oxide film.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device.
  • the semiconductor device provided by the embodiment of the present disclosure as described above can be obtained by this manufacturing method.
  • FIG. 3 is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 3, the manufacturing method may include:
  • an epitaxial layer composed of a plurality of sacrificial layers and a plurality of initial semiconductor layers is stacked in the order of the sacrificial layer and the initial semiconductor layer along the first direction, and the epitaxial layer is separated from the substrate.
  • the farthest layer is the sacrificial layer;
  • S20 Define a memory cell region in the epitaxial layer, etch a memory cell isolation trench along the first direction, and fill the memory cell isolation trench with memory cell isolation pillars;
  • S30 Remove the sacrificial layer in the non-word line area and retain the sacrificial layer in the word line area; the remaining initial semiconductor layer forms a plurality of initial semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction,
  • the initial semiconductor layer includes source regions and drain regions at both ends and a channel region between the source region and the drain region in the second direction; changing the source region and the drain region of the initial semiconductor layer
  • the polarity of the semiconductor material in the drain region is determined, and the sacrificial layer in the word line region is used as a mask to keep the polarity of the channel region of the initial semiconductor layer unchanged, resulting in a source region, a drain region and an inverter region. Turn the semiconductor layer in the channel region; remove the sacrificial layer in the word line region;
  • S40 Arrange a gate surrounding the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate; and semiconductor layers arranged in a third direction. There is one, so that the gate on this one semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gates on the multiple semiconductor layers arranged in the third direction are connected in the third direction. Together they form word lines;
  • S50 Set a capacitor surrounding one end of the drain region of the semiconductor layer around one end of the drain region away from the channel region;
  • S60 Open a bit line trench penetrating the semiconductor layer in the bit line region of the plurality of semiconductor layers arranged along the first direction, and in the bit line trench and the bit line trenches of the plurality of semiconductor layers arranged along the first direction.
  • Bit line material is filled in between to form a bit line extending along the first direction, and the bit line is connected to the source regions of the plurality of semiconductor layers in contact with the bit line, so that the source regions of the plurality of semiconductor layers are The source regions share a bit line.
  • a "word line area” is defined as an area in the sacrificial layer of the memory cell area where a word line is to be formed
  • a "non-word line area” is defined as an area in the sacrificial layer of the memory cell area where a word line is not to be formed.
  • step S30 may include:
  • S31 Remove the sacrificial layer in the non-word line area, leaving the sacrificial layer in the word line area; the remaining initial semiconductor layer forms a plurality of initial semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction,
  • the initial semiconductor layer includes, in the second direction, a source region and a drain region located at both ends, and a channel region located between the source region and the drain region;
  • S33 Diffuse the target element in the doped layer into the semiconductor material in the source region and drain region of the initial semiconductor layer, so that the semiconductor material in the source region and drain region of the initial semiconductor layer The polarity is changed; and using the sacrificial layer of the word line region as a mask to keep the polarity of the channel region of the initial semiconductor layer unchanged, a semiconductor having a source region, a drain region and an inversion channel region is obtained. layer; remove the doped layer and the sacrificial layer of the word line region.
  • step S20 may include:
  • S21 Define a memory cell region in the epitaxial layer, and etch a memory cell isolation trench along the first direction;
  • S22 Perform side etching on the portion corresponding to the memory cell isolation trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support layer;
  • step S40 may include:
  • S41 Open a bit line trench penetrating the semiconductor layer in the bit line region of the plurality of semiconductor layers arranged along the first direction, and in the bit line trench and the bit line trenches of the plurality of semiconductor layers arranged along the first direction.
  • Bit line material is filled in between to form a bit line extending along the first direction, and the bit line is connected to the source regions of the plurality of semiconductor layers in contact with the bit line, so that the source regions of the plurality of semiconductor layers are The source regions share a bit line;
  • S42 Set multiple word lines arranged along the first direction to different lengths, so that the multiple word lines arranged along the first direction and located at different layers present a ladder shape;
  • S43 An interlayer isolation layer is provided between two semiconductor layers adjacent along the first direction, thereby isolating the gates on the two semiconductor layers adjacent along the first direction.
  • step S40 may include:
  • S41 Arrange a gate dielectric layer and a gate electrode surrounding the channel region in sequence around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, in There is one semiconductor layer arranged in the third direction, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gate electrodes on the multiple semiconductor layers arranged in the third direction are The gates are connected together in a third direction to form a word line;
  • step S40 may include:
  • S41 Arrange a gate dielectric layer and a gate electrode surrounding the channel region in sequence around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, in There is one semiconductor layer arranged in the third direction, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gate electrodes on the multiple semiconductor layers arranged in the third direction are The gates are connected together in a third direction to form a word line;
  • S42 Set the multiple word lines arranged along the first direction to different lengths, so that the multiple word lines arranged along the first direction and located on different layers present a ladder shape;
  • the arrangement will be along the first direction.
  • the plurality of word lines are set to different lengths, so that the plurality of word lines arranged along the first direction present a ladder shape;
  • step S40 may include:
  • S41 Arrange a gate dielectric layer and a gate electrode surrounding the channel region in sequence around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, in There is one semiconductor layer arranged in the third direction, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gate electrodes on the multiple semiconductor layers arranged in the third direction are The gates are connected together in a third direction to form a word line;
  • S43 Set an interlayer isolation layer between two adjacent semiconductor layers along the first direction to isolate the gates on the two adjacent semiconductor layers along the first direction;
  • step S40 may include:
  • S41 Arrange a gate dielectric layer and a gate electrode surrounding the channel region in sequence around the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, in There is one semiconductor layer arranged in the third direction, so that the gate electrode on this semiconductor layer serves as a word line; or, there are multiple semiconductor layers arranged in the third direction, so that the gate electrodes on the multiple semiconductor layers arranged in the third direction are The gates are connected together in a third direction to form a word line;
  • S42 Set the multiple word lines arranged along the first direction to different lengths, so that the multiple word lines arranged along the first direction and located on different layers present a ladder shape;
  • the arrangement will be along the first direction.
  • the plurality of word lines are set to different lengths, so that the plurality of word lines arranged along the first direction present a ladder shape;
  • An interlayer isolation layer is provided between two adjacent semiconductor layers along the first direction, thereby isolating the gates on the two adjacent semiconductor layers along the first direction.
  • step S50 may include: sequentially arranging a first electrode plate surrounding the drain region of the semiconductor layer, a dielectric material around an end of the drain region of the semiconductor layer away from the channel region. layer and a second electrode plate, resulting in a capacitor surrounding the drain region of said semiconductor layer.
  • the manufacturing method may further include: after step S60,
  • S70 Fill the empty space between the semiconductor layer, the bit line and the word line with an isolation material.
  • the manufacturing method of the semiconductor device may include:
  • an epitaxial layer composed of a plurality of sacrificial layers 800 and a plurality of initial semiconductor layers 11' is stacked in the order of the sacrificial layer 800 and the initial semiconductor layer 11' along the first direction, and the epitaxial layer is The layer farthest from the substrate 100 among the layers is the sacrificial layer 800, resulting in an intermediate product as shown in Figure 4A and Figure 4B;
  • S21 Define the memory cell region 1' in the epitaxial layer, and etch the memory cell isolation trench 500' along the first direction;
  • S22 Perform side etching on the portion corresponding to the memory cell isolation trench 500' and the sacrificial layer 800 along the second direction to obtain an internal support trench 600', and fill the internal support layer in the internal support trench 600'. 600;
  • the remaining initial semiconductor layer 11' forms a plurality of initial semiconductors arranged in arrays along the first direction and the third direction and extending along the second direction.
  • Layer 11" the initial semiconductor layer 11" includes a source region 111' and a drain region 113' at both ends in the second direction, between the source region 111' and the drain region 113' The channel region 112 is obtained to obtain the intermediate product as shown in Figure 6A and Figure 6B;
  • a gate dielectric layer (not shown in the figure) and a gate electrode 12 surrounding the channel region 112 are sequentially arranged around the channel region 112 of the semiconductor layer 11 to obtain a plurality of gate electrodes composed of the semiconductor layer 11 and The transistor 10 formed by the gate electrode 12; and, there is one semiconductor layer 11 arranged in the third direction, so that the gate electrode 12 on this semiconductor layer 11 serves as the word line 400; or, the semiconductor layer arranged in the third direction There are multiple 11, so that the gate electrodes 12 on the plurality of semiconductor layers 11 arranged in the third direction are connected together in the third direction to form the word line 400;
  • S42 Set the multiple word lines 400 arranged along the first direction to different lengths, so that the multiple word lines 400 arranged along the first direction and located at different layers present a ladder shape;
  • a bit line trench 300' penetrating the semiconductor layer 11 is opened in the bit line region of the plurality of semiconductor layers 11 arranged along the first direction.
  • Bit line materials are filled between the bit line trenches 300' of the semiconductor layer 11 to form a bit line 300 extending along the first direction.
  • the bit line 300 and the plurality of semiconductor layers 11 in contact with the bit line 300 are The source regions 111 are connected so that the source regions 111 of the plurality of semiconductor layers 11 share a bit line 300, thereby obtaining the semiconductor device as shown in Figure 1A and Figure 1B;
  • S70 Fill the empty space between the semiconductor layer 11, the bit line 300 and the word line 4000 with the isolation material 700 to obtain the semiconductor device as shown in FIG. 2A and FIG. 2B.
  • the material of the sacrificial layer may be any one or more of other conductive materials with similar properties such as silicon germanium (SiGe).
  • the thickness of the sacrificial layer may be 30 nm to 50 nm, for example, it may be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.
  • a super lattice thin film stack of sacrificial layer/initial semiconductor layer can be grown on the substrate through epitaxial equipment, to obtain a plurality of sacrificial layers and initial semiconductor layers. composed of epitaxial layers.
  • a sacrificial layer and an initial semiconductor layer may be regarded as an epitaxial unit, and the epitaxial layer may include multiple, for example, 32 epitaxial units.
  • the same layer of patterned photo mask can be used to perform patterning and etching through light exposure to form grooves arranged along the third direction and extending along the second direction to form multiple grooves formed by
  • the epitaxial layer formed by the sacrificial layer and the initial semiconductor layer forms an isolation in the third direction to obtain a memory cell region.
  • the memory cell isolation trench can be obtained by reactive-ion etching (RIE).
  • RIE reactive-ion etching
  • step S22 the portion of the memory cell isolation trench corresponding to the sacrificial layer may be side-etched by wet etching.
  • the internal support layer in step S22, can be filled in the internal support layer groove through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, such as , SiN can be filled in the internal support layer groove through the ALD process to form the internal support layer.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the memory cell isolation pillars can be filled in the memory cell isolation trench through SOD, HDP or HARP process.
  • the memory cell isolation pillars can be filled in the memory cell isolation trench through SOD, HDP or HARP process. Silicon oxide films are filled to form memory cell isolation pillars.
  • the sacrificial layer in the non-word line area can be etched away by using an etching method and selecting an ultra-high sacrificial layer/initial semiconductor layer etching ratio, while retaining the sacrificial layer in the word line area and the initial semiconductor layer.
  • the etching method can be dry etching or wet etching.
  • the sacrificial layer of the word line region is used as a mask to protect the channel region 112 of the initial semiconductor layer in step S30, the material of the channel region 112 of the initial semiconductor layer and the polarity has not changed, that is to say, the polarities of the initial semiconductor layer, the initial semiconductor layer, and the channel region 112 of the semiconductor layer are the same, so the initial semiconductor layer, the initial semiconductor layer , the material of the channel region 112 of the semiconductor layer is the same.
  • the semiconductor materials of the source region 111 and the drain region 113 of the initial semiconductor layer may both be P-type.
  • the source region of the initial semiconductor layer 111 and the drain region 113 are respectively transformed into the source region 111 and the drain region 113 of the semiconductor layer, so the semiconductor materials of the source region 111 and the drain region 113 of the semiconductor layer are both N-type.
  • the target element in the doping layer can be diffused into the source of the initial semiconductor layer in step S33.
  • the target element is doped into the semiconductor material of the source region 111 and the drain region 113
  • the target element is doped into the semiconductor material of the source region 111 and the drain region 113 .
  • the doping concentration of the target element is greater than the doping concentration of other doping elements.
  • the target element may be phosphorus
  • the material of the doping layer may be a phosphorus-containing oxide, for example, it may be selected from any one or more of phosphorus-containing oxides and phosphorus-containing nitrides. .
  • a doping layer containing a target element may be deposited on the surface of the source region 111 and the drain region 113 of the initial semiconductor layer through an ALD process.
  • step S33 the target element in the doping layer can be diffused into the semiconductor material of the source region 111 and the drain region 113 of the initial semiconductor layer through flash anneal.
  • the etching ratio of the source and drain regions of the ultra-highly doped layer and the semiconductor layer, and the source and drain regions of the sacrificial layer and the semiconductor layer can be selected sequentially by etching.
  • the etching ratio sequentially removes the doped layer on the surface of the source and drain regions of the semiconductor layer and the sacrificial layer of the word line region.
  • a staircase word line (staircase WL) can be obtained by trim etch.
  • the interlayer isolation layer 2 can be set through an ALD or chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • SiO 2 can be filled through an ALD or CVD process to form the interlayer isolation layer 2 .
  • the isolation material in step S70, can be filled in the blank space through SOD, HDP or HARP process.
  • an SOD silicon oxide film and an HDP silicon oxide film can be formed in the blank space through SOD, HDP or HARP process. and any one or more of HARP silicon oxide films.
  • Embodiments of the present disclosure also provide a dynamic random access memory (dynamic random access memory), including the semiconductor device as described above.
  • dynamic random access memory dynamic random access memory
  • An embodiment of the present disclosure also provides an electronic device, including the dynamic random access memory as described above.
  • the electronic device may include a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
  • connection and “arrangement” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection;
  • connection and “setting” can mean direct connection, indirect connection through an intermediary, or internal connection between two elements.
  • connection and “setting” can mean direct connection, indirect connection through an intermediary, or internal connection between two elements.

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Abstract

一种半导体器件及其制造方法、动态随机存取存储器和电子设备，半导体器件包括：衬底；多个存储单元列，每个存储单元列均包括沿第一方向堆叠设置在衬底一侧的多个存储单元，多个存储单元列在衬底上沿第二方向和第三方向排列形成阵列；存储单元包括晶体管和电容器，晶体管包括半导体层和栅极，半导体层包括源极区、反转沟道区和漏极区；多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极区均与一条共用的位线连接；多条沿第三方向延伸的字线。

Description

半导体器件及其制造方法、动态随机存取存储器和电子设备
本公开要求于2022年5月17日提交中国专利局、申请号为202210542082.7、发明名称为“一种半导体器件结构及其制造方法、DRAM和电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开涉及但不限于半导体器件领域，尤指一种半导体器件及其制造方法、动态随机存取存储器和电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，广泛应用在个人电脑、笔记本和消费电子产品中，每年的产值占整个半导体行业的30％左右。为了快速提高存储器的集成度和可扩展性，半导体器件的特征尺寸在不断缩小，但现在世界前三大DRAM公司正在进入1a技术节点，DRAM单元的尺寸较难再进一步微缩，其电容的面积随着按比例缩小(scaling down)变得越来越困难，制备工艺也越来越复杂，与逻辑器件工艺的兼容性越来越差。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本公开的保护范围。
本公开实施例提供一种半导体器件，包括：
衬底；
多个存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置在所述衬底一侧的多个存储单元，所述多个存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列；所述存储单元包括晶体管和电容器，所述晶体管 包括半导体层和栅极，所述半导体层沿第二方向延伸并且包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别位于所述半导体层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述栅极环绕在所述沟道区四周；所述电容器环绕在所述漏极区远离所述沟道区一端的四周，所述半导体层的沟道区为反转沟道区；
多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极区均与一条共用的位线连接；
多条沿第三方向延伸的字线，其中，所述衬底在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极形成；或者，所述衬底在第三方向上设置有多个存储单元列，每条所述字线由沿第三方向排列的多个存储单元的晶体管的栅极连接在一起形成。
在本公开实施例中，所述半导体层的沟道区的半导体材料可以为P型，所述半导体层的源极区和漏极区的半导体材料可以均为N型。
在本公开实施例中，所述半导体层的沟道区的半导体材料可以为掺硼的硅；所述半导体层的源极区和漏极区的半导体材料可以均为掺硼和磷的硅，并且在所述半导体层的源极区和漏极区的半导体材料中，磷的掺杂浓度均大于硼的掺杂浓度。
在本公开实施例中，沿第一方向排列的多条字线的长度可以不同，形成阶梯状。
在本公开实施例中，所述字线的材料可以为多晶硅和多晶硅锗中的任意一种或更多种。
在本公开实施例中，所述电容器可以包括第一电极板、第二电极板、设置在所述第一电极板和所述第二电极板之间的介电质层，所述漏极区与所述第一电极板相连接。
在本公开实施例中，所述存储单元列还可以包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
在本公开实施例中，所述层间隔离层的材料可以为氧化硅。
在本公开实施例中，所述晶体管还可以包括栅极介电层，所述栅极介电层设置在所述沟道区与所述栅极之间。
在本公开实施例中，所述栅极介电层的材料可以选自二氧化硅、二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆(ZrO)中的任意一种或更多种。
在本公开实施例中，所述半导体器件还可以包括一个或多个沿第一方向延伸的存储单元隔离柱，在第二方向上可以每间隔两个存储单元列设置有一个所述存储单元隔离柱。
在本公开实施例中，所述存储单元隔离柱的材料可以为氧化硅。
在本公开实施例中，所述半导体器件还可以包括内部支撑层，所述内部支撑层设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
在本公开实施例中，所述内部支撑层可以位于所述存储单元隔离柱两侧。
在本公开实施例中，所述内部支撑层的材料可以为氮化硅(SiN)。
本公开实施例还提供一种半导体器件的制造方法，包括：
在衬底一侧按照牺牲层和初始半导体层的顺序沿第一方向堆叠设置由多个牺牲层和多个初始半导体层组成的外延层，并使所述外延层中离所述衬底最远的一层为牺牲层；
在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱；
去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；改变所述初始半导体层的源极区和漏极区的半导体材料的极性，并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述字线区的牺牲层；
在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由 所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
在所述半导体层的漏极区远离所述沟道区一端的四周设置环绕所述漏极区一端的电容器；
在沿第一方向排列的多条半导体层的位线区开设贯通所述半导体层的位线槽，在所述位线槽中和沿第一方向排列的多条半导体层的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线。
在本公开实施例中，去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体柱，所述初始半导体柱在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；改变所述初始半导体柱的源极区和漏极区的半导体材料的极性，并以所述字线区的牺牲层为掩膜保持所述初始半导体柱的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体柱；去除所述字线区的牺牲层，可以包括：
去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
在所述初始半导体层的源极区和漏极区四周设置含有目标元素的掺杂层；
使所述掺杂层中的目标元素扩散到所述初始半导体层的源极区和漏极区的半导体材料中，使得所述初始半导体层的源极区和漏极区的半导体材料的极性改变；并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述掺杂层和所述字线区的牺牲层。
在本公开实施例中，所述牺牲层的材料可以为硅锗(SiGe)。
在本公开实施例中，所述初始半导体层的源极区和漏极区的半导体材料可以均为P型，所述半导体层的源极区和漏极区的半导体材料可以均为N型。
在本公开实施例中，所述目标元素可以为磷，所述掺杂层的材料可以选自含磷氧化物和含磷氮化物的任意一种或更多种。
在本公开实施例中，所述在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱可以包括：
在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽；
沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
在所述存储单元隔离槽中填充存储单元隔离柱。
在本公开实施例中，在所述半导体柱的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体柱和所述栅极形成的晶体管；以及，若在第三方向上排列的半导体柱有一条，则使这一条半导体柱上的栅极作为字线；或者，若在第三方向上排列的半导体柱有多条，则使在第三方向上排列的多条半导体柱上的栅极在第三方向上连接在一起形成字线可以包括：
在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线。
在本申请本公开实施例中，在所述半导体柱的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体柱和所述栅极形成的晶体管；以及，若在第三方向上排列的半导体柱有一条，则使这一条半导体柱上的栅极作为字线；或者，若在第三方向上排列的半导体柱有多条，则使在第三方向上排列的多条半导体柱上的栅极在第三方向上连接在一起形成字线可以包括：将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的多条 字线呈现出阶梯状。
在本申请本公开实施例中，在所述半导体柱的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体柱和所述栅极形成的晶体管；以及，若在第三方向上排列的半导体柱有一个，则使这一个半导体柱上的栅极作为字线；或者，若在第三方向上排列的半导体柱有多个，则使在第三方向上排列的多个半导体柱上的栅极在第三方向上连接在一起形成字线可以包括：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两个半导体层上的栅极隔离开。
在本公开实施例中，所述在所述半导体柱的漏极区远离所述沟道区一端的四周设置环绕所述漏极区一端的电容器可以包括：在所述半导体层的漏极区远离所述沟道区一端的四周依次设置环绕所述半导体层的漏极区的第一电极板、介电质层和第二电极板，得到环绕所述半导体层的漏极区的电容器。
在本公开实施例中，所述制造方法还可以包括：在沿第一方向排列的多条半导体柱的位线区开设贯通所述半导体柱的位线槽，在所述位线槽中和沿第一方向排列的多条半导体柱的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体柱的所述源极区连接，使得所述多条半导体柱的所述源极区共用一条位线之后，在所述半导体层、所述位线和所述字线之间的空白空间中填充隔离材料。
本公开实施例还提供了一种动态随机存取存储器(动态随机存取存储器)，包括如上所述的半导体器件。
本公开实施例还提供了一种电子设备，包括如上所述的动态随机存取存储器。
在本公开实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本公开而了解。本公开的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1A为本公开示例性实施例的半导体器件的主视剖面结构示意图；
图1B为本公开示例性实施例的半导体器件的俯视结构示意图；
图2A为本公开另一示例性实施例的半导体器件的主视剖面结构示意图；
图2B为本公开另一示例性实施例的半导体器件的俯视结构示意图；
图3为本公开实施例的半导体器件的制造方法的工艺流程简图；
图4A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图4B为本公开示例性实施例的半导体器件的制造方法的俯视结构示意图；
图5A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图5B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图；
图6A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图6B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图；
图7A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图7B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图；
图8A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图8B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图；
图9A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图9B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图；
图10A为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图10B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的俯视结构示意图。
附图中的标记符号的含义为：
100-衬底；200-存储单元列；300-位线；300’-位线槽；400-字线；500-存储单元隔离柱；500’-存储单元隔离槽；600-内部支撑层；600’-内部支撑槽；700-隔离材料；800-牺牲层；1-存储单元；1’-存储单元区；10-晶体管；11-半导体层；11’-初始半导体层；11”-初始半导体柱；111/111’-源极区；112-沟道区；113/113’-漏极区；114-掺杂层；12-栅极；20-电容器；21-第一电极板；22-第二电极板；23-介电质层；2-层间隔离层。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本公开的描述中，“第一”、“第二”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
本公开实施例提供了一种半导体器件。图1A为本公开示例性实施例的半导体器件的主视剖面结构示意图，图1B为本公开示例性实施例的半导体器件的俯视结构示意图。如图1A和图1B所示，所述半导体器件可以包括：衬底100、多个存储单元列200、多条沿第一方向延伸的位线300(Bit Line,BL) 和多条沿第三方向延伸的字线400(Word Line,WL)。
每个所述存储单元列200均包括沿第一方向堆叠设置在所述衬底100一侧的多个存储单元1，所述多个存储单元列200在所述衬底100上沿第二方向和第三方向排列形成阵列；所述存储单元1包括晶体管10和电容器20，所述晶体管10包括半导体层11和栅极12，所述半导体层11沿第二方向延伸并且包括源极区111、沟道区112和漏极区113，所述源极区111和所述漏极区113分别位于所述半导体层11的两端，所述沟道区112位于所述源极区111和所述漏极区113之间，所述栅极12环绕在所述沟道区112四周；所述电容器20环绕在所述漏极区113远离所述沟道区112一端的四周；所述半导体层11的沟道区112为反转(inversion)沟道区。
沿第二方向上相邻的两个存储单元列200的多个存储单元1的晶体管10的源极区111均与一条共用的位线300连接。
所述衬底100在第三方向上可以设置有一个或多个存储单元列200；当所述衬底100在第三方向上设置有一个存储单元列200时，每条所述字线400由沿第三方向排列的一个存储单元列200的一个存储单元1的晶体管10的栅极12形成；或者，当所述衬底100在第三方向上设置有多个存储单元列200时，每条所述字线400由沿第三方向排列的多个存储单元1的晶体管10的栅极12连接在一起形成。
在本公开的描述中，“第一方向”定义为与所述衬底所在的平面垂直的方向，即所述半导体器件的高度所在的方向；“第二方向”定义为与所述“第一方向”垂直并且所述衬底的宽度所在的方向；“第三方向”定义为与所述“第一方向”垂直并且所述衬底的长度所在的方向。“第一方向”、“第二方向”和“第三方向”可以如图1A和图1B所示。
在本公开的描述中，“反转沟道区112”是指所述半导体层的沟道区112与所述半导体层的源极区111的极性不同，沟道区112与所述半导体层的漏极区113的极性不同，源极区111和漏极区113的极性相同，当所述半导体器件导通时，所述沟道区112的极性可以发生反转。例如，所述半导体层的沟道区112的半导体材料可以为P型(又叫空穴型)，所述半导体层的源极区111和漏极区113的半导体材料可以均为N型(又叫电子型)，当所述半 导体器件导通时，所述沟道区112的极性由P型反转为N型。
在本公开的描述中，每个存储单元列均由沿第一方向堆叠设置在衬底一侧的多个存储单元形成，本公开将属于同一层的一个或多个存储单元作为一个组，该该组存储单元在垂直衬底的方向叠层设置，不同叠层的存储单元组构成沿着垂直衬底方向延伸的列。
所述的多个组构成一个阵列，也就是说每个层的存储单元组构成一个阵列，或多个叠层的存储单元组形成的多列构成一个阵列。还可以表述为：多个存储单元列沿第二方向和第三方向排列形成阵列。
本公开实施例的半导体器件将晶体管的半导体层设置为横向的(即沿第二方向延伸)，并将电容器设置在相邻晶体管的半导体层之间，而不是设置在晶体管左右两侧，因此多个晶体管和多个电容器可以在第一方向上堆叠，形成具有立体堆叠结构的存储单元列，使得在有限的衬底表面上可以设置更多的存储单元，提高了半导体器件的存储密度；而且，在第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极共用一条位线，也可以减小半导体器件的尺寸，进一步增加半导体器件的存储密度，从而减少单位Gb的制作成本，为半导体器件微缩瓶颈下，提供了一种新的技术研发方向；另外，本公开实施例的半导体器件的晶体管的沟道采用反转沟道，在半导体器件导通后沟道的极性可以发生反转，可以带来高的开态电流，从而获得高的开关比。
在本公开实施例中，所述半导体层的沟道区112的半导体材料可以为掺硼的硅，所述半导体层的沟道区112的半导体材料为P型；所述半导体层的源极区111和漏极区113的半导体材料可以均为掺硼和磷的硅，并且在所述半导体层的源极区111和漏极区113的半导体材料中，磷的掺杂浓度均远远大于硼的掺杂浓度，所述半导体层的源极区111和漏极区113的半导体材料为N型。
在本公开实施例中，所述半导体层可以为半导体柱。
在本公开实施例中，一个存储单元列可以包括2个至100个存储单元，例如，可以包括2个、3个(如图1A和图1B所示)、4个、5个、10个、13个、15个、18个、20个、30个、40个、50个、60个、70个、80个、90 个、100个存储单元。
在本公开实施例中，所述衬底沿第二方向上可以设置有2个至1000个存储单元列，例如，可以设置有2个(如图1A和图1B所示)、4个、6个、8个、10个、12个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个、200个、300个、400个、500个、600个、700个、800个、900个、1000个存储单元列；所述衬底沿第三方向上可以设置有1个至100个存储单元列，例如，可以设置有1个、2个、3个(如图1A和图1B所示)、4个、5个、12个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元列。
在本公开实施例中，所述衬底可以为半导体衬底，例如，可以为单晶硅衬底，还可以为绝缘体上半导体(Semiconductor on Insulator,SOI)衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层或其它半导体或光电材料，例如硅-锗(Si 1-xGe x，其中x可以是例如0.2与0.8之间的摩尔分数)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP)。所述衬底可经掺杂或可未经掺杂。
在本公开实施例中，所述半导体层的沟道区的半导体材料可以为P型，所述半导体层的源极区和漏极区的半导体材料可以均为N型。
在本公开实施例中，所述半导体层的沟道区的半导体材料可以为掺硼的硅；所述半导体层的源极区和漏极区的半导体材料可以均为掺硼和磷的硅，并且在所述半导体层的源极区和漏极区的半导体材料中，磷的掺杂浓度均大于硼的掺杂浓度。
在本公开实施例中，沿第一方向排列的多条字线的长度可以不同，使得沿第一方向排列的位于不同层的多条字线可以形成阶梯状。
在本公开实施例中，所述字线的材料可以为与所述半导体层兼容的材料，例如，可以选自多晶硅、多晶硅锗等中的任意一种或更多种。
在本公开实施例中，所述位线的材料可以选自钨、钼(Mo)、钴(Co)和具有相似性质的其他金属材料中的任意一种或更多种。
在本公开实施例中，所述半导体层沿第一方向上的高度可以根据实际的电性需求来设置，例如，可以为10nm至50nm。
在本公开实施例中，如图1A和图1B所示，所述电容器20可以包括第一电极板21、第二电极板22、设置在所述第一电极板21和所述第二电极板22之间的介电质层23，所述漏极区113与所述第一电极板21相连接。沿第三方向排列的多个电容器20的第二电极板22可以连接在一起，但其第一电极板21是分开的。
在本公开实施例中，如图1A和图1B所示，第一电极板21可以是内电极板、第二电极板22可以是外电极板。
在本公开实施例中，如图1A和图1B所示，一个晶体管10可以对应一个电容器20，即所述存储单元1可以为1T1C结构。
在本公开实施例中，沿第一方向相邻的两个电容器20可以共用一个外电极板。
在本公开实施例中，所述第一电极板21和所述第二电极板22的材料可以各自独立地选自氮化钛(TiN)、钛铝(TiAl)、氮化钽(TaN)等具有相似性质的其他金属材料的任意一种或更多种。所述第一电极板21的厚度可以为5nm至15nm，所述第二电极板22的厚度可以为5nm至15nm。
在本公开实施例中，所述介电质层23的材料可以为高介电常数(K)材料，例如，可以选自二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆ZrO和钛酸锶(SrTiO 3,STO)中的任意一种或更多种。所述介电质层23的厚度可以为5nm至15nm。
在本公开实施例中，如图1A和图1B所示，所述存储单元列200还可以包括层间隔离层22，所述层间隔离层22设置在所述存储单元列200中相邻的两个存储单元1的晶体管10的栅极12之间，将相邻的两个存储单元1的晶体管10的栅极12隔离开。
在本公开实施例中，所述层间隔离层2的材料可以为氧化硅，例如，可以为SiO 2。
在本公开实施例中，所述层间隔离层2可以为层间隔离带。
在本公开实施例中，所述晶体管10还可以包括栅极介电层(又叫栅极绝缘层，图中未示)，所述栅极介电层设置在所述沟道区112与所述栅极12之间。
在本公开实施例中，所述栅极介电层的材料可以选自二氧化硅、二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆ZrO中的任意一种或更多种。
在本公开实施例中，所述栅极介电层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
在本公开实施例中，所述栅极12的材料可以选自多晶硅和多晶硅锗中的任意一种或更多种。
在本公开实施例中，如图1A和图1B所示，所述半导体器件还可以包括一个或多个沿第一方向延伸的存储单元隔离柱500。例如，在第二方向上每间隔两个存储单元列200可以设置有一个所述存储单元隔离柱500。
在本公开实施例中，所述存储单元隔离柱的材料可以为氧化硅，例如，可以选自旋转涂敷(Spin-On Deposition,SOD)氧化硅薄膜、高密度等离子体(High Density Plasma,HDP)氧化硅薄膜和高深宽比工艺(High Aspect Ratio Process，HARP)氧化硅薄膜中的任意一种或更多种。
在本公开实施例中，如图1A和图1B所示，所述半导体器件还可以包括内部支撑层600，所述内部支撑层600设置在沿第一方向相邻的两个半导体层11之间，配置为对所述半导体层11提供支撑。
在本公开实施例中，如图1A和图1B所示，所述内部支撑层600还可以位于所述存储单元隔离柱500两侧。当所述存储单元隔离柱500两侧设置有内部支撑层600时可以对所述半导体层11提供牢固的支撑。
在本公开实施例中，所述内部支撑层的材料可以为具有支撑作用的薄膜材料，例如，可以为氮化硅(SiN)。
图2A为本公开另一示例性实施例的半导体器件的主视剖面结构示意图，图2B为本公开另一示例性实施例的半导体器件的俯视结构示意图。如图2A和图2B所示，在本公开示例性实施例中，所述半导体层、所述位线和所述字线之间的空白空间中可以填充有隔离材料700。
在本公开实施例中，所述隔离材料可以选自SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或更多种。
本公开实施例还提供一种半导体器件的制造方法。如上所述本公开实施例提供的半导体器件可以通过该制造方法得到。
图3为本公开实施例的半导体器件的制造方法的工艺流程简图。如图3所示，所述制造方法可以包括：
S10：在衬底一侧按照牺牲层和初始半导体层的顺序沿第一方向堆叠设置由多个牺牲层和多个初始半导体层组成的外延层，并使所述外延层中离所述衬底最远的一层为牺牲层；
S20：在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱；
S30：去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；改变所述初始半导体层的源极区和漏极区的半导体材料的极性，并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述字线区的牺牲层；
S40：在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
S50：在所述半导体层的漏极区远离所述沟道区一端的四周设置环绕所述漏极区一端的电容器；
S60：在沿第一方向排列的多个半导体层的位线区开设贯通所述半导体层的位线槽，在所述位线槽中和沿第一方向排列的多个半导体层的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接 触的多个半导体层的所述源极区连接，使得所述多个半导体层的所述源极区共用一条位线。
在本公开的描述中，“字线区”定义为存储单元区的牺牲层中待形成字线的区域，“非字线区”定义为存储单元区的牺牲层中不会形成字线的区域。
在本公开实施例中，步骤S30可以包括：
S31：去除非字线区的牺牲层，剩余字线区的牺牲层；剩余的初始半导体层形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
S32：在所述初始半导体层的源极区和漏极区四周(这里指外露的四周)设置含有目标元素的掺杂层；
S33：使所述掺杂层中的目标元素扩散到所述初始半导体层的源极区和漏极区的半导体材料中，使得所述初始半导体层的源极区和漏极区的半导体材料的极性改变；并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述掺杂层和所述字线区的牺牲层。
在本公开实施例中，步骤S20可以包括：
S21：在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽；
S22：沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S23：在所述存储单元隔离槽中填充存储单元隔离柱。
在本公开实施例中，步骤S40可以包括：
S41：在沿第一方向排列的多个半导体层的位线区开设贯通所述半导体层的位线槽，在所述位线槽中和沿第一方向排列的多个半导体层的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得所述多个半导体层的所述源极区共用一条位线；
任选地，S42：将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
任选地，S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两个半导体层上的栅极隔离开。
例如，在本公开示例性实施例中，i)步骤S40可以包括：
S41：在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
或者，ii)步骤S40可以包括：
S41：在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
S42：将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
任选地，在使一个半导体层上的栅极作为字线或者使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线之后，将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的多条字线呈现出阶梯状；
或者，iii)步骤S40可以包括：
S41：在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两个半导体层上的栅极隔离开；
或者，iiii)步骤S40可以包括：
S41：在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
S42：将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的位于不同层的多条字线呈现出阶梯状；
任选地，在使一个半导体层上的栅极作为字线或者使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线之后，将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的多条字线呈现出阶梯状；
S43：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两个半导体层上的栅极隔离开。
在本公开实施例中，步骤S50可以包括：在所述半导体层的漏极区远离所述沟道区一端的四周依次设置环绕所述半导体层的漏极区的第一电极板、介电质层和第二电极板，得到环绕所述半导体层的漏极区的电容器。
在本公开实施例中，所述制造方法还可以包括：在步骤S60之后，
S70：在所述半导体层、所述位线和所述字线之间的空白空间中填充隔离材料。
图4A至图10B为本公开示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图和俯视结构示意图。如图4A至图10B所示，在示例性实施例中，所述半导体器件的制造方法可以包括：
S10：在衬底100一侧按照牺牲层800和初始半导体层11’的顺序沿第一方向堆叠设置由多个牺牲层800和多个初始半导体层11’组成的外延层，并使所述外延层中离所述衬底100最远的一层为牺牲层800，得到如图4A和图 4B所示的中间品；
S21：在所述外延层中定义出存储单元区1’，并沿第一方向刻蚀出存储单元隔离槽500’；
S22：沿第二方向对所述存储单元隔离槽500’与所述牺牲层800对应的部分进行侧边刻蚀，得到内部支撑槽600’，在所述内部支撑槽600’中填充内部支撑层600；
S23：在所述存储单元隔离槽500’中填充存储单元隔离柱500，得到如图5A和图5B所示的中间品；
S31：去除非字线区的牺牲层800，保留字线区的牺牲层800；剩余的初始半导体层11’形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层11”，所述初始半导体层11”在第二方向上包括位于两端的源极区111’和漏极区113’、位于所述源极区111’和所述漏极区113’之间的沟道区112，得到如图6A和图6B所示的中间品；
S32：在所述初始半导体层11”的源极区111’和漏极区113’外露的四周设置含有目标元素的掺杂层114，得到如图7A和图7B所示的中间品；
S33：使所述掺杂层114中的目标元素扩散到所述初始半导体层11”的源极区111’和漏极区113’的半导体材料中，使得所述初始半导体层11”的源极区111’和漏极区113’的半导体材料的极性改变；并以所述字线区的牺牲层800为掩膜保持所述初始半导体层11”的沟道区112的极性不变，得到具有源极区111、漏极区113和反转沟道区112的半导体层11；去除所述掺杂层114和所述字线区的牺牲层800，得到如图8A和图8B所示的中间品；
S41：在所述半导体层11的沟道区112四周依次设置环绕所述沟道区112的栅极介电层(图中未示)和栅极12，得到多个由所述半导体层11和所述栅极12形成的晶体管10；以及，在第三方向上排列的半导体层11有一个，使这一个半导体层11上的栅极12作为字线400；或者，在第三方向上排列的半导体层11有多个，使在第三方向上排列的多个半导体层11上的栅极12在第三方向上连接在一起形成字线400；
S42：将沿第一方向排列的多条字线400设置为不同的长度，使得沿第 一方向排列的位于不同层的多条字线400呈现出阶梯状；
S43：在沿第一方向上相邻的两个半导体层11之间设置层间隔离层2，从而将沿第一方向上相邻的两个半导体层11上的栅极12隔离开，得到如图9A和图9B所示的中间品；
S50：在所述半导体层11的漏极区113远离所述沟道区112一端的四周依次设置环绕所述半导体层11的漏极区113的第一电极板21、介电质层23和第二电极板22，得到环绕所述半导体层11的漏极区113的电容器20，得到如图10A和图10B所示的中间品；
S60：在沿第一方向排列的多条半导体层11的位线区开设贯通所述半导体层11的位线槽300’，在所述位线槽300’中和沿第一方向排列的多条半导体层11的位线槽300’之间填充位线材料，形成沿第一方向延伸的位线300，将所述位线300和与该位线300相接触的多条半导体层11的所述源极区111连接，使得所述多条半导体层11的所述源极区111共用一条位线300，得到如图1A和图1B所示的半导体器件；
S70：在所述半导体层11、所述位线300和所述字线4000之间的空白空间中填充隔离材料700，得到如图2A和图2B所示的半导体器件。
在本公开实施例中，所述牺牲层的材料可以为硅锗(SiGe)等具有相似性质的其他导电材料中的任意一种或更多种。所述牺牲层的厚度可以为30nm至50nm，例如，可以为30nm、35nm、40nm、45nm、50nm。
在本公开实施例中，步骤S10中可以通过外延设备在所述衬底上生长出牺牲层/初始半导体层的超晶格(super lattice)薄膜堆叠层，得到多个由牺牲层和初始半导体层组成的外延层。
在本公开实施例中，步骤S10中，可以将一个牺牲层和一个初始半导体层看成一个外延单元，所述外延层可以包括多个，例如，32个外延单元。
在本公开实施例中，步骤S21中可以利用同一层图案光罩(Photo mask)通过光照曝光进行图案化刻蚀，形成沿第三方向排列并沿第二方向延伸的沟槽从而将多个由牺牲层和初始半导体层形成的外延层在第三方向上形成隔离，得到存储单元区。
在本公开实施例中，步骤S21中可以通过反应离子刻蚀(Reactive-Ion Etch,RIE)得到存储单元隔离槽。
在本公开实施例中，步骤S22中，可以通过湿法刻蚀对所述存储单元隔离槽的与所述牺牲层对应的部分进行侧边刻蚀。
在本公开实施例中，步骤S22中，可以通过原子层沉积(Atomic layer deposition,ALD)工艺或化学气相沉积(Chemical Vapor Deposition,CVD)工在所述内部支撑层槽中填充内部支撑层，例如，可以通过ALD工艺在所述内部支撑层槽中填充SiN，形成内部支撑层。
在本公开实施例中，步骤S23中可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充存储单元隔离柱，例如，可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充氧化硅薄膜从而形成存储单元隔离柱。
在本公开实施例中，步骤S31中可以通过刻蚀法、选择超高牺牲层/初始半导体层刻蚀比将非字线区的牺牲层刻蚀掉而保留字线区的牺牲层和初始半导体层，所述刻蚀法可以为干法刻蚀或湿法刻蚀。
在本公开实施例中，由于步骤S30中采用所述字线区的牺牲层为掩膜对所述初始半导体层的沟道区112进行保护，因此所述初始半导体层的沟道区112的材料和极性没有发生变化，也就是说所述初始半导体层、所述初始半导体层、所述半导体层的沟道区112的极性是相同的，因此所述初始半导体层、所述初始半导体层、所述半导体层的沟道区112的材料是相同的。
在本公开实施例中，所述初始半导体层的源极区111和漏极区113的半导体材料可以均为P型，经过步骤S30中的极性改变后，所述初始半导体层的源极区111和漏极区113分别转化为所述半导体层的源极区111和漏极区113，因此所述半导体层的源极区111和漏极区113的半导体材料均为N型。
为了将所述初始半导体层的源极区111和漏极区113的半导体材料由P型改变为N型，可以在步骤S33中将掺杂层中的目标元素扩散到所述初始半导体层的源极区111和漏极区113的半导体材料中，从而将目标元素掺杂到源极区111和漏极区113的半导体材料中，并且使在源极区111和漏极区113的半导体材料中，目标元素的掺杂浓度大于其他掺杂元素的掺杂浓度。
在本公开实施例中，所述目标元素可以为磷，所述掺杂层的材料可以为含磷氧化物，例如可以选自含磷氧化物和含磷氮化物的任意一种或更多种。
在本公开实施例中，步骤S32中可以通过ALD工艺在所述初始半导体层的源极区111和漏极区113表面沉积一层含有目标元素的掺杂层。
在本公开实施例中，步骤S33中可以通过快速退火(flash anneal)使所述掺杂层中的目标元素扩散到所述初始半导体层的源极区111和漏极区113的半导体材料中。
在本公开实施例中，步骤S33中可以通过刻蚀法依次选择超高掺杂层与半导体层的源极区和漏极区刻蚀比、牺牲层与半导体层的源极区和漏极区刻蚀比依次去除所述半导体层的源极区和漏极区表面的掺杂层和所述字线区的牺牲层。
在本公开实施例中，步骤S42中可以通过修整刻蚀(trim etch)得到阶梯状字线(staircase WL)。
在本公开实施例中，步骤S43中可以通过ALD或化学气相沉积(Chemical Vapor Deposition,CVD)工艺设置层间隔离层2，例如，可以通过ALD或CVD工艺填充SiO 2，形成层间隔离层2。
在本公开实施例中，步骤S70中可以通过SOD、HDP或HARP工艺在空白空间中填充隔离材料，例如，可以通过SOD、HDP或HARP工艺在空白空间中形成SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或更多种。
本公开实施例还提供了一种动态随机存取存储器(动态随机存取存储器)，包括如上所述的半导体器件。
本公开实施例还提供了一种电子设备，包括如上所述的动态随机存取存储器。
在本公开实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
在本公开中的描述中，需要说明的是，术语“上”、“下”、“一侧”、“另一侧”、“一端”、“另一端”等指示的方位或位置关系为基于附图所 示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的结构具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，除非另有明确的规定和限定，术语“连接”、“设置”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；术语“连接”、“设置”可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (29)

  1. 一种半导体器件，包括：
    衬底；
    多个存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置在所述衬底一侧的多个存储单元，所述多个存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列；所述存储单元包括晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸并且包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别位于所述半导体层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述栅极环绕在所述沟道区四周；所述电容器环绕在所述漏极区远离所述沟道区一端的四周，所述半导体层的沟道区为反转沟道区；
    多条沿第一方向延伸的位线，沿第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极区均与一条共用的位线连接；
    多条沿第三方向延伸的字线，其中，所述衬底在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极形成；或者，所述衬底在第三方向上设置有多个存储单元列，每条所述字线由沿第三方向排列的多个存储单元的晶体管的栅极连接在一起形成。
  2. 根据权利要求1所述的半导体器件，其中，所述半导体层的沟道区的半导体材料为P型，所述半导体层的源极区和漏极区的半导体材料均为N型。
  3. 根据权利要求2所述的半导体器件，其中，所述半导体层的沟道区的半导体材料为掺硼的硅；所述半导体层的源极区和漏极区的半导体材料均为掺硼和磷的硅，并且在所述半导体层的源极区和漏极区的半导体材料中，磷的掺杂浓度均大于硼的掺杂浓度。
  4. 根据权利要求1所述的半导体器件，其中，沿第一方向排列的多条字线的长度不同，形成阶梯状。
  5. 根据权利要求4所述的半导体器件，其中，所述字线的材料为多晶硅和多晶硅锗中的任意一种或更多种。
  6. 根据权利要求1至5中任一项所述的半导体器件，其中，所述电容器包括第一电极板、第二电极板、设置在所述第一电极板和所述第二电极板之间的介电质层，所述漏极区与所述第一电极板相连接。
  7. 根据权利要求1至6中任一项所述的半导体器件，其中，所述存储单元列还包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
  8. 根据权利要求7所述的半导体器件，其中，所述层间隔离层的材料为氧化硅。
  9. 根据权利要求1至8中任一项所述的半导体器件，其中，所述晶体管还包括栅极介电层，所述栅极介电层设置在所述沟道区与所述栅极之间。
  10. 根据权利要求9所述的半导体器件，其中，
    所述栅极介电层的材料选自二氧化硅、二氧化铪、氧化锆和氧化铝中的任意一种或多种。
  11. 根据权利要求1至10中任一项所述的半导体器件，其中，还包括一个或多个沿第一方向延伸的存储单元隔离柱，在第二方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
  12. 根据权利要求11项所述的半导体器件，其中，所述存储单元隔离柱的材料为氧化硅。
  13. 根据权利要求11或12所述的半导体器件，其中，所述半导体器件还包括内部支撑层，所述内部支撑层设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
  14. 根据权利要求13所述的半导体器件，其中，所述内部支撑层位于所述存储单元隔离柱两侧。
  15. 根据权利要求13或14所述的半导体器件，其中，所述内部支撑层的材料为SiN。
  16. 一种半导体器件的制造方法，包括：
    在衬底一侧按照牺牲层和初始半导体层的顺序沿第一方向堆叠设置由多 个牺牲层和多个初始半导体层组成的外延层，并使所述外延层中离所述衬底最远的一层为牺牲层；
    在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱；
    去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；改变所述初始半导体层的源极区和漏极区的半导体材料的极性，并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述字线区的牺牲层；
    在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线；
    在所述半导体层的漏极区远离所述沟道区一端的四周设置环绕所述漏极区一端的电容器；
    在沿第一方向排列的多个半导体层的位线区开设贯通所述半导体层的位线槽，在所述位线槽中和沿第一方向排列的多个半导体层的位线槽之间填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得所述多个半导体层的所述源极区共用一条位线。
  17. 根据权利要求16所述的制造方法，其中，所述去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；改变所述初始半导体层的源极区和漏极区的半导体材料的极性，并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变， 得到具有源极区、漏极区和反转沟道区的半导体层；去除所述字线区的牺牲层还包括：
    去除非字线区的牺牲层，保留字线区的牺牲层；剩余的初始半导体层形成多个沿第一方向和第三方向阵列排列并且沿第二方向延伸的初始半导体层，所述初始半导体层在第二方向上包括位于两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
    在所述初始半导体层的源极区和漏极区四周设置含有目标元素的掺杂层；
    使所述掺杂层中的目标元素扩散到所述初始半导体层的源极区和漏极区的半导体材料中，使得所述初始半导体层的源极区和漏极区的半导体材料的极性改变；并以所述字线区的牺牲层为掩膜保持所述初始半导体层的沟道区的极性不变，得到具有源极区、漏极区和反转沟道区的半导体层；去除所述掺杂层和所述字线区的牺牲层。
  18. 根据权利要求16或17所述的制造方法，其中，
    所述牺牲层的材料为硅锗。
  19. 根据权利要求16或17所述的制造方法，其中，
    所述初始半导体层的源极区和漏极区的半导体材料均为P型，所述半导体层的源极区和漏极区的半导体材料均为N型。
  20. 根据权利要求17所述的制造方法，其中，所述目标元素为磷，所述掺杂层的材料选自含磷氧化物和含磷氮化物的任意一种或更多种。
  21. 根据权利要求16所述的制造方法，其中，所述在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽，以及在所述存储单元隔离槽中填充存储单元隔离柱，包括：
    在所述外延层中定义出存储单元区，并沿第一方向刻蚀出存储单元隔离槽；
    沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
    在所述存储单元隔离槽中填充存储单元隔离柱。
  22. 根据权利要求16所述的制造方法，其中，所述在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线，包括：
    在所述半导体层的沟道区四周依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线。
  23. 根据权利要求22所述的制造方法，其中，所述在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线，还包括：在使一个半导体层上的栅极作为字线或者使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线之后，将沿第一方向排列的多条字线设置为不同的长度，使得沿第一方向排列的多条字线呈现出阶梯状。
  24. 根据权利要求22所述的制造方法，其中，所述在所述半导体层的沟道区四周设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一个，使这一个半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多个，使在第三方向上排列的多个半导体层上的栅极在第三方向上连接在一起形成字线，还包括：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两个半导体层上的栅极隔离开。
  25. 根据权利要求16至24中任一项所述的制造方法，其中，所述在所述半导体层的漏极区远离所述沟道区一端的四周设置环绕所述漏极区一端的 电容器包括：在所述半导体层的漏极区远离所述沟道区一端的四周依次设置环绕所述半导体层的漏极区的第一电极板、介电质层和第二电极板，得到环绕所述半导体层的漏极区的电容器。
  26. 根据权利要求16至25中任一项所述的制造方法还包括：在形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得所述多个半导体层的所述源极区共用一条位线之后，在所述半导体层、所述位线和所述字线之间的空白空间中填充隔离材料。
  27. 一种动态随机存取存储器，包括根据权利要求1至15中任一项所述的半导体器件。
  28. 一种电子设备，包括根据权利要求27所述的动态随机存取存储器。
  29. 根据权利要求28所述的电子设备，包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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